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1. 发明申请

WO2016201239A1 POWER MANAGER WITH A POWER SWITCH ARBITER 审中-公开
标题翻译：电源管理器与电源开关ARBITER
公开(公告)号：WO2016201239A1
公开(公告)日：2016-12-15
申请号：PCT/US2016/036906
申请日：2016-06-10
申请人： SONICS, INC.
发明人： EHMANN, Gregory , WINGARD, Drew, E. , WINGEN, Neal, T.
IPC分类号： G06F1/26
CPC分类号： G06F1/3287 , G06F1/3228 , G06F1/329 , G06F9/4403 , G06F13/37 , G06F13/4031 , Y02D10/151 , Y02D10/171 , Y02D10/24
摘要： An arbitrator governs an arbitration between different power domains and sequences powering up the different power domains supplied by the same voltage supply (VS) circuit on the Chip, The arbitrator sequencing logic limits how many different power domains simultaneously power up to a maximum amount, which is less than enough instantaneous electrical current drawn on the VS-circuit to cause a reduction below a minimum allowable supply voltage level for the VS-circuit, The sequencing logic manages the sequencing of powering up the different power domains by factoring in i) whether different power domains arbitrating to power up are part of a set of power domains that share the VS-circuit, ii) an amount of an instantaneous eiectricai current drawn, and iii) an amount of credits available before the minimum allowable supply voltage level occurs for that VS-circuit. The sequencing logic controls behavior of power domains when powering up from multiple different behaviors.
摘要翻译：仲裁员控制不同功率域之间的仲裁，并对由芯片上的相同电源（VS）电路提供的不同功率域供电的序列进行管理。仲裁器排序逻辑限制了多少不同的功率域同时上电达到最大量，小于在VS电路上画出的足够的瞬时电流，导致低于VS电路的最小可允许电源电压电平。排序逻辑通过考虑因素来管理对不同功率域供电的顺序i）是否不同仲裁加电的功率域是共享VS电路的一组电源域的一部分，ii）所绘制的瞬时电流电流的量，以及iii）在发生最小允许电源电压电平之前可用的信用量 VS-电路。排序逻辑控制从多个不同行为上电时电源域的行为。

2. 发明申请

WO2004095296A3 A METHOD AND APPARATUS FOR ROUND ROBIN RESOURCE ARBITRATION 审中-公开
标题翻译： ROBIN资源仲裁的方法和装置
公开(公告)号：WO2004095296A3
公开(公告)日：2005-03-03
申请号：PCT/US2004011943
申请日：2004-04-16
申请人： SONICS INC
发明人： MEYER MICHAEL J , WINGARD DREW , WEBER WOLF-DIETRICH
IPC分类号： G06F13/00 , G06F13/14 , G06F13/37
CPC分类号： G06F13/37
摘要： A method and apparatus for a round robin resource arbitration scheme is described. An apparatus to provide round robin token arbitration comprises at least two token arbiters, each token arbiter associated with a node to which at least two sub-trees are connected, each sub-tree comprising a token arbiter or a finite state machine requestor.
摘要翻译：描述了一种用于循环资源仲裁方案的方法和装置。提供循环令牌仲裁的装置包括至少两个令牌仲裁器，每个令牌仲裁器与连接有至少两个子树的节点相关联，每个子树包括令牌仲裁器或有限状态机请求者。

3. 发明申请

WO1998032063A2 METHOD AND APPARATUS FOR ZERO LATENCY BUS TRANSACTIONS 审中-公开
标题翻译：零延迟总线交易的方法和装置
公开(公告)号：WO1998032063A2
公开(公告)日：1998-07-23
申请号：PCT/US1997022147
申请日：1997-12-03
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , JAYAKUMAR, Muthurajan , HUANG, Sunny, C. , MACWILLIAMS, Peter, D. , WU, William, S. , PAWLOWSKI, Stephen , PRASAD, Bindi, A.
IPC分类号： G06F00/00
CPC分类号： G06F13/37 , G06F13/4252
摘要： A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase.
摘要翻译：计算机系统中的分流事务总线，其允许使用附加总线以流水线方式进行无序回复以用于响应阶段。

4. 发明申请

WO1996007970A1 METHOD AND APPARATUS FOR PERFORMING DEFERRED TRANSACTIONS 审中-公开
标题翻译：执行延期交易的方法和装置
公开(公告)号：WO1996007970A1
公开(公告)日：1996-03-14
申请号：PCT/US1995011315
申请日：1995-09-08
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , SARANGDHAR, Nitin, V. , LAI, Konrad, K. , SINGH, Gurbir , MACWILLIAMS, Peter, D.
IPC分类号： G06F13/14
CPC分类号： G06F13/37 , G06F13/368 , G06F13/4213
摘要： A method and apparatus for performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens (302) between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.
摘要翻译：一种用于在计算机系统的总线上执行总线事务的方法和装置。本发明包括一种用于允许流水线总线系统中的无序回复的方法和装置。无序响应包括在计算机系统中的请求代理和响应代理之间发送令牌（302），而不使用专用令牌总线。

5. 发明申请

WO1994015302A1 METHOD AND APPARATUS FOR ARBITRATING ON AN ACYCLIC DIRECTED GRAPH 审中-公开
标题翻译：用于在ACYCLIC导向图上进行仲裁的方法和装置
公开(公告)号：WO1994015302A1
公开(公告)日：1994-07-07
申请号：PCT/US1993012311
申请日：1993-12-16
申请人： APPLE COMPUTER, INC.
发明人： APPLE COMPUTER, INC. , OPRESCU, Florin
IPC分类号： G06F15/16
CPC分类号： H04L12/40078 , G06F13/36 , G06F13/37 , G06F15/17343 , H04L12/40084 , H04L45/48
摘要： A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph. The hierarchical arrangement of nodes has one node designated a root while all other nodes have established parent/child relationships with the nodes to which they are linked. Each node may have a plurality of connected child ports with a predetermined acknowledgment priority scheme established. Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. The root node may always assert its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer. Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme. Preemptive bus initialization may be triggered by any node upon detection of a necessitating error or addition or removal of a connection to an existing node.
摘要翻译：总线仲裁方案在系统中实现，其中系统总线上的节点的任意组合已被解析成非循环有向图。节点的分层排列有一个节点被指定为根，而所有其他节点已经与它们所链接的节点建立了父/子关系。每个节点可以具有建立具有预定的确认优先级方案的多个连接的子端口。公平总线访问仲裁以对应于预定端口优先级的顺序提供总线授予，允许所有节点在总线上转向。根节点可以总是声明其优先访问状态以获得总线访问，这对于容纳需要等时数据传输的根节点很有用。或者，可以实现令牌通过仲裁方案，其中根据上述预定端口优先级方案，总线访问令牌围绕节点传递。在检测到必要的错误或添加或删除到现有节点的连接时，可以由任何节点触发先占总线初始化。

6. 发明申请

WO1984004185A1 BUS REPEATER 审中-公开
标题翻译：总线重复
公开(公告)号：WO1984004185A1
公开(公告)日：1984-10-25
申请号：PCT/US1984000556
申请日：1984-04-12
申请人： CONVERGENT TECHNOLOGIES, INC.
发明人： CONVERGENT TECHNOLOGIES, INC. , BURGER, John, P.
IPC分类号： G06F03/00
CPC分类号： G06F13/4045 , G06F13/37 , G06F13/4031 , H05K1/14
摘要： Method and apparatus for allowing multiple enclosures (10) to be connected so that their respective motherboards (15) together define a single bus. Systemwide arbitration is carried out asynchronously on an enclosure basis while arbitration within each enclosure occurs synchronously. A bus repeater (20, 25, 25') is provided at each of the upstream and downstream ends of each enclosure's motherboard. The upstream bus repeater (20) in a given enclosure is coupled by a flexible connector cable (30) to the downstream bus repeater (25, 25') in the enclosure immediately upstream. One of the bus repeaters (say the upstream one) has the status as master or arbiter while the other has a status of a slave. The connector cables have two sets of lines (32, 35), thereby allowing the bus repeaters to pass two basic types of signals: (a) bused signals (address, data) which are made available to the relevant unit boards; and (b) private signals which are passed only to the bus repeaters. The set of private signals comprises two subsets (i) downstream bound, and (ii) upstream bound, each subset of which includes request, busy, grant, and arbitrate signals. Within each enclosure, the bus repeaters monitor the local bus request and bus busy lines, and logically combine them with the upstream bound and downstream bound private request and busy signals.

7. 发明申请

WO2018156379A1 POWER AWARE ARBITRATION FOR BUS ACCESS 审中-公开
公开(公告)号：WO2018156379A1
公开(公告)日：2018-08-30
申请号：PCT/US2018/017905
申请日：2018-02-13
申请人： QUALCOMM INCORPORATED
发明人： SHIRLEN, Martyn
IPC分类号： G06F13/16 , G06F13/38
CPC分类号： G06F13/37 , G06F13/1663 , G06F13/385 , H03M13/19 , Y02D10/14 , Y02D10/151
摘要： Systems and methods for operating a bus interface unit include queues for receiving and storing one or more words from one or more agents for transmission on to a data bus. From at least a subset of the one or more words, a next word which will cause the least switching power among the subset of the one or more words when transmitted on to the data bus is determined and the next word is selected for transmission on to the data bus, to reduce dynamic power consumption of the data bus. The next word may be selected as a word among the subset of the one or more words with a least Hamming distance from a current word scheduled for transmission on to the data bus.

8. 发明申请

WO03009148A3 METHOD AND APPARATUS FOR POSITION DEPENDENT DATA SCHEDULING 审中-公开
标题翻译：用于位置依赖数据调度的方法和装置
公开(公告)号：WO03009148A3
公开(公告)日：2003-05-01
申请号：PCT/US0222534
申请日：2002-07-15
申请人： RAMBUS INC
发明人： HAMPEL CRAIG
IPC分类号： G06F13/36 , G06F13/37
CPC分类号： G06F13/36 , G06F13/37
摘要： A method and apparatus for position dependent data scheduling for communication of data for different domains along a bus is provided. Having an awareness of the relative position of different domains along a bus, one embodiment of the invention schedules bus operations to allow data from multiple bus operations to be simultaneously present on the bus while preventing interference among the data. The invention is compatible with buses having a termination on one end and those having terminations on both ends. In accordance with one embodiment of the invention, bus operations are scheduled so that first data of a first bus operation involving a first domain are not present at domains involved in a second bus operation at times that would result in interference with second data of the second bus operation.
摘要翻译：提供了一种用于位置相关数据调度的方法和装置，用于沿总线对不同域的数据进行通信。了解沿着总线的不同域的相对位置，本发明的一个实施例调度总线操作以允许来自多个总线操作的数据同时存在于总线上，同时防止数据之间的干扰。本发明与在一端具有端接的总线和在两端具有端接的总线兼容。根据本发明的一个实施例，调度总线操作，使得涉及第一域的第一总线操作的第一数据不存在于涉及第二总线操作的域处，这将导致对第二总线操作的第二数据的干扰巴士操作。

9. 发明申请

WO9832063A3 METHOD AND APPARATUS FOR ZERO LATENCY BUS TRANSACTIONS 审中-公开
标题翻译：零延迟总线交易的方法和装置
公开(公告)号：WO9832063A3
公开(公告)日：1999-03-18
申请号：PCT/US9722147
申请日：1997-12-03
申请人： INTEL CORP
发明人： JAYAKUMAR MUTHURAJAN , HUANG SUNNY C , MACWILLIAMS PETER D , WU WILLIAM S , PAWLOWSKI STEPHEN , PRASAD BINDI A
IPC分类号： G06F13/37 , G06F13/42 , G06F
CPC分类号： G06F13/37 , G06F13/4252
摘要： A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase.

10. 发明申请

WO1987007459A1 COMMUNICATION PROTOCOL FOR A NETWORK 审中-公开
标题翻译：网络通信协议
公开(公告)号：WO1987007459A1
公开(公告)日：1987-12-03
申请号：PCT/AU1987000158
申请日：1987-05-29
申请人： LAOCON CONTROL TECHNOLOGY LIMITED , VASKOVICS, George , GALLAI, Steve , RAKOCZY, Istvan
发明人： LAOCON CONTROL TECHNOLOGY LIMITED
IPC分类号： H04L11/16
CPC分类号： H04L12/433 , G06F11/0757 , G06F11/1443 , G06F13/37
摘要： A processing control network (11) comprising a plurality of processing modules (13) connected to a ring network has a communication protocol. Each module has an input port (21), an output port (23) and a computer controlled switch (25) which can be operated to route communications through the module in a number of different ways. The protocol involves one module (13) seizing control of the network (11) to become a transmitter module by opening its switch (25) and transmitting information to the other modules. The other modules close their switches (25) to become receiver modules for receiving this information in succession about the network. The transmitter module transmits information from its output port (23) and subsequently receives the same information eventually at its input port (21) after passing around the network and so can perform a verification check in the transmitted information. Subsequently the transmitter module relinquishes control of the network (11) by closing its switch (25) to become a receiver module and allows the next module (13) the opportunity to become the transmitter module.
摘要翻译：包括连接到环网的多个处理模块（13）的处理控制网络（11）具有通信协议。每个模块具有输入端口（21），输出端口（23）和计算机控制开关（25），其可以被操作以以多种不同的方式路由通过模块的通信。该协议涉及一个模块（13）通过打开其交换机（25）并向其他模块发送信息来占用网络（11）的控制以变成发射机模块。其他模块将其交换机（25）关闭成为用于接收关于网络的该信息的接收机模块。发射机模块从其输出端口（23）发送信息，并且在通过网络之后最终在其输入端口（21）处接收相同的信息，因此可以对发送的信息进行验证检查。随后，发射机模块通过关闭其交换机（25）来放弃对网络（11）的控制，以成为接收机模块，并允许下一个模块（13）成为发射机模块。

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