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1. 发明申请

WO2018033694A1 A MEMORY UNIT AND METHOD OF OPERATION OF A MEMORY UNIT TO HANDLE OPERATION REQUESTS 审中-公开
标题翻译：一种存储单元和操作存储单元处理操作请求的方法
公开(公告)号：WO2018033694A1
公开(公告)日：2018-02-22
申请号：PCT/GB2017/051861
申请日：2017-06-26
申请人： ARM LIMITED
发明人： HANSSON, Andreas
IPC分类号： G06F12/0811 , G06F12/084 , G06F15/78 , G06F9/38 , G06F12/0893
摘要： A memory unit includes a data storage to store data, an operation controller to receive operation requests issued by an upstream source, a downstream capabilities storage to store an indication of operations performable by at least one downstream memory unit, and processing circuitry to perform operations on data stored in the data storage under control of the operation controller. When an operation request to perform an operation on target data is received from the upstream request source, the operation controller is arranged to determine when to control the processing circuitry to perform the operation, and when to forward the operation to a downstream memory unit in dependence on whether the target data is stored in the data storage unit and the indication of operations performable by at least one downstream memory unit. This allows for operations to be executed at a suitable location within a memory system, taking into account not only where the data resides, but also the complexity of the operation and the capabilities of the processing circuitry provided at various memory locations within the memory system.
摘要翻译：存储器单元包括用于存储数据的数据存储器，用于接收由上游源发出的操作请求的操作控制器，用于存储可由至少一个下游存储器单元执行的操作的指示的下游能力存储器以及处理电路，用于在操作控制器的控制下对存储在数据存储器中的数据执行操作。当从上游请求源接收到对目标数据执行操作的操作请求时，操作控制器布置成确定何时控制处理电路执行操作，以及何时将操作依赖地转发到下游存储器单元关于目标数据是否存储在数据存储单元中以及由至少一个下游存储器单元执行的操作的指示。这允许在存储器系统内的合适位置处执行操作，不仅考虑数据驻留的位置，而且考虑操作的复杂性以及在存储器系统内的各个存储器位置处提供的处理电路的能力。

2. 发明申请

WO2015198009A1 A DEVICE CONTROLLER AND METHOD FOR PERFORMING A PLURALITY OF WRITE TRANSACTIONS ATOMICALLY WITHIN A NONVOLATILE DATA STORAGE DEVICE 审中-公开
标题翻译：一种用于在非易失性数据存储设备中进行多重写入交易的设备控制器和方法
公开(公告)号：WO2015198009A1
公开(公告)日：2015-12-30
申请号：PCT/GB2015/051467
申请日：2015-05-19
申请人： ARM LIMITED
发明人： DE JONG, Irenéus Johannes , HANSSON, Andreas
IPC分类号： G06F12/02 , G06F3/06 , G06F13/16
CPC分类号： G06F3/061 , G06F3/06 , G06F3/0656 , G06F3/0679 , G06F9/467 , G06F12/0246 , G06F12/0253 , G06F12/0802 , G06F12/10 , G06F13/16 , G06F2212/222 , G06F2212/65 , G06F2212/7201
摘要： A device controller and method are provided for performing a plurality of write transactions atomically within a non-volatile data storage device. Each transaction specifies a logical address and the method comprises creating an address translation map for the logical addresses specified by the plurality of write transactions, by referencing an address translation record within the non-volatile data storage device to determine for each logical address a corresponding physical address within the data storage device. Further, if the corresponding physical address indicated in the address translation record already contains valid data, the logical address is remapped to a new physical address in the address translation map. However, at this point the address translation record as stored in the data storage device is not updated. Instead, the plurality of write transactions are performed using the logical address to physical address mapping in the address translation map. Then, only once the plurality of write transactions have been performed is the address translation record updated in the non- volatile data storage device in order to identify the logical address to physical address mapping in the address translation map. Since, at the time of performing the write transactions, any new data that updates data already stored in the data storage device is written into a different physical address location, and hence the previous version of the data is still stored on the data storage device, and given that the address translation record is not updated unless the plurality of write transactions are actually performed atomically, then this enables the state held on the data storage device to be rolled back to the state that existed prior to performing the plurality of write transactions, if any event prevents that plurality of write transactions being performed atomically.
摘要翻译：提供了用于在非易失性数据存储设备内原子地执行多个写入事务的设备控制器和方法。每个事务指定逻辑地址，并且该方法包括通过引用非易失性数据存储设备内的地址转换记录来为多个写入事务指定的逻辑地址创建地址转换映射，以确定每个逻辑地址相应的物理数据存储设备内的地址。此外，如果地址转换记录中指示的对应的物理地址已经包含有效数据，则将逻辑地址重新映射到地址转换映射中的新的物理地址。然而，此时存储在数据存储装置中的地址转换记录不被更新。相反，使用地址转换映射中的逻辑地址到物理地址映射来执行多个写入事务。然后，只有一次执行多次写入事务是在非易失性数据存储设备中更新的地址转换记录，以便识别地址转换映射中的物理地址映射的逻辑地址。由于在执行写入事务时，将已经存储在数据存储装置中的数据的任何新数据写入不同的物理地址位置，因此数据的先前版本仍然存储在数据存储装置上，并且假定地址转换记录不被更新，除非多个写入事务实际上是以原子方式执行的，则这使得保持在数据存储设备上的状态能够回滚到在执行多个写入事务之前存在的状态，如果任何事件阻止多个写事务以原子方式执行。

3. 发明申请

WO2018055324A1 AN APPARATUS, MEMORY CONTROLLER, MEMORY MODULE AND METHOD FOR CONTROLLING DATA TRANSFER 审中-公开
标题翻译：用于控制数据传输的设备，存储器控制器，存储器模块和方法
公开(公告)号：WO2018055324A1
公开(公告)日：2018-03-29
申请号：PCT/GB2017/052224
申请日：2017-07-31
申请人： ARM LIMITED
发明人： HANSSON, Andreas , ELSASSER, Wendy Arnott , CAMPBELL, Michael Andrew
IPC分类号： G06F13/42
CPC分类号： G06F12/0623 , G06F12/084 , G06F12/0888 , G06F13/1663 , G06F13/4234 , G06F2212/6046 , Y02D10/14 , Y02D10/151
摘要： An apparatus, memory controller, memory module and method are provided for controlling data transfer in memory. The apparatus comprises a memory controller and a plurality of memory modules. The memory controller is arranged to orchestrate direct data transfer by transmitting a first direct transfer command to a first memory module and a second direct transfer command to a second memory module. The first memory module is responsive to receipt of the first direct transfer command to directly transmit the data for receipt by the second memory module in a way that bypasses the memory controller. The second memory module is responsive to the second direct transfer command to receive the data from the first memory module directly, rather than requiring the data to have been routed via the memory controller, and then stores that data in dependence on the second direct transfer command. This provides an efficient mechanism for transferring data between multiple memory modules coupled to the same memory controller.
摘要翻译：提供了用于控制存储器中的数据传输的设备，存储器控制器，存储器模块和方法。该装置包括存储器控制器和多个存储器模块。存储器控制器被配置为通过向第一存储器模块发送第一直接转移命令并向第二存储器模块发送第二直接转移命令来编排直接数据传输。第一存储器模块响应于第一直接传输命令的接收而以绕过存储器控制器的方式直接传输供第二存储器模块接收的数据。第二存储器模块响应于第二直接传输命令而直接从第一存储器模块接收数据，而不是要求数据经由存储器控制器被路由，然后根据第二直接传输命令来存储该数据。这提供了一种有效的机制，用于在连接到同一个内存控制器的多个内存模块之间传输数据。

4. 发明申请

WO2016016605A1 A DATA PROCESSING APPARATUS, AND A METHOD OF HANDLING ADDRESS TRANSLATION WITHIN A DATA PROCESSING APPARATUS 审中-公开
标题翻译：数据处理装置，以及在数据处理装置中处理地址转换的方法
公开(公告)号：WO2016016605A1
公开(公告)日：2016-02-04
申请号：PCT/GB2015/051809
申请日：2015-06-22
申请人： ARM LIMITED
发明人： HANSSON, Andreas , SAIDI, Ali Ghassan , UDIPI, Aniruddha Nagendran , DIESTELHORST, Stephan
IPC分类号： G06F12/10
CPC分类号： G06F12/1036 , G06F12/0862 , G06F12/1009 , G06F12/1027 , G06F2212/1016 , G06F2212/651 , G06F2212/654 , G06F2212/657 , G06F2212/681 , G06F2212/684 , Y02D10/13
摘要： A data processing apparatus and method are provided for performing address translation in response to a memory access request issued by processing circuitry of the data processing apparatus and specifying a virtual address for a data item. Address translation circuitry performs an address translation process with reference to at least one descriptor provided by at least one page table, in order to produce a modified memory access request specifying a physical address for the data item. The address translation circuitry includes page table walk circuitry configured to generate at least one page table walk request in order to retrieve the at least one descriptor required for the address translation process. In addition, walk ahead circuitry is located in a path between the address translation circuitry and a memory device containing the at least one page table. The walk ahead circuitry comprises detection circuitry used to detect a memory page table walk request generated by the page table walk circuitry of the address translation circuitry for a descriptor in a page table. In addition, the walk ahead circuitry has further request generation circuitry which is used to generate a prefetch memory request in order to prefetch data from the memory device at a physical address determined with reference to the descriptor requested by the detected memory page table walk request. This prefetched data may be another descriptor required as part of the address translation process, or may be the actual data item being requested by the processing circuitry. Such an approach can significantly reduce latency associated with the address translation process.
摘要翻译：提供了一种数据处理装置和方法，用于响应由数据处理装置的处理电路发出的存储器访问请求并指定数据项的虚拟地址来执行地址转换。参考由至少一个页表提供的至少一个描述符，地址转换电路执行地址转换过程，以便产生指定数据项的物理地址的经修改的存储器访问请求。地址转换电路包括页表行走电路，其被配置为生成至少一个页表步行请求，以便检索地址转换处理所需的至少一个描述符。此外，前进电路位于地址转换电路和包含至少一个页表的存储器件之间的路径中。步行电路包括用于检测由页表中的描述符的地址转换电路的页表步行电路产生的存储器页表行走请求的检测电路。另外，步行电路具有进一步的请求生成电路，其用于生成预取存储器请求，以便以参考由检测到的存储器页表步行请求所请求的描述符确定的物理地址从存储器设备预取数据。该预取数据可以是作为地址转换处理的一部分所需的另一个描述符，或可以是由处理电路请求的实际数据项。这种方法可以显着减少与地址转换过程相关联的延迟。

5. 发明申请

WO2016166503A1 MULTIPLE HETEROGENEOUS ENERGY STORES 审中-公开
标题翻译：多个异质能源存储
公开(公告)号：WO2016166503A1
公开(公告)日：2016-10-20
申请号：PCT/GB2016/050646
申请日：2016-03-10
申请人： ARM LIMITED
发明人： HANSSON, Andreas , CRAWFORD, Ashley John , DIESTELHORST, Stephan , MYERS, James Edward
IPC分类号： G06F1/26 , G06F1/32 , H02J7/34
CPC分类号： G06F1/329 , G06F1/263 , G06F1/3228 , H02J7/345 , H02J2007/0067 , Y02D10/24
摘要： There is provided an apparatus comprising a requirement determination unit to determine an energy requirement for a system component. A status determination unit determines status information relating to a plurality of heterogeneous energy stores and actuating system control unit controls an activity of the system component in dependence on the status information relating to the plurality of heterogeneous energy stores and the energy requirement.
摘要翻译：提供了一种装置，其包括用于确定系统部件的能量需求的需求确定单元。状态确定单元确定与多个异构能量存储相关的状态信息，并且致动系统控制单元根据与多个异构能量存储和能量需求相关的状态信息来控制系统组件的活动。

6. 发明申请

WO2018100331A1 STORAGE CIRCUITRY RESPONSIVE TO A TAG-MATCHING COMMAND 审中-公开
公开(公告)号：WO2018100331A1
公开(公告)日：2018-06-07
申请号：PCT/GB2017/052732
申请日：2017-09-15
申请人： ARM LIMITED
发明人： HANSSON, Andreas , NIKOLERIS, Nikos , ELSASSER, Wendy Arnott
IPC分类号： G11C7/10 , G11C8/06 , G11C8/08 , G11C8/16 , G11C11/408 , G11C11/4093 , G11C11/4096 , G06F12/0846 , G06F12/0864 , G06F12/0895
摘要： Storage circuitry (64) comprises an array (32) of storage locations (34) arranged in rows and columns, a row buffer (36) comprising a plurality of entries (68) each to store information from a storage location at a corresponding column of an active row (46) of the array (32), and comparison circuitry (70) responsive to a tag-matching command specifying a tag value (72) to compare the tag value with information stored in each of a subset of two or more entries (68) of the row buffer (36). The comparison circuitry (70) identifies which of the subset of entries, if any, is a matching entry storing information matching the tag value. This allows memory technologies such as DRAM to be used more efficiently as a set-associative cache.

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