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1. 发明申请

WO2006051487A1 FLASH- AND ROM- MEMORY 审中-公开
标题翻译： FLASH-和ROM-存储器
公开(公告)号：WO2006051487A1
公开(公告)日：2006-05-18
申请号：PCT/IB2005/053672
申请日：2005-11-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VERHAAR, Rob , DORMANS, Guido, J., M. , STORMS, Maurits , CUPPENS, Roger , LIST, Frans, J. , BEURZE, Robert, H.
发明人： VERHAAR, Rob , DORMANS, Guido, J., M. , STORMS, Maurits , CUPPENS, Roger , LIST, Frans, J. , BEURZE, Robert, H.
IPC分类号： H01L27/112 , H01L27/115 , H01L21/8246 , H01L21/8247
CPC分类号： H01L27/1122 , H01L27/112 , H01L27/11226 , H01L27/115
摘要： Method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell in a second semiconductor device, the first and second semiconductor device each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively; the Flash memory cell being made in non-volatile memory technology and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate; the ROM memory cell being made in a baseline technology and comprising a single gate transistor, which method includes manipulating a layout of at least one baseline mask as used in the baseline technology; the manipulation including: incorporating into the layout of the at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell to a layout of one ROM memory cell by eliminating, from the at least one baseline mask, a layout for the floating transistor from the layout of the Flash memory cell and designating the layout of the access transistor of the Flash memory cell as a layout of the single gate transistor of the ROM memory cell.
摘要翻译：用于将第一半导体器件上的闪存单元转换为第二半导体器件中的ROM存储单元的方法，所述第一和第二半导体器件各自布置在半导体衬底上，并且每个包括相同的器件部分和相同的布线方案将设备部分分别连接到闪存单元和ROM存储单元; 所述闪存单元由非易失性存储器技术制成并且包括存取晶体管和浮置晶体管，所述浮动晶体管包括浮置栅极和控制栅极; 所述ROM存储器单元是在基线技术中制成并且包括单个栅极晶体管，该方法包括操作基线技术中使用的至少一个基线掩模的布局; 所述操作包括：将所述至少一个基准掩码的布局合并到所述闪存单元的布局中，以及通过从所述至少一个基线掩码中消除所述闪存单元的布局而将所述闪存单元的布局转换为一个ROM存储器单元的布局，根据闪存单元的布局布置浮动晶体管，并指定闪存单元的存取晶体管的布局作为ROM存储单元的单栅极晶体管的布局。

2. 发明申请

WO2004112047A1 NON-VOLATILE STATIC MEMORY CELL 审中-公开
标题翻译：非挥发性静态存储单元
公开(公告)号：WO2004112047A1
公开(公告)日：2004-12-23
申请号：PCT/IB2004/050882
申请日：2004-06-10
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , CUPPENS, Roger , DITEWEG, Anthonie, M., H.
发明人： CUPPENS, Roger , DITEWEG, Anthonie, M., H.
IPC分类号： G11C14/00
CPC分类号： G11C14/00
摘要： A static memory cell comprising a pair of cross-coupled inverters (10, 12) which is “shadowed” with non-volatile memory elements (14, 16) so that data written in the static memory can be stored in the non-volatile cell, but also can be recalled later. The non-volatile cells (14, 16) are programmed with opposite data to increase the robustness of the retrieval process, and they are cross-coupled to the internal nodes (A, B) of the static memory cell, one the non-volatile cells (14) having a control gate connected to B and its source to A, and the other non-volatile element (16) having a control gate connected to A and its source to B. The drain of each non-volatile element (14, 16) is connected by means of a respective pMOS transistor (18, 20) to a program supply means.
摘要翻译：一种静态存储单元，包括一对与非易失性存储元件（14,16）“遮蔽”的交叉耦合的反相器（10,12），使得写入静态存储器中的数据可以存储在非易失性单元，但也可以稍后回顾。非易失性单元（14,16）被编程为相反的数据以增加检索过程的鲁棒性，并且它们与静态存储器单元的内部节点（A，B）交叉耦合，一个非易失性单元具有与B连接的控制栅极的电池（14），其源极连接到A，而另一个非易失性元件（16）具有连接到A的控制栅极，其源极连接到B.每个非易失性元件（14）的漏极，16）通过相应的pMOS晶体管（18,20）连接到程序提供装置。

3. 发明申请

WO2003098637A1 MRAM-CELL AND ARRAY-ARCHITECTURE WITH MAXIMUM READ-OUT SIGNAL AND REDUCED ELECTROMAGNETIC INTERFERENCE 审中-公开
标题翻译：具有最大读出信号和降低电磁干扰的MRAM单元和阵列结构
公开(公告)号：WO2003098637A1
公开(公告)日：2003-11-27
申请号：PCT/IB2003/002231
申请日：2003-05-19
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DITEWIG, Anthonie, M., H. , CUPPENS, Roger
发明人： DITEWIG, Anthonie, M., H. , CUPPENS, Roger
IPC分类号： G11C11/16
CPC分类号： G11C11/16 , G11C11/15
摘要： An MRAM memory is proposed which gives a maximum read-out signal. This is advantageous for high-speed sensing of the MRAM bits. In an MRAM memory with magnetoresistive memory cells linked together to form logically organized rows and columns, It is obtained by, at least during writing, connecting write bitlines of two adjacent rows or columns with each other, so as to write inverse data values in two adjacent memory cells. In this way, a return path for the writing current is provided in a small loop, which enhances EMC behavior.
摘要翻译：提出了一种提供最大读出信号的MRAM存储器。这对于MRAM位的高速感测是有利的。在具有连接在一起形成逻辑组织的行和列的磁阻存储器单元的MRAM存储器中，至少在写入期间通过将两个相邻行或列的写位线彼此连接来获得，以便将二进制数据值写入二相邻的存储单元。以这种方式，写入电流的返回路径以小环路提供，这增强了EMC行为。

4. 发明申请

WO2003050813A3 A DEVICE AND METHOD TO READ A 2-TRANSISTOR FLASH MEMORY CELL 审中-公开
公开(公告)号：WO2003050813A3
公开(公告)日：2003-06-19
申请号：PCT/IB2002/005206
申请日：2002-12-05
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DITEWIG, Anthonie, M., H. , WIDDERSHOVEN, Franciscus, P. , CUPPENS, Roger
发明人： DITEWIG, Anthonie, M., H. , WIDDERSHOVEN, Franciscus, P. , CUPPENS, Roger
IPC分类号： G11C16/04
摘要： The present invention relates to electronic memories, more particularly to an improved method and apparatus to read the content of compact 2-transistor flash memory cells. A method of reading a 2-transistor flash memory cell 1 is provided. The memory cell 1 comprises a storage transistor 2 with a storage gate 6 and a selecting transistor 3 with a select gate 7. The method comprises leaving the storage gate 6 floating while the select gate 7 is switched from a first voltage to a second voltage, whereby the first voltage is lower than the second voltage. A device according to the present invention comprises a switching circuit for leaving the storage gate 6 floating while the select gate 7 is switched from the first voltage to the second voltage, the first voltage being lower than thesecond voltage.

5. 发明申请

WO2003050813A2 A DEVICE AND METHOD TO READ A 2-TRANSISTOR FLASH MEMORY CELL 审中-公开
标题翻译：一种读取2-晶体管闪存单元的装置和方法
公开(公告)号：WO2003050813A2
公开(公告)日：2003-06-19
申请号：PCT/IB2002/005206
申请日：2002-12-05
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DITEWIG, Anthonie, M., H. , WIDDERSHOVEN, Franciscus, P. , CUPPENS, Roger
发明人： DITEWIG, Anthonie, M., H. , WIDDERSHOVEN, Franciscus, P. , CUPPENS, Roger
IPC分类号： G11C
CPC分类号： G11C16/26
摘要： The present invention relates to electronic memories, more particularly to an improved method and apparatus to read the content of compact 2-transistor flash memory cells. A method of reading a 2-transistor flash memory cell 1 is provided. The memory cell 1 comprises a storage transistor 2 with a storage gate 6 and a selecting transistor 3 with a select gate 7. The method comprises leaving the storage gate 6 floating while the select gate 7 is switched from a first voltage to a second voltage, whereby the first voltage is lower than the second voltage. A device according to the present invention comprises a switching circuit for leaving the storage gate 6 floating while the select gate 7 is switched from the first voltage to the second voltage, the first voltage being lower than thesecond voltage.
摘要翻译：本发明涉及电子存储器，尤其涉及读取紧凑型双晶体管闪存单元的内容的改进方法和装置。提供读取双晶体管快闪存储单元1的方法。存储单元1包括具有存储栅极6的存储晶体管2和具有选择栅极7的选择晶体管3.该方法包括在选择栅极7从第一电压切换到第二电压时使存储栅极6浮置，由此第一电压低于第二电压。根据本发明的器件包括开关电路，用于在选择栅极7从第一电压切换到第二电压时使存储栅极6浮置，第一电压低于第二电压。

6. 发明申请

WO2003001529A2 METHOD AND CIRCUIT ARRANGEMENT FOR MEMORY ERROR RECOVERY 审中-公开
标题翻译：用于存储器错误恢复的方法和电路布置
公开(公告)号：WO2003001529A2
公开(公告)日：2003-01-03
申请号：PCT/IB2002/002334
申请日：2002-06-18
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SALTERS, Roelof, H., W. , CUPPENS, Roger , DITEWEG, Anthonie, M., H.
发明人： SALTERS, Roelof, H., W. , CUPPENS, Roger , DITEWEG, Anthonie, M., H.
IPC分类号： G11C
CPC分类号： G11C29/802 , G11C29/812
摘要： The present invention relates to a method and circuit arrangement for performing an error recovery in a memory arrangement comprising at least two separate memories. The memory arrangement comprises a central storage for storing a faulty-address information of the at least two separate memories. Each memory has its own local address comparison unit and local volatile memory for addresses. The faulty-address information is transported from the central storage to the local volatile memories for address comparison of a redundancy system. Thereby, overhead and complexity can be reduced and flexibility of the architecture enhanced.
摘要翻译：本发明涉及一种用于在包括至少两个分开的存储器的存储器装置中执行错误恢复的方法和电路装置。存储器装置包括用于存储至少两个单独存储器的故障地址信息的中央存储器。每个存储器都有自己的本地地址比较单元和用于地址的本地易失性存储器。故障地址信息从中央存储器传送到本地易失性存储器，用于冗余系统的地址比较。因此，可以降低开销和复杂性并增强架构的灵活性。

7. 发明申请

WO2003001381A1 METHOD AND CIRCUIT ARRANGEMENT FOR MEMORY ERROR PROCESSING 审中-公开
标题翻译：用于存储器错误处理的方法和电路布置
公开(公告)号：WO2003001381A1
公开(公告)日：2003-01-03
申请号：PCT/IB2002/002333
申请日：2002-06-18
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DITEWIG, Anthonie, M., H. , CUPPENS, Roger , SALTERS, Roelof, H., W.
发明人： DITEWIG, Anthonie, M., H. , CUPPENS, Roger , SALTERS, Roelof, H., W.
IPC分类号： G06F11/10
CPC分类号： G11C29/785 , G06F11/1016
摘要： The present invention relates to a method and circuit arrangement for performing an error correction in a memory arrangement in which a redundancy system is used. The addresses of faulty cells are recorded redundantly by applying a corresponding coding. Then, an error correction is applied to the faulty-address information before it is compared to an externally applied address. Thereby, errors due to faulty redundancy addresses can be prevented.
摘要翻译：本发明涉及一种用于在其中使用冗余系统的存储装置中执行纠错的方法和电路装置。通过应用相应的编码来冗余地记录故障单元的地址。然后，在将故障地址信息与外部施加的地址进行比较之前，将错误校正应用于故障地址信息。因此，可以防止由于冗余地址故障引起的错误。

8. 发明申请

WO2005117022A1 REVERSED MAGNETIC TUNNELING JUNCTION FOR POWER EFFICIENT BYTE WRITING OF MRAM 审中-公开
标题翻译： MRAM功率有效字节写入的反向磁连接
公开(公告)号：WO2005117022A1
公开(公告)日：2005-12-08
申请号：PCT/IB2005/051618
申请日：2005-05-18
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DITEWEG, Anthonie, M., H. , CUPPENS, Roger
发明人： DITEWEG, Anthonie, M., H. , CUPPENS, Roger
IPC分类号： G11C11/16
CPC分类号： H01L27/228 , G11C11/16 , H01L27/222
摘要： A magnetoresistive memory device comprises magnetoresistive cells, each cell comprising a free magnetic layer and a fixed magnetic layer. The device furthermore comprises a bit line for each magnetoresistive cell and digit lines. Each digit line is common to a number of magnetoresistive cells and is positioned in a direction perpendicular to the bitlines. The magnetic layers are positioned in between the bitlines and the digit lines, but in a reversal of the usual layout according to the prior art, i.e. the digit line is positioned closer to the fixed magnetic layer than to the free magnetic layer. This enables a reduction in total write current where the write current in the line nearer the magnetic layer can be less than the current in a line spaced further away. Since there are more bit lines than digit lines activated, the total of the bit currents and the digit current can be reduced. Reduced total write current is useful in mobile battery powered applications to maximize battery life.
摘要翻译：磁阻存储器件包括磁阻单元，每个单元包括自由磁性层和固定磁性层。该装置还包括用于每个磁阻单元和位线的位线。每个数字线对多个磁阻单元是共同的，并且位于垂直于位线的方向上。磁层位于位线和数字线之间，但是根据现有技术的通常布局的反转，即数字线定位成比固定磁性层更靠近自由磁性层。这使得能够减少总写入电流，其中更接近磁性层的线中的写入电流可以小于在更远的距离上的线中的电流。由于比数字线更多的位线被激活，所以可以减少位电流和数字电流的总和。总写入电流的降低在移动电池供电的应用中是有用的，以最大限度地延长电池寿命。

9. 发明申请

WO2004049342A2 CURRENT RE-ROUTING SCHEME FOR SERIAL-PROGRAMMED MRAM 审中-公开
标题翻译：串行编程MRAM的当前重新布线方案
公开(公告)号：WO2004049342A2
公开(公告)日：2004-06-10
申请号：PCT/IB2003/004868
申请日：2003-10-29
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DITEWIG, Anthonie, M., H. , CUPPENS, Roger
发明人： DITEWIG, Anthonie, M., H. , CUPPENS, Roger
IPC分类号： G11C11/16
CPC分类号： G11C11/16
摘要： The present invention provides a method and device for programming a magnetic random access memory element with reduced current consumption, by re-routing digitline current through a selected bitline in a selected direction.
摘要翻译：本发明提供一种用于通过在所选方向上重新路由选定位线的数字线电流来编程具有降低的电流消耗的磁随机存取存储器元件的方法和装置。

10. 发明申请

WO2003098634A3 MAGNETORESISTIVE MEMORY CELL ARRAY AND MRAM MEMORY COMPRISING SUCH ARRAY 审中-公开
公开(公告)号：WO2003098634A3
公开(公告)日：2003-11-27
申请号：PCT/IB2003/002019
申请日：2003-05-16
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DITEWIG, Anthonie, M., H. , CUPPENS, Roger
发明人： DITEWIG, Anthonie, M., H. , CUPPENS, Roger
IPC分类号： G11C8/16
摘要： The present invention describes a matrix with magnetoresistive memory cells arranged in logically organized rows and columns, Each memory cell includes a magnetoresistive element. The matrix comprises means for simultaneously reading from one cell in a column and writing to another cell in a column, or means for simultaneous reading from one cell in a row and writing to another cell in the same row.Such matrix can be used in a read-while-write MRAM memory.

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