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1. 发明申请

WO2006051090A1 METHOD OF MAKING FULLY SILICIDED GATE ELECTRODE 审中-公开
标题翻译：制备完全硅化物电极的方法
公开(公告)号：WO2006051090A1
公开(公告)日：2006-05-18
申请号：PCT/EP2005/055873
申请日：2005-11-10
申请人： INFINEON TECHNOLOGIES AG , KIM, SunOo , KLEE, Veit
发明人： KIM, SunOo , KLEE, Veit
IPC分类号： H01L21/336 , H01L21/28 , H01L29/78
CPC分类号： H01L29/6653 , H01L21/28097 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： A method of making a semiconductor device for an integrated circuit chip. An interim gate electrode stack formed includes a top silicon portion patterned from a second silicon layer, a sandwiched oxide portion patterned from an etch stop oxide layer, and a bottom silicon portion patterned from a first silicon layer formed on a gate dielectric layer over a substrate. Etching the second silicon layer is stopped at the etch stop oxide layer. A spacer structure is formed about the interim gate electrode stack, and then the top silicon portion and the sandwiched oxide portion are removed. The spacer structure height may be reduced. A metal layer is formed over the bottom silicon portion of the interim gate electrode stack and over source and drain regions of the substrate, all of which are suicided at the same time to form a folly suicided (FUSI) gate electrode and suicided source and drain regions.
摘要翻译：制造用于集成电路芯片的半导体器件的方法。形成的中间栅极电极堆叠包括从第二硅层图案化的顶部硅部分，从蚀刻停止氧化物层图案化的夹层氧化物部分和从在衬底上形成的栅极电介质层上形成的第一硅层图案化的底部硅部分。蚀刻第二硅层在蚀刻停止氧化物层处停止。围绕临时栅电极堆叠形成间隔结构，然后去除顶部硅部分和夹层氧化物部分。可以减小间隔件结构的高度。在中间栅极电极堆叠的底部硅部分上方形成金属层，并在衬底的源极和漏极区域上形成一个金属层，所有这些都同时被硅化，以形成愚蠢的（FUSI）栅电极和自制的源极和漏极区域。

2. 发明申请

WO2003017356A2 IMPROVED STRAP RESISTANCE USING SELECTIVE OXIDATION TO CAP DT POLY BEFORE STI ETCH 审中-公开
标题翻译：使用选择性氧化改善纹理电阻，以便在涂层之前进行CAP DT聚合
公开(公告)号：WO2003017356A2
公开(公告)日：2003-02-27
申请号：PCT/EP2002/009009
申请日：2002-08-12
申请人： INFINEON TECHNOLOGIES AG
发明人： WENSLEY, Paul , COMMONS, Martin , MONO, Tobias , KLEE, Veit
IPC分类号： H01L21/762
CPC分类号： H01L27/10864 , H01L21/76224 , H01L21/763 , H01L27/10861
摘要： A method of providing shallow trench (143) isolation for a semiconductor wafer (100). Trenches (113) are formed within a first semiconductor material (112) and a pad nitride (114), leaving a portion of first semiconductor material (112) and pad nitride (114) in a region between the trenches (113). A second semiconductor material (116) is deposited over the trenches (113) to fill the trenches (113) to a height below the first semiconductor material (112) top surface. A first insulator (130) is selectively formed over the second semiconductor material (116). The pad nitride (114) and a portion of the first semiconductor material (112) between the trenches (113) are removed to isolate element regions of the wafer (100) and form straps (142) having a low resistance.
摘要翻译：一种为半导体晶片（100）提供浅沟槽（143）隔离的方法。沟槽（113）形成在第一半导体材料（112）和衬垫氮化物（114）内，在沟槽（113）之间的区域中留下第一半导体材料（112）的一部分和衬垫氮化物（114）。第二半导体材料（116）沉积在沟槽（113）上以将沟槽（113）填充到第一半导体材料（112）顶表面下方的高度。在第二半导体材料（116）上有选择地形成第一绝缘体（130）。去除衬垫氮化物（114）和沟槽（113）之间的第一半导体材料（112）的一部分以隔离晶片（100）的元件区域并形成具有低电阻的带（142）。

3. 发明申请

WO2003003122A3 METHOD OF MEASURING CRITICAL DIMENSION AND OVERLAY IN SINGLE STEP 审中-公开
公开(公告)号：WO2003003122A3
公开(公告)日：2003-01-09
申请号：PCT/US2002/019091
申请日：2002-06-17
申请人： INFINEON TECHNOLOGIES AG
发明人： COMMONS, Martin , MONO, Tobias , KLEE, Veit , POHL, John , WENSLEY, Paul
IPC分类号： G03F7/20
摘要： A semiconductor wafer structure in a overlay pattern that permits determination of overlay and critical dimension features by CD SEM in a single pass along a given axis, comprising:a) a center feature (13) that provides a critical dimension point along a given axis;b) plurality of smaller sections (14, 14A) positioned adjacent to the center feature section along the given axis that include a plurality of spaces between each of the plurality of smaller sections; and c) a plurality of displacement lines adjacent to the plurality of the smaller sections to displace a plurality of spaces.

4. 发明申请

WO2003014828A1 RESOLUTION ENHANCEMENT FOR ALTERNATING PHASE SHIFT MASKS 审中-公开
标题翻译：解决方案用于替换相移屏蔽
公开(公告)号：WO2003014828A1
公开(公告)日：2003-02-20
申请号：PCT/EP2002/008783
申请日：2002-08-06
申请人： INFINEON TECHNOLOGIES AG
发明人： KLEE, Veit , MONO, Tobias , SCHRÖDER, Uwe, Paul
IPC分类号： G03F1/00
CPC分类号： G03F1/34 , G03F1/32
摘要： An alternating phase shift mask (400) and method of manufacturing thereof including assist edges (450) and (452) surrounding a main phase edge (420). Assist edges (450) and (452) improve the resolution of the alternating phase shift mask (400), thus enabling the patterning of smaller size features on a semiconductor wafer.
摘要翻译：一种交替相移掩模（400）及其制造方法，包括围绕主相边缘（420）的辅助边缘（450）和（452）。辅助边缘（450）和（452）提高交替相移掩模（400）的分辨率，因此能够对半导体晶片上的较小尺寸特征图案化。

5. 发明申请

WO2007068714A3 METHOD OF MAKING A CONTACT IN A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：WO2007068714A3
公开(公告)日：2007-06-21
申请号：PCT/EP2006/069648
申请日：2006-12-13
申请人： INFINEON TECHNOLOGIES AG , KLEE, Veit , KNOEFLER, Roman , SCHROEDER, Paul Uwe
发明人： KLEE, Veit , KNOEFLER, Roman , SCHROEDER, Paul Uwe
IPC分类号： H01L21/311 , H01L21/308 , H01L21/60 , H01L21/768 , H01L21/027
摘要： To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed. A mask material is formed over the insulating layer and is aligned with the pattern transfer layer. Remaining portions of the pattern transfer layer are removed and recesses are etched in the insulating layer using the mask material as a mask.

6. 发明申请

WO2004027519A2 DUMMY PATTERNS FOR REDUCING PROXIMITY EFFECTS AND METHOD OF USING SAME 审中-公开
标题翻译：用于减少临近效应的DUMMY模式及其使用方法
公开(公告)号：WO2004027519A2
公开(公告)日：2004-04-01
申请号：PCT/EP2003/009879
申请日：2003-09-05
申请人： INFINEON TECHNOLOGIES AG
发明人： COMMONS, Martin , KLEE, Veit , MONO, Tobias , WENSLEY, Paul
IPC分类号： G03F7/20
CPC分类号： G03F1/36
摘要： Disclosed is an optical lithographic mask having one or more dummy patterns, each said dummy pattern having a masked area of said optical lithographic mask seperated from one or more feature masked areas on said optical lithographic mask by an unmasked region of width d, wherein said width d is selected to substantially minimize an average deviation between the dimensions of said feature masked areas and corresponding features etched out upon a semiconductor surface utilizing said optical lithographic mask.
摘要翻译：公开了一种具有一个或多个虚拟图案的光学光学掩模，每个所述虚拟图案具有通过宽度为d的未掩蔽区域在所述光学光刻掩模上的一个或多个特征掩蔽区域分离的所述光学平版印刷掩模区域，其中所述宽度 d被选择为基本上最小化利用所述光学平版印刷掩模在所述特征掩蔽区域的尺寸和在半导体表面上蚀刻出的对应特征之间的平均偏差。

7. 发明申请

WO2003001593A3 STI PROCESS FOR DRAM 审中-公开
公开(公告)号：WO2003001593A3
公开(公告)日：2003-01-03
申请号：PCT/US2002/019892
申请日：2002-06-21
申请人： INFINEON TECHNOLOGIES AG
发明人： POHL, John , CHAUDHARY, Nirmal , KLEE, Veit , MONO, Tobias , SCHROEDER, Paul
IPC分类号： H01L21/8242
摘要： A nitride hard mask (230) is used to isolate active areas of a DRAM cell. The shallow trench isolation (STI) method includes forming memory cells comprising deep trenches (216) on a semiconductor wafer (200). The memory cell deep trenches (216) are separated from active areas (212) by a region of substrate (212). A nitride hard mask (230) is formed over the semiconductor wafer (200). The wafer (200) is patterned with the nitride hard mask (230), and the wafer (200) is etched to remove the region of substrate (212) between the deep trenches and active areas to provide shallow trench isolation. An etch chemistry selective to the nitride hard mask (230) is used.

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