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1. 发明申请

WO03005447A8 STRUCTURE AND METHOD OF FABRICATING EMBEDDED VERTICAL DRAM ARRAYS WITH SILICIDED BITLINE AND POLYSILICON INTERCONNECT 审中-公开
标题翻译：嵌入式BITLINE和POLYSILICON INTERCONNECT嵌入垂直DRAM阵列的结构与方法
公开(公告)号：WO03005447A8
公开(公告)日：2004-02-19
申请号：PCT/GB0202961
申请日：2002-06-27
申请人： IBM , IBM UK , INFINEON TECHNOLOGIES AG
发明人： DIVAKARUNI RAMACHANDRA , GRUENING ULRIKE , MANDELMAN JACK , NESBIT LARRY , RADENS CARL
IPC分类号： H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108
CPC分类号： H01L27/10891 , H01L27/10864 , H01L27/10876 , H01L27/10894
摘要： A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.
摘要翻译：用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域中制造具有硅化多晶硅层的垂直MOSFET DRAM单元，着陆焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠。该工艺消除了对M0金属化层的需要。

2. 发明申请

WO03005447A2 STRUCTURE AND METHOD OF FABRICATING EMBEDDED VERTICAL DRAM ARRAYS WITH SILICIDED BITLINE AND POLYSILICON INTERCONNECT 审中-公开
标题翻译：硅化双线和多晶硅互连嵌入式垂直DRAM阵列的结构和制作方法
公开(公告)号：WO03005447A2
公开(公告)日：2003-01-16
申请号：PCT/GB0202961
申请日：2002-06-27
申请人： IBM , IBM UK , INFINEON TECHNOLOGIES AG
发明人： DIVAKARUNI RAMACHANDRA , GRUENING ULRIKE , MANDELMAN JACK , NESBIT LARRY , RADENS CARL
IPC分类号： H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108
CPC分类号： H01L27/10891 , H01L27/10864 , H01L27/10876 , H01L27/10894
摘要： A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The process eliminates the need for a M0 metallization layer.
摘要翻译：用于制造嵌入式垂直DRAM单元的结构和工艺包括在阵列区域，连接焊盘和/或互连结构，支撑源极和漏极区域和/或栅极堆叠中制造具有硅化多晶硅层的垂直MOSFET DRAM单元。该工艺消除了对M0金属化层的需求。

3. 发明申请

WO2007023011A2 DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 审中-公开
标题翻译：双端口增益电池与侧面和顶部门控读取晶体管
公开(公告)号：WO2007023011A2
公开(公告)日：2007-03-01
申请号：PCT/EP2006063581
申请日：2006-06-27
申请人： IBM , IBM UK , MANDELMAN JACK , CHENG KANGGUO , DIVAKARUNI RAMACHANDRA , RADENS CARL , WANG GENG
发明人： MANDELMAN JACK , CHENG KANGGUO , DIVAKARUNI RAMACHANDRA , RADENS CARL , WANG GENG
IPC分类号： H01L27/108 , H01L21/8242 , H01L27/12
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储器单元和工艺序列。具体而言，本发明提供了与现有SOI CMOS技术兼容的密集，高性能SRAM单元替换。本领域已知各种增益单元布局。本发明通过提供用SOI CMOS制造的密集布局来改进现有技术。一般而言，存储器单元包括分别设置有栅极，源极和漏极的第一晶体管; 第二晶体管，分别具有第一栅极，第二栅极，源极和漏极; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

4. 发明申请

WO2007023011B1 DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 审中-公开
标题翻译：双端口增益单元与侧面和顶部读取晶体管
公开(公告)号：WO2007023011B1
公开(公告)日：2007-07-12
申请号：PCT/EP2006063581
申请日：2006-06-27
申请人： IBM , IBM UK , MANDELMAN JACK , CHENG KANGGUO , DIVAKARUNI RAMACHANDRA , RADENS CARL , WANG GENG
发明人： MANDELMAN JACK , CHENG KANGGUO , DIVAKARUNI RAMACHANDRA , RADENS CARL , WANG GENG
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

5. 发明申请

WO2009120612A2 SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRAIN AND METHODS OF MANUFACTURING AND DESIGN STRUCTURE 审中-公开
标题翻译：具有拉伸和/或压缩应变的半导体器件以及制造和设计结构的方法
公开(公告)号：WO2009120612A2
公开(公告)日：2009-10-01
申请号：PCT/US2009037910
申请日：2009-03-23
申请人： IBM , CHENG KANGGUO , RADENS CARL
发明人： CHENG KANGGUO , RADENS CARL
IPC分类号： H01L21/8238 , G06F9/45 , G06F17/50 , H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device having a tensile and/or compressive strain applied thereto and methods of manufacturing the semiconductor devices and design structure to enhance channel strain. The method includes forming a gate structure for an NFET and a PFET and forming sidewalls on the gate structure for the NFET and the PFET using a same deposition and etching process. The method also includes providing stress materials in the source and drain regions of the NFET and the PFET.
摘要翻译：施加有拉伸和/或压缩应变的半导体器件以及制造半导体器件和设计结构以增强沟道应变的方法。该方法包括形成用于NFET和PFET的栅极结构，并且使用相同的沉积和蚀刻工艺在用于NFET和PFET的栅极结构上形成侧壁。该方法还包括在NFET和PFET的源极和漏极区中提供应力材料。

6. 发明申请

WO0195391A8 SELF-LIMITING POLYSILICON BUFFERED LOCOS FOR DRAM TRENCH CAPACITOR COLLAR 审中-公开
标题翻译：用于DRAM TRENCH电容器COLLAR的自限制多晶硅缓冲电路
公开(公告)号：WO0195391A8
公开(公告)日：2002-03-28
申请号：PCT/US0117927
申请日：2001-06-01
申请人： INFINEON TECHNOLOGIES CORP , IBM
发明人： NESBIT LARRY , MCSTAY IRENE LENNOX , RADENS CARL , TEWS HELMUT HORST , DIVAKARUNI RAMA , MANDELMAN JACK
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861 , H01L27/10867
摘要： A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner (81) is deposited on the silicon trench walls. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer (79). A layer of amorphous silicon (83) is then deposited over the nitride liner. A silicon nitride layer is deposited on the oxidized surface of the amorphous silicon. A resist (83) is formed in the lower portion of the trench, and the exposed silicon nitride layer on top of the amorphous silicon is removed, leaving the upper portion of the amorphous silicon layer exposed. The upper portion of the layer of amorphous silicon is then oxidized so as to form a relatively thin, uniform collar (89) along the entire circumference of the trench. The nitride liner underlying the amorphous silicon layer enhances the thickness uniformity of the amorphous silicon layer and thereby the uniformity of the resulting oxide collar. The nitride liner also acts to limit lateral oxidation of the silicon trench walls during oxidation of the amorphous silicon layer. The nitride liner underlying the collar is also effective in cell operation to control the cell charge at the collar-substrate interface.
摘要翻译：一种在存储沟槽DRAM单元的存储沟槽中形成相对薄的均匀绝缘环的方法。首先在硅衬底中形成DRAM沟槽。然后，氮化物衬垫（81）沉积在硅沟槽壁上。氮化物衬垫可以直接沉积在硅壁上或下面的氧化物层（79）上。然后在氮化物衬垫上沉积一层非晶硅（83）。在非晶硅的氧化表面上沉积氮化硅层。在沟槽的下部形成抗蚀剂（83），去除非晶硅顶部的露出的氮化硅层，使非晶硅层的上部露出。然后，非晶硅层的上部被氧化，以便沿沟槽的整个圆周形成相对较薄的均匀的环（89）。非晶硅层下面的氮化物衬垫增强了非晶硅层的厚度均匀性，从而提高了所得氧化物环的均匀性。氮化物衬垫还用于在非晶硅层的氧化期间限制硅沟槽壁的横向氧化。在套环下面的氮化物衬垫在电池操作中也有效地控制在衬套 - 衬底界面处的电池电荷。

7. 发明申请

WO2009100053A2 PATTERN FORMATION EMPLOYING SELF-ASSEMBLED MATERIAL 审中-公开
标题翻译：使用自组装材料的图案形成
公开(公告)号：WO2009100053A2
公开(公告)日：2009-08-13
申请号：PCT/US2009032936
申请日：2009-02-03
申请人： IBM , BLACK CHARLES T , DALTON TIMOTHY J , DORIS BRUCE B , RADENS CARL
发明人： BLACK CHARLES T , DALTON TIMOTHY J , DORIS BRUCE B , RADENS CARL
IPC分类号： H01L21/20
CPC分类号： H01L21/0338 , B81B2203/0369 , B81C1/00031 , B81C2201/0149 , B81C2201/0198 , B82Y30/00 , H01L21/0337 , H01L51/0017 , Y10S977/882 , Y10S977/887 , Y10S977/888 , Y10T428/24479 , Y10T428/2457 , Y10T428/24612 , Y10T428/24736 , Y10T428/24802
摘要： In one embodiment, hexagonal tiles encompassing a large are divided into three groups, each containing one-third of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group (01, 02, 03) are formed in a template layer (2OA, 2OB, 20C), and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self- aligned line and space structures (4OA, 5OA; 4OB, 5OB; 4OC, 50C) are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.
摘要翻译：在一个实施例中，包括大的六边形瓦片被分成三组，每组包含彼此分离的所有六边形瓦片的三分之一。每个组（01,02,03）中的六边形瓦片的开口形成在模板层（20A，20B，20C）中，并且在每个开口内施加和组合一组自组装嵌段共聚物。该过程重复三次以包含所有三组，导致在大面积上延伸的自对准图案。在另一个实施例中，大面积被分成两个不重叠和互补组的矩形瓦片。每个矩形区域的宽度小于自组装嵌段共聚物的顺序范围。在每组中以顺序的方式形成自组装自对准线和空间结构（40A，50A; 40B，50B; 40C，50C），使得线和空间图形形成在延伸超过订购。

8. 发明申请

WO2007016047A3 METHOD AND STRUCTURE FOR FORMING SLOT VIA BITLINE FOR MRAM DEVICES 审中-公开
标题翻译：用于通过MRAM器件的位线形成槽的方法和结构
公开(公告)号：WO2007016047A3
公开(公告)日：2008-01-03
申请号：PCT/US2006028718
申请日：2006-07-24
申请人： IBM , GAIDIS MICHAEL C , RADENS CARL , CLEVENGER LAWRENCE A , DALTON TIMOTHY J , HSU LOUIS L C , WONG KEITH KWONG HON , YANG CHIH-CHAO
发明人： GAIDIS MICHAEL C , RADENS CARL , CLEVENGER LAWRENCE A , DALTON TIMOTHY J , HSU LOUIS L C , WONG KEITH KWONG HON , YANG CHIH-CHAO
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： B82Y10/00 , H01L27/222 , H01L43/12
摘要： A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.
摘要翻译：磁性随机存取存储器（MRAM）器件包括形成在下布线层上的磁隧道结（MTJ）堆叠，形成在MTJ堆叠上的硬掩模和形成在硬掩模上的上布线层。上布线层包括经由位于其中的位线的槽，槽经由与硬掩模接触的位线并与部分地围绕硬掩模的侧壁的蚀刻停止层接触。

9. 发明申请

WO2011032741A3 METHOD FOR MANUFACTURING A THIN-FILM PHOTOVOLTAIC CELL MODULE ENCOMPASSING AN ARRAY OF CELLS AND PHOTOVOLTAIC CELL MODULE 审中-公开
标题翻译：制造薄膜光伏电池模块的方法，包括电池阵列和光电池模块
公开(公告)号：WO2011032741A3
公开(公告)日：2012-04-05
申请号：PCT/EP2010059849
申请日：2010-07-09
申请人： IBM , KRAUSE RAINER KLAUS , LI ZHENGWEN O , QUON ROGER A , CLEVENGER LAWRENCE A , PETRARCA KEVIN S , RADENS CARL , SAPP BRIAN C
发明人： KRAUSE RAINER KLAUS , LI ZHENGWEN O , QUON ROGER A , CLEVENGER LAWRENCE A , PETRARCA KEVIN S , RADENS CARL , SAPP BRIAN C
IPC分类号： H01L31/05 , H05K1/02 , H05K3/22
CPC分类号： H01L31/042 , H01L31/0465 , H01L31/0504 , H02S50/10 , Y02E10/50
摘要： The invention relates to a method for manufacturing a thin-film photovoltaic cell module (10) encompassing an array of cells (100), comprising the steps of (i) providing the array of cells (100); (ii) determining, per cell (100), an electrical performance for one or more cells (100) of the array; (iii) identifying each cell (100) by its position in the array; (iv) determining one or more electrical paths (50, 52, 54) encompassing one or more of the cells (100) according to at least one optimization criterion; and (v) combining two or more cells (100) for realizing one or more electrical paths (50, 52, 54) by maintaining or establishing electrical connections (30) between individual cells (100) of the array according to the at least one optimization criterion.
摘要翻译：本发明涉及一种用于制造包围电池阵列（100）的薄膜光伏电池模块（10）的方法，包括以下步骤：（i）提供电池阵列（100）; （ii）每个单元（100）确定阵列的一个或多个单元（100）的电性能; （iii）通过其在阵列中的位置来识别每个单元（100）; （iv）根据至少一个优化标准确定包含一个或多个所述单元（100）的一个或多个电路径（50,52,54）; 以及（v）通过根据所述至少一个维持或建立阵列的各个单元（100）之间的电连接（30），组合用于实现一个或多个电路径（50,52,54）的两个或更多个单元（100）优化标准。

10. 发明申请

WO0227784A3 MAKING OF FUSES AND ANTIFUSES WITH A VERTICAL DRAM PROCESS 审中-公开
标题翻译：用垂直DRAM工艺制造熔体和抗菌剂
公开(公告)号：WO0227784A3
公开(公告)日：2003-04-10
申请号：PCT/US0142293
申请日：2001-09-25
申请人： INFINEON TECHNOLOGIES CORP , IBM
发明人： DIVAKARUNI RAMA , RADENS CARL , NESBIT LARRY , BERGNER WOLFGANG
IPC分类号： H01L21/8242 , H01L23/525
CPC分类号： H01L27/10861 , H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A structure and process for semiconductor fuses and antifuses in vertical DRAMS provides fuses and antifuses in trench openings formed within a semiconductor substrate. Vertical transistors may be formed in other of the trench openings formed within the semiconductor substrate. The fuse is formed including a semiconductor plug (108) formed within an upper portion of the trench opening (110) and includes conductive leads (252, 254) contacting the semiconductor plug. The antifuse is formed including a semiconductor plug formed within an upper portion of the trench opening and includes conductive leads formed over the semiconductor plug, at least one conductive lead isolated from the semiconductor plug by an antifuse dielectric. Each of the fuse and antifuse are fabricated using a sequence of process operations also used to simultaneously fabricate vertical transistors according to vertical DRAM technology, the plug forming the gate of the vertical transistor.
摘要翻译：垂直DRAMS中的半导体熔丝和反熔丝的结构和工艺在半导体衬底内形成的沟槽开口中提供熔丝和反熔丝。垂直晶体管可以形成在形成在半导体衬底内的其它沟槽开口中。熔丝形成包括形成在沟槽开口（110）的上部内的半导体插塞（108），并且包括接触半导体插头的导电引线（252,254）。反熔丝形成包括形成在沟槽开口的上部内的半导体插塞，并且包括形成在半导体插头上的导电引线，至少一个导电引线，其通过反熔丝绝缘体与半导体插塞隔离。熔丝和反熔丝中的每一个都使用一系列工艺操作来制造，这些工艺操作也用于根据垂直DRAM技术同时制造垂直晶体管，该插头形成垂直晶体管的栅极。

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