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1. 发明申请

WO2010110938A2 PULSE CONTROL FOR NONVOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的脉冲控制
公开(公告)号：WO2010110938A2
公开(公告)日：2010-09-30
申请号：PCT/US2010/022605
申请日：2010-01-29
申请人： RAMBUS INC. , KELLAM, Mark, D. , HAUKNESS, Brent, Steven , BRONNER, Gary, B. , DONNELLY, Kevin
发明人： KELLAM, Mark, D. , HAUKNESS, Brent, Steven , BRONNER, Gary, B. , DONNELLY, Kevin
IPC分类号： G11C16/32 , G11C16/30 , G11C16/08
CPC分类号： G11C16/10 , G11C16/0408 , G11C16/12 , G11C16/26 , G11C16/3459
摘要： This disclosure provides a nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage (selected in response to the bitline) is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about (20) nanoseconds, while a "rest period" between pulses typically is chosen to be on the order of about a hundred nanoseconds or greater (e.g., one microsecond). Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of (50) nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); if desired, segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.
摘要翻译：本公开提供了一种非易失性存储器件，其使用脉冲控制和休止时间来减轻缺陷前兆的形成。第一实施例使用脉冲位线控制，其中当期望改变相关联的存储器单元中的状态时，存储器单元沟道与参考电压（响应于位线而选择）之间的耦合被脉冲化。每个脉冲可以被选择为小于大约（20）纳秒，而“休息时段” 通常选择脉冲之间的时间约为几百纳秒或更大（例如，一微秒）。由于使用了位线控制，因此可以启用非常短的上升时间，从而可以生成（50）纳秒或更短的脉冲持续时间。在其他实施例中，这些方法也可以更一般地应用于其他导体（例如，用于编程或擦除操作的字线或衬底）; 如果需要的话，也可以使用分段的字线或位线，以最小化RC负载并使足够短的上升时间使脉冲稳健。

2. 发明申请

WO2013028377A1 SYSTEM AND METHOD FOR PERFORMING MEMORY OPERATIONS ON RRAM CELLS 审中-公开
标题翻译：在RRAM电池上执行存储器操作的系统和方法
公开(公告)号：WO2013028377A1
公开(公告)日：2013-02-28
申请号：PCT/US2012/050368
申请日：2012-08-10
申请人： RAMBUS INC. , HAUKNESS, Brent, Steven
发明人： HAUKNESS, Brent, Steven
IPC分类号： G11C13/00 , G11C16/06
CPC分类号： G11C13/0026 , G11C13/0002 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0088 , G11C2213/79
摘要： A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an RRAM cell, and a bit line control coupled to the bit line circuit. The RRAM cell includes a gate node coupled to the word line, a bias node coupled to the source line, and a bit line node coupled to the bit line. The bit line control circuit is configured to generate non-negative command voltages to perform respective memory operations on the RRAM cell.
摘要翻译：电阻RAM（RRAM）器件具有位线，字线，承载基本静态和非负电压的偏置电压的源极线，RRAM单元和耦合到位线电路的位线控制。 RRAM单元包括耦合到字线的栅极节点，耦合到源极线的偏置节点和耦合到位线的位线节点。位线控制电路被配置为产生非负指令电压，以对RRAM单元执行相应的存储器操作。

3. 发明申请

WO2010090691A2 MULTIPLE PLANE, NON-VOLATILE MEMORY WITH SYNCHRONIZED CONTROL 审中-公开
标题翻译：多平面，具有同步控制的非易失性存储器
公开(公告)号：WO2010090691A2
公开(公告)日：2010-08-12
申请号：PCT/US2009/069504
申请日：2009-12-23
申请人： RAMBUS INC. , HAUKNESS, Brent, Steven
发明人： HAUKNESS, Brent, Steven
IPC分类号： G06F12/02 , G06F12/08 , G06F9/06 , G06F13/16
CPC分类号： G06F12/0246 , G06F2212/7209 , G11C16/10 , G11C16/32 , G11C16/3454 , G11C2216/22 , G11C2216/24
摘要： This disclosure provides a multiple-plane flash memory device where high voltage programming (setting) or erasing (resetting) pulses are timed to occur simultaneously. By regulating when each memory plane (e.g., each logical or physical partition of memory having its own dedicated array control and page buffer) applies high voltage pulses, the overhead circuitry needed to control multiple concurrent operations may be reduced, thereby conserving valuable die space. Both the "program phase" and the "verify phase" of each state change operation cycle may be orchestrated across all planes at once, with shared timing and high voltage distribution.
摘要翻译：本公开提供了一种多平面闪速存储器件，其中高电压编程（设置）或擦除（复位）脉冲被定时同时发生。通过调节当每个存储器平面（例如，具有其自己的专用阵列控制和页面缓冲器的存储器的每个逻辑或物理分区）施加高电压脉冲时，可以减少控制多个并行操作所需的开销电路，从而节省有价值的管芯空间。每个状态改变操作周期的“程序阶段”和“验证阶段”可以一起在所有平面上协调，具有共享定时和高电压分布。

4. 发明申请

WO2010077414A1 NON-VOLATILE MEMORY DEVICE FOR CONCURRENT AND PIPELINED MEMORY OPERATIONS 审中-公开
标题翻译：用于并流和管道存储器操作的非易失性存储器件
公开(公告)号：WO2010077414A1
公开(公告)日：2010-07-08
申请号：PCT/US2009/060911
申请日：2009-10-15
申请人： RAMBUS INC. , HAUKNESS, Brent, Steven , SHAEFFER, Ian
发明人： HAUKNESS, Brent, Steven , SHAEFFER, Ian
IPC分类号： G11C16/10 , G11C16/26 , G11C16/04
CPC分类号： G11C16/26 , G11C16/10 , G11C2216/22
摘要： This disclosure provides a non-volatile memory device that concurrently processes multiple page reads, erases or writes involving the same memory space. The device relies upon a crossbar and a set of page buffers that may each be dynamically assigned to each read or write request. The device also separates memory array control from IO control, such that multiple cycle state change operations can be performed while the buffers are used to transfer data into and out of the buffers along an external data bus; using this structure, the memory device can accept multiple transactions where pages can be immediately loaded into buffers and then "pipelined" either for transfer to a write data register or to an external bus as appropriate. By significantly mitigating the substantial "busy time" associated with program and erase of non-volatile memory devices, especially flash devices, this disclosure greatly expands potential application of such devices.
摘要翻译：本公开提供了一种非易失性存储器设备，其同时处理涉及相同存储器空间的多页读取，擦除或写入。该设备依赖于交叉开关和一组页面缓冲器，每个缓冲器可以动态分配给每个读取或写入请求。该器件还将存储器阵列控制与IO控制分离，使得可以执行多个周期状态改变操作，同时缓冲器用于沿着外部数据总线将数据传入和传出缓冲器; 使用这种结构，存储设备可以接受多个事务，其中页面可以被立即加载到缓冲器中，然后“流水线化”以适当地传送到写数据寄存器或外部总线。通过显着地减轻与非易失性存储器件，特别是闪存器件的编程和擦除相关的实质性“繁忙时间”，该公开内容极大地扩展了这种器件的潜在应用。

5. 发明申请

WO2023278204A2 DRAM REFRESH CONTROL WITH MASTER WORDLINE GRANULARITY OF REFRESH INTERVALS 审中-公开
公开(公告)号：WO2023278204A2
公开(公告)日：2023-01-05
申请号：PCT/US2022/034350
申请日：2022-06-21
申请人： RAMBUS INC.
发明人： VOGELSANG, Thomas , PARTSCH, Torsten , HAUKNESS, Brent, Steven , LINSTADT, John, Eric
IPC分类号： G11C11/406 , G11C11/408 , G11C11/40611 , G11C11/40622
摘要： DRAM cells need to be periodically refreshed to preserve the charge stored in them. The retention time is typically not the same for all DRAM cells but follows a distribution with multiple orders of magnitude difference between the retention time of cells with the highest charge loss and the cells with the lowest charge loss. Different refresh intervals are used for certain wordlines based on the required minimum retention time of the cells on those wordlines. The memory controller does not keep track of refresh addresses. After initialization of the DRAM devices, the memory controller issues a smaller number of refresh commands when compared to refreshing all wordlines at the same refresh interval.

6. 发明申请

WO2015085093A1 2T-1R ARCHITECTURE FOR RESISTIVE RAM 审中-公开
标题翻译： 2T-1R电阻RAM结构
公开(公告)号：WO2015085093A1
公开(公告)日：2015-06-11
申请号：PCT/US2014/068624
申请日：2014-12-04
申请人： RAMBUS INC.
发明人： SEKAR, Deepak, Chandra , ELLIS, Wayne, Frederick , HAUKNESS, Brent, Steven , BRONNER, Gary, Bela , VOGELSANG, Thomas
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C2013/0083 , G11C2013/0088 , G11C2213/74 , G11C2213/79 , G11C2213/82
摘要： A memory device includes a plurality of resistive memory cells and a plurality of word lines. Each resistive memory cell includes a resistive memory element, a first switching element electrically coupled in series with the resistive memory element, and a second switching element electrically coupled in series with the first switching element. The first switching element and the second switching element in each resistive memory cell is coupled to different ones of the word lines.
摘要翻译：存储器件包括多个电阻存储器单元和多个字线。每个电阻性存储单元包括电阻性存储器元件，与电阻性存储元件串联电耦合的第一开关元件，以及与第一开关元件串联电耦合的第二开关元件。每个电阻存储单元中的第一开关元件和第二开关元件耦合到不同的字线。

7. 发明申请

WO2017192759A1 MEMORY COMPONENT WITH EFFICIENT WRITE OPERATIONS 审中-公开
标题翻译：有效写操作的存储器组件
公开(公告)号：WO2017192759A1
公开(公告)日：2017-11-09
申请号：PCT/US2017/030902
申请日：2017-05-03
申请人： RAMBUS INC.
发明人： WARE, Frederick, A. , LINSTADT, John, Eric , HAUKNESS, Brent, Steven , WRIGHT, Kenneth, L. , VOGELSANG, Thomas
IPC分类号： G06F12/00 , G11C7/10 , G11C11/401 , G11C11/4096
CPC分类号： G11C11/403 , G06F12/06 , G11C5/025 , G11C7/1018 , G11C7/1045 , G11C7/1096 , G11C7/18 , G11C8/08 , G11C11/40618 , G11C11/408 , G11C11/4085 , G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/4097
摘要： A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.
摘要翻译：存储器组件包括第一存储体。第一存储体具有多个具有存储元件子行的子阵列。存储器组件包括耦合到第一存储体的写入驱动器，用于执行子阵列的整个子行的写入操作。要执行写入操作，写入驱动程序需要将一连串写入数据加载到内存条。存储体然后可以激活与整个子行的多个存储元件相关联的多个读出放大器，以将写入数据的突发加载到多个读出放大器。

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