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1. 发明申请

WO2007112555A1 FLASH MEMORY SYSTEM CONTROL SCHEME 审中-公开
标题翻译：闪存存储器系统控制方案
公开(公告)号：WO2007112555A1
公开(公告)日：2007-10-11
申请号：PCT/CA2007/000501
申请日：2007-03-29
申请人： MOSAID TECHNOLOGIES INCORPORATED , KIM, Jin-Ki
发明人： KIM, Jin-Ki
IPC分类号： G11C7/10 , G11C11/4193 , G11C16/00
CPC分类号： G11C7/1042 , G06F12/0246 , G06F2212/1036 , G06F2212/7211 , G11C7/1021 , G11C16/10 , G11C16/32 , G11C2216/22 , G11C2216/24
摘要： A Flash memory system architecture having serially connected Flash memory devices to achieve high speed programming of data. High speed programming of data is achieved by interleaving pages of the data to be programmed amongst the memory devices in the system, such that different pages of data are stored in different memory devices. A memory controller issues program commands for each memory device. As each memory device receives a program command, it either begins a programming operation or passes the command to the next memory device. Therefore, the memory devices in the Flash system sequentially program pages of data one after the other, thereby minimizing delay in programming each page of data into the Flash memory system. The memory controller can execute a wear leveling algorithm to maximize the endurance of each memory device, or to optimize programming performance and endurance for data of any size.
摘要翻译：闪存系统架构具有串行连接的闪存设备，以实现数据的高速编程。通过将要编程的数据的页面交织在系统中的存储器件中来实现数据的高速编程，使得不同的数据页被存储在不同的存储器件中。存储器控制器为每个存储器件发出程序命令。当每个存储器件接收到程序命令时，它开始编程操作或将命令传递到下一个存储器件。因此，闪存系统中的存储器件一个接一个地顺序地编程数据页面，从而最小化将每一页数据编程到闪存系统中的延迟。存储器控制器可以执行磨损均衡算法以最大化每个存储器件的耐久性，或优化任何尺寸的数据的编程性能和耐久性。

2. 发明申请

WO2016118234A1 PARTIAL BLOCK ERASE FOR BLOCK PROGRAMMING IN NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器中的块编程的部分块擦除
公开(公告)号：WO2016118234A1
公开(公告)日：2016-07-28
申请号：PCT/US2015/062781
申请日：2015-11-25
申请人： SanDisk Technologies LLC
发明人： LAI, Chun-Hung , YIN, Cheng-Kuan , LEE, Shih-Chung , DUTTA, Deepanshu , OOWADA, Ken
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34 , G11C16/04
CPC分类号： G11C16/14 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3431 , G11C16/349 , G11C2211/5648 , G11C2216/24
摘要： A non-volatile memory system utilizes partial block erasing during program operations to mitigate the effects of programming pass voltage disturbances. A programming request is received that is associated with a group of word lines from a block, such as all or a portion of the word lines. The system erases and soft programs the block prior to beginning programming. The system programs a subset of the word lines of the block for the programming request. After programming the subset of word lines, the system pauses the programming operation and performs an erase operation for the unprogrammed word lines of the block. The already programmed word lines and one or more optional buffer word lines may be inhibited from erasing during the erase operation. After erasing the unprogrammed word lines, the system completes the programming request by programming the remaining user data in the unprogrammed region of the block.
摘要翻译：非易失性存储器系统在编程操作期间利用部分块擦除来减轻编程通过电压干扰的影响。接收与来自块的一组字线相关联的编程请求，例如字线的全部或一部分。在开始编程之前，系统擦除并软编程块。系统编程用于编程请求的块的字线的子集。在对字线子集编程之后，系统暂停编程操作，并对块的未编程字线执行擦除操作。可以在擦除操作期间禁止已经编程的字线和一个或多个可选的缓冲字线擦除。在擦除未编程的字线之后，系统通过对块的未编程区域中剩余的用户数据进行编程来完成编程请求。

3. 发明申请

WO2010090691A3 MULTIPLE PLANE, NON-VOLATILE MEMORY WITH SYNCHRONIZED CONTROL 审中-公开
标题翻译：具有同步控制的多平面，非易失性存储器
公开(公告)号：WO2010090691A3
公开(公告)日：2010-09-30
申请号：PCT/US2009069504
申请日：2009-12-23
申请人： RAMBUS INC , HAUKNESS BRENT STEVEN
发明人： HAUKNESS BRENT STEVEN
IPC分类号： G06F12/02 , G06F9/06 , G06F12/08 , G06F13/16
CPC分类号： G06F12/0246 , G06F2212/7209 , G11C16/10 , G11C16/32 , G11C16/3454 , G11C2216/22 , G11C2216/24
摘要： This disclosure provides a multiple-plane flash memory device where high voltage programming (setting) or erasing (resetting) pulses are timed to occur simultaneously. By regulating when each memory plane (e.g., each logical or physical partition of memory having its own dedicated array control and page buffer) applies high voltage pulses, the overhead circuitry needed to control multiple concurrent operations may be reduced, thereby conserving valuable die space. Both the "program phase" and the "verify phase" of each state change operation cycle may be orchestrated across all planes at once, with shared timing and high voltage distribution.
摘要翻译：本公开提供了一种多平面闪存设备，其中高电压编程（设置）或擦除（重置）脉冲被定时为同时发生。通过调节每个存储平面（例如，具有其自己的专用阵列控制和页缓冲器的存储器的每个逻辑或物理分区）何时施加高电压脉冲，可以减少控制多个并发操作所需的开销电路，从而节省宝贵的管芯空间。每个状态改变操作周期的“程序阶段”和“验证阶段”都可以一次跨所有平面进行编排，共享时序和高电压分布。

4. 发明申请

WO2010090691A2 MULTIPLE PLANE, NON-VOLATILE MEMORY WITH SYNCHRONIZED CONTROL 审中-公开
标题翻译：多平面，具有同步控制的非易失性存储器
公开(公告)号：WO2010090691A2
公开(公告)日：2010-08-12
申请号：PCT/US2009/069504
申请日：2009-12-23
申请人： RAMBUS INC. , HAUKNESS, Brent, Steven
发明人： HAUKNESS, Brent, Steven
IPC分类号： G06F12/02 , G06F12/08 , G06F9/06 , G06F13/16
CPC分类号： G06F12/0246 , G06F2212/7209 , G11C16/10 , G11C16/32 , G11C16/3454 , G11C2216/22 , G11C2216/24
摘要： This disclosure provides a multiple-plane flash memory device where high voltage programming (setting) or erasing (resetting) pulses are timed to occur simultaneously. By regulating when each memory plane (e.g., each logical or physical partition of memory having its own dedicated array control and page buffer) applies high voltage pulses, the overhead circuitry needed to control multiple concurrent operations may be reduced, thereby conserving valuable die space. Both the "program phase" and the "verify phase" of each state change operation cycle may be orchestrated across all planes at once, with shared timing and high voltage distribution.
摘要翻译：本公开提供了一种多平面闪速存储器件，其中高电压编程（设置）或擦除（复位）脉冲被定时同时发生。通过调节当每个存储器平面（例如，具有其自己的专用阵列控制和页面缓冲器的存储器的每个逻辑或物理分区）施加高电压脉冲时，可以减少控制多个并行操作所需的开销电路，从而节省有价值的管芯空间。每个状态改变操作周期的“程序阶段”和“验证阶段”可以一起在所有平面上协调，具有共享定时和高电压分布。

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