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1. 发明申请

WO2006001952A2 LOW POWER AND LOW TIMING JITTER PHASE-LOCK LOOP AND METHOD 审中-公开
标题翻译：低功率和低时序抖动器相位锁定和方法
公开(公告)号：WO2006001952A2
公开(公告)日：2006-01-05
申请号：PCT/US2005/017692
申请日：2005-05-18
申请人： MICRON TECHNOLOGY, INC. , CHOI, Dong, Myung
发明人： CHOI, Dong, Myung
IPC分类号： H03L7/00
CPC分类号： G06F1/04 , G11C7/02 , G11C7/1006 , G11C7/1018 , G11C7/1051 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/406 , G11C11/4076 , G11C11/4093 , H03L7/0891 , H03L7/0995 , H03L7/16 , H03L2207/10
摘要： A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLKOUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.
摘要翻译：锁相环从输入时钟信号产生输出时钟信号。输出时钟信号通过时钟树耦合并被反馈到相位检测器，该相位检测器将输出时钟信号的相位与输入时钟信号的相位进行比较。输出时钟信号由具有耦合以接收来自相位检测器的输出的控制输入的压控振荡器和耦合到压控振荡器的输出的倍频器产生。结果，由倍频器产生的CLKOUT信号具有相对高的频率，而压控振荡器通过以较低的频率运行使用相对较小的功率。

2. 发明申请

WO2003015102A1 同期型半導体記憶装置モジュールおよびその制御方法、情報機器审中-公开
标题翻译：同步半导体存储器件模块及其控制方法，信息器件
公开(公告)号：WO2003015102A1
公开(公告)日：2003-02-20
申请号：PCT/JP2002/007880
申请日：2002-08-01
申请人：シャープ株式会社 , 奥村寛
发明人：奥村寛
IPC分类号： G11C16/06
CPC分类号： G11C7/1072 , G11C7/1018 , G11C7/1027 , G11C7/1045 , G11C7/22 , G11C8/04 , G11C16/08
摘要： An access start address and a burst strength are specified by an input address signal and a data signal. An access end address is calculated from the access start address and the burst strength. According to an instruction from an internal control circuit (131A), a burst address calculation circuit (113) successively updates the address, counts the number of updates, and outputs the updated address to an address latch circuit (103). The burst address calculation circuit terminates its operation when the updated address is matched with the access end address and the number of updates is matched with the burst length, and changes the chip selection state when the updated address is matched with the final column address of one row address.
摘要翻译：访问开始地址和突发强度由输入地址信号和数据信号指定。从访问起始地址和突发强度计算访问结束地址。根据来自内部控制电路（131A）的指令，突发地址计算电路（113）连续更新地址，对更新次数进行计数，并将更新的地址输出到地址锁存电路（103）。突发地址计算电路在更新的地址与接入端地址匹配并且更新次数与突发长度匹配时终止其操作，并且当更新的地址与最后的列地址匹配时改变芯片选择状态行地址。

3. 发明申请

WO2003005368A1 半導体装置及びメモリモジュール审中-公开
标题翻译：半导体器件和存储器模块
公开(公告)号：WO2003005368A1
公开(公告)日：2003-01-16
申请号：PCT/JP2001/005794
申请日：2001-07-04
申请人：株式会社日立製作所 , 鮎川一重 , 三浦誓士 , 斉藤良和
发明人：鮎川一重 , 三浦誓士 , 斉藤良和
IPC分类号： G11C11/401
CPC分类号： G11C11/406 , G11C7/1018 , G11C2207/105 , H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/3025 , H01L2924/00012 , H01L2924/00
摘要： An inexpensive memory module in which burst access can be carried out at a high rate by packaging an SRAM, a DRAM and a control circuit together. The control circuit assigns addresses such that the forward part of burst access is allowed to access the SRAM and the rear part of burst access to access the DRAM. When the DRAM maps two chips to the same address space and refresh is carried out alternately, refresh is concealed and ease−of−use is enhanced thus realizing an inexpensive memory where burst access can be carried out at a high rate utilizing a large capacity DRAM. A large capacity memory where the DRAM does not require external refreshing is realized. Furthermore, the size can be reduced by mounting a plurality of semiconductor chips in one sealing body.
摘要翻译：一种廉价的存储器模块，其中可以通过将SRAM，DRAM和控制电路封装在一起，以高速率进行突发存取。控制电路分配地址，使得允许突发存取的前部访问SRAM和突发访问的后部以访问DRAM。当DRAM将两个芯片映射到相同的地址空间并且交替执行刷新时，刷新被隐藏并且易于使用被增强，从而实现廉价的存储器，其中可以利用大容量DRAM以高速率进行突发存取。实现了DRAM不需要外部刷新的大容量存储器。此外，通过将多个半导体芯片安装在一个密封体中，可以减小尺寸。

4. 发明申请

WO0193272A3 BURST ARCHITECTURE FOR A FLASH MEMORY 审中-公开
标题翻译：闪存存储器的爆炸结构
公开(公告)号：WO0193272A3
公开(公告)日：2002-03-28
申请号：PCT/US0116426
申请日：2001-05-21
申请人： ADVANCED MICRO DEVICES INC , FUJITSU LTD
发明人： AKAOGI TAKAO , CLEVELAND LEE , NGUYEN KENDRA
IPC分类号： G11C16/02 , G11C7/10 , G11C16/06
CPC分类号： G11C7/1018 , G11C7/1072
摘要： A burst mode architecture to provide burst mode access to a plurality of data words in a flash memory is described. The burst mode architecture includes a first circuit (216, 220), a control circuit (210) coupled to the first circuit (216, 220), and a data buffer (236, 238) selectively coupled to the first circuit (216, 220) by the control circuit (210). The first circuit (216, 220) accesses a plurality of data words, beginning with an initial access of a first data word and a second data word. The control circuit (210) generates a timing signal having pulses and a second signal. The second signal is generated upon completion of the initial access of the first data word and the second data word. The first circuit (216, 220) follows the initial access with subsequent accesses of the plurality of data words responsively to the second signal and the timing signal. The data buffer has an output and procedures the first data word at the output and successively produces, with each successive pulse of the timing signal following an initial period of time, the second data word, and subsequent data words at the output. The subsequent data words correspond to the subsequent accesses of the plurality of data words.
摘要翻译：描述了提供对闪存中的多个数据字的突发模式访问的突发模式架构。突发模式架构包括第一电路（216,220），耦合到第一电路（216,220）的控制电路（210）和选择性地耦合到第一电路（216,220）的数据缓冲器（236,238））控制电路（210）。第一电路（216,220）从第一数据字和第二数据字的初始访问开始访问多个数据字。控制电路（210）产生具有脉冲和第二信号的定时信号。完成第一数据字和第二数据字的初始访问时产生第二信号。第一电路（216,220）在响应于第二信号和定时信号的多个数据字的后续访问之后跟随初始访问。数据缓冲器具有输出并对输出端的第一个数据字进行处理，并且随着初始时间段之后的定时信号的每个连续脉冲，连续地产生第二数据字和输出端的后续数据字。随后的数据字对应于多个数据字的后续访问。

5. 发明申请

WO99041751A1 MEMORY DEVICE AND METHOD 审中-公开
标题翻译：存储器件和方法
公开(公告)号：WO99041751A1
公开(公告)日：1999-08-19
申请号：PCT/JP1999/000662
申请日：1999-02-16
IPC分类号： G11C11/401 , G06T1/60 , G11C7/10 , G11C8/00 , G11C8/04 , H04N5/21 , H04N5/44 , H04N5/907
CPC分类号： G11C7/1075 , G11C7/1018 , G11C8/04 , H04N5/21 , H04N5/907 , H04N7/012
摘要： A memory device for storing a sequential image data in succession and outputting the stored image data is provided. The memory device comprises a memory unit comprising N memory blocks, each memory block being capable of individual serving, a write address generator for generating a write address signal to write into the memory unit and a read address generator for generating a read address signal to read from the memory unit. The memory unit further comprises a controller for controlling the write address signal and the read address signal so that each start address for writing and reading for each image data is shifted as unit of the memory block and the writing and reading operations are not simultaneously performed to same memory block, each image data having a size being equivalent to one of M blocks (M
摘要翻译：提供了用于连续存储顺序图像数据并输出所存储的图像数据的存储器件。该存储装置包括存储单元，该存储单元包括N个存储块，每个存储块能够独立地存储;写入地址生成器，用于产生写入存储单元的写入地址信号;以及读取地址生成器，用于产生读取地址信号从存储单元。存储单元还包括控制器，用于控制写入地址信号和读取地址信号，使得用于每个图像数据的写入和读取的每个起始地址以存储块的单位移动，并且写入和读取操作不被同时执行到相同的存储块，每个图像数据具有等于M个块（M

6. 发明申请

WO1996034393A1 SEMICONDUCTOR STORAGE DEVICE, AND METHOD AND SYSTEM FOR MODULATING PULSE USED FOR THE DEVICE 审中-公开
标题翻译：半导体存储器件，以及用于调制用于器件的脉冲的方法和系统
公开(公告)号：WO1996034393A1
公开(公告)日：1996-10-31
申请号：PCT/JP1996000972
申请日：1996-04-09
申请人： HITACHI, LTD. , AOKI, Masakazu , SHIMOHIGASHI, Katsuhiro , YAMAKIDO, Kazuo , OISHI, Kanji , SATO, Katsuyuki , YANAGISAWA, Kazumasa , HORIGUCHI, Masashi , SAKATA, Takeshi , SEKIGUCHI, Tomonori
发明人： HITACHI, LTD.
IPC分类号： G11C11/407
CPC分类号： G11C7/1018 , G11C7/1072
摘要： A semiconductor storage device is provided with an address input circuit to which a row address signal is inputted synchronously with a row address strobe signal and a column address signal is inputted synchronously with a column address strobe signal, a memory array in which a plurality of dynamic memory cells are arranged in a matrix and address selection is performed in units of bits based on the address signal inputted through the address input circuit, a modulation circuit which pulse-modulates the data read out in the units of a plurality of bits by using the column address strobe signal as a reference signal, or a clock signal as the reference clock in the case of a synchronous dynamic RAM, and a demodulation circuit which demodulates the inputted pulse-modulated write signals. Therefore, the access speed to a memory can be substantially increased by inputting/outputting a large amount of data through pulse modulation while the input/ouput interface of an existing dynamic RAM or synchronous dynamic RAM is used as it is.
摘要翻译：半导体存储装置具有与行地址选通信号同步地输入行地址信号的地址输入电路，列列地址信号与列地址选通信号同步输入;存储器阵列，其中多个动态存储单元被布置成矩阵，并且基于通过地址输入电路输入的地址信号以位为单位执行地址选择;调制电路，其通过使用多个位以单位为单位读出的数据进行脉冲调制列地址选通信号作为参考信号，或时钟信号作为同步动态RAM的情况下的基准时钟，解调电路对输入的脉冲调制写入信号进行解调。因此，当现有的动态RAM或同步动态RAM的输入/输出接口原样使用时，通过脉冲调制输入/输出大量的数据可以大大提高对存储器的访问速度。

7. 发明申请

WO9629637A3 OPTIMIZATION CIRCUITRY AND CONTROL FOR A SYNCHRONOUS MEMORY DEVICE WITH PROGRAMMABLE LATENCY PERIOD 审中-公开
标题翻译：具有可编程时间段的同步存储器件的优化电路和控制
公开(公告)号：WO9629637A3
公开(公告)日：1996-10-31
申请号：PCT/US9603379
申请日：1996-03-12
申请人： MICRON TECHNOLOGY INC
发明人： ZAGAR PAUL STEPHEN , SCHAEGER SCOTT
IPC分类号： G11C11/413 , G06F20060101 , G06F12/00 , G11C8/00 , G11C11/407 , G11C11/408 , G11C13/00 , G06F
CPC分类号： G11C11/4082 , G11C7/1018 , G11C11/4076 , G11C11/4087
摘要： A method and apparatus for optimizing the speed path of a memory access operation in a synchronous depending upon the present latency period for the synchronous DRAM. The improved memory device compensates the time between row address latching and column address latching tRCD by delaying the presentment of the column address to compensate tRCD from the time available for column address latching to valid data-out (tAA) when tRCD is the critical parameter. Optimization circuitry reduces the amount of time available for tAA and 'shifts' it to the more critical parameter tRCD, enabling the optimization or reduction of the time allocated for tRCD by compensating tRCD with the extra time available for tAA. Thus, the memory access optimization circuitry enables an optmization or reduction in the total memory access time by compensating the optimized tRCD with the extra time available for tAA.

8. 发明申请

WO1988010478A1 PRINTING APPARATUS WITH IMPROVED DATA FORMATTING CIRCUITRY 审中-公开
标题翻译：具有改进数据格式化电路的打印设备
公开(公告)号：WO1988010478A1
公开(公告)日：1988-12-29
申请号：PCT/US1988002016
申请日：1988-06-13
申请人： EASTMAN KODAK COMPANY
发明人： EASTMAN KODAK COMPANY , GRETTER, Steven
IPC分类号： G06K15/12
CPC分类号： G06K15/1247 , G11C7/1018 , H04N1/193
摘要： An image recording apparatus (10) is provided with relatively inexpensive circuitry for formatting image signals to a printhead (20). The circuitry includes an integrated circuit memory chip (52) having sufficient buffer memory sites for storing either a full line of image signals to be printed or image signals sufficient for filling more than one shift register assemblage (41) associated with the recording element driving means. Rasterized image signals are fed to said memory chip (52) in consecutive sequential order. A printhead (20) includes a plurality of recording elements (30) such as LED's arranged in a line configuration. Driving means (44) actuate said elements for recording on a line by line basis. Intermediate register means (57, 58) outputs the image signals in parallel to each of the shift register assemblages (41). Image signals are read from the memory chip (52) means to the intermediate register means (57, 58) in a non-consecutive sequential order. The control for writing data into and reading data from the memory chip comprises a counter (53) and several flip-flop registers which together provide addresses to locations in the memory chip (52).

9. 发明申请

WO2016209556A1 INTERNAL CONSECUTIVE ROW ACCESS FOR LONG BURST LENGTH 审中-公开
标题翻译：内部协调一致的长期接触
公开(公告)号：WO2016209556A1
公开(公告)日：2016-12-29
申请号：PCT/US2016/034863
申请日：2016-05-27
申请人： INTEL CORPORATION
发明人： TOMISHIMA, Shigeki , LU, Shih-Lien , BAINS, Kuljit S.
IPC分类号： G06F13/28 , G06F13/16
CPC分类号： G06F3/0619 , G06F3/0659 , G06F3/0685 , G11C7/1018 , G11C7/1045 , G11C7/1072 , G11C11/4076
摘要： A memory device executes internal operations to provide a programmable burst length. The memory device includes multiple banks that are independent and separately addressable. The memory device selects a number of banks to operate in burst sequence, where all selected banks operate on a command sent from an associated memory controller. In response to receiving the access command, the memory device generates multiple internal operations to cause all selected memory banks to execute the access command, without requiring multiple commands from the memory controller.
摘要翻译：存储器件执行内部操作以提供可编程突发长度。存储器件包括独立且可单独寻址的多个存储体。存储器设备选择多个存储体以突发序列操作，其中所有选择的存储体基于从相关联的存储器控制器发送的命令操作。响应于接收到访问命令，存储器设备生成多个内部操作以使所有选定的存储体执行访问命令，而不需要来自存储器控制器的多个命令。

10. 发明申请

WO2010051621A1 BRIDGE DEVICE HAVING A VIRTUAL PAGE BUFFER 审中-公开
标题翻译：具有虚拟页面缓冲器的桥接器件
公开(公告)号：WO2010051621A1
公开(公告)日：2010-05-14
申请号：PCT/CA2009001537
申请日：2009-10-28
申请人： MOSAID TECHNOLOGIES INC , GILLINGHAM PETER B , PYEON HONG BEOM , KIM JIN-KI
发明人： GILLINGHAM PETER B , PYEON HONG BEOM , KIM JIN-KI
IPC分类号： G11C7/10 , G11C16/06
CPC分类号： G06F12/0238 , G06F3/0634 , G06F12/04 , G06F12/0646 , G06F13/36 , G06F13/4234 , G06F13/4291 , G11C7/10 , G11C7/1006 , G11C7/1018 , G11C7/1039 , G11C7/106 , G11C7/1087
摘要： A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has a virtual page buffer corresponding to each discrete memory device for storing read data from the discrete memory device, or write data from an external device. The virtual page buffer is configurable to have a size up to the maximum physical size of the page buffer of a discrete memory device. The page buffer is then logically divided into page segments, where each page segment corresponds in size to the configured virtual page buffer size. By storing read or write data in the virtual page buffer, both the discrete memory device and the external device can operate to provide or receive data at different data rates to maximize the performance of both devices.
摘要翻译：包括分立存储器装置和用于控制分立存储器装置的桥接器件的复合存储器装置。桥接设备具有对应于每个分立存储器设备的虚拟页面缓冲器，用于存储来自分立存储器设备的读取数据或写入来自外部设备的数据。虚拟页面缓冲器可被配置为具有高达分立存储器设备的页面缓冲器的最大物理尺寸的大小。页面缓冲区然后在逻辑上被分成页面段，其中每个页面段的大小对应于配置的虚拟页面缓冲区大小。通过在虚拟页面缓冲器中存储读取或写入数据，分立存储器设备和外部设备都可以操作以提供或接收不同数据速率的数据，以最大化两个设备的性能。

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