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1. 发明申请

WO2020117481A1 OFF-MODULE DATA BUFFER 审中-公开
公开(公告)号：WO2020117481A1
公开(公告)日：2020-06-11
申请号：PCT/US2019/062568
申请日：2019-11-21
申请人： RAMBUS INC.
发明人： WARE, Frederick, A. , HAYWOOD, Christopher
IPC分类号： G11C11/4093 , G11C11/4096 , G11C5/04
摘要： In a modular memory system, a memory control component, first and second memory sockets and data buffer components are all mounted to the printed circuit board. The first and second memory sockets have electrical contacts to electrically engage counterpart electrical contacts of memory modules to be inserted therein, and each of the data buffer components includes a primary data interface electrically coupled to the memory control component, and first and second secondary data interfaces electrically coupled to subsets of the electrical contacts within the first and second memory sockets, respectively.

2. 发明申请

WO2018080783A1 HYBRID MEMORY MODULE 审中-公开
标题翻译：混合存储模块
公开(公告)号：WO2018080783A1
公开(公告)日：2018-05-03
申请号：PCT/US2017/055908
申请日：2017-10-10
申请人： RAMBUS INC.
发明人： WARE, Frederick, A. , LINSTADT, John, Eric , WRIGHT, Kenneth, L.
IPC分类号： G06F11/10 , G06F12/02 , G11C7/10 , G11C11/4093
摘要： A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.
摘要翻译：存储器模块包括服务于较大量的相对较慢且对磨损敏感的非易失性存储器的相对快速和持久的动态随机存取存储器（DRAM）的缓存。本地控制器管理DRAM高速缓存和非易失性存储器之间的通信，以适应不同的访问粒度，减少必需的内存事务数量，并最大限度地减少非易失性内存组件外部的数据流。

3. 发明申请

WO2017192759A1 MEMORY COMPONENT WITH EFFICIENT WRITE OPERATIONS 审中-公开
标题翻译：有效写操作的存储器组件
公开(公告)号：WO2017192759A1
公开(公告)日：2017-11-09
申请号：PCT/US2017/030902
申请日：2017-05-03
申请人： RAMBUS INC.
发明人： WARE, Frederick, A. , LINSTADT, John, Eric , HAUKNESS, Brent, Steven , WRIGHT, Kenneth, L. , VOGELSANG, Thomas
IPC分类号： G06F12/00 , G11C7/10 , G11C11/401 , G11C11/4096
CPC分类号： G11C11/403 , G06F12/06 , G11C5/025 , G11C7/1018 , G11C7/1045 , G11C7/1096 , G11C7/18 , G11C8/08 , G11C11/40618 , G11C11/408 , G11C11/4085 , G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/4097
摘要： A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.
摘要翻译：存储器组件包括第一存储体。第一存储体具有多个具有存储元件子行的子阵列。存储器组件包括耦合到第一存储体的写入驱动器，用于执行子阵列的整个子行的写入操作。要执行写入操作，写入驱动程序需要将一连串写入数据加载到内存条。存储体然后可以激活与整个子行的多个存储元件相关联的多个读出放大器，以将写入数据的突发加载到多个读出放大器。

4. 发明申请

WO2016081192A1 MEMORY SYSTEMS AND METHODS FOR IMPROVED POWER MANAGEMENT 审中-公开
标题翻译：用于改进电源管理的存储系统和方法
公开(公告)号：WO2016081192A1
公开(公告)日：2016-05-26
申请号：PCT/US2015/058956
申请日：2015-11-04
申请人： RAMBUS INC.
发明人： WARE, Frederick, A. , HARRIS, James, E.
IPC分类号： G06F12/00
CPC分类号： G11C11/4093 , G11C5/04 , G11C5/063 , G11C7/22 , G11C8/12
摘要： A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.
摘要翻译：具有多个存储器件的存储器模块包括管理存储器控制器和存储器件之间的通信的缓冲器系统。每个存储器件支持访问模式和低功耗模式，后者用于为不立即需要的设备节省电力。该模块使用芯片选择解码器提供细粒度的功率管理，芯片选择解码器将来自存储器控制器的芯片选择信号解码为确定哪些存储器件是哪种模式的功率状态信号。因此，根据需要，设备可以以相对较小的数量从低功率模式中脱离，以限制功耗。

5. 发明申请

WO2013141921A1 HIGH CAPACITY MEMORY SYSTEMS 审中-公开
标题翻译：高容量存储系统
公开(公告)号：WO2013141921A1
公开(公告)日：2013-09-26
申请号：PCT/US2012/071036
申请日：2012-12-20
申请人： RAMBUS INC.
发明人： WARE, Frederick, A. , TSERN, Ely, K. , LEIBOWITZ, Brian, S. , ELLIS, Wayne, Frederick , BANSAL, Akash , BROOKS, John, Welsford , KASAMSETTY, Kishore, Ven
IPC分类号： G11C7/10 , G11C7/22 , G11C8/00 , G11C11/4096 , G06F13/14
CPC分类号： G11C8/18 , G06F13/161 , G06F13/1647 , G06F13/1657 , G06F13/4234 , G11C5/02 , G11C5/04 , G11C7/10 , G11C7/1072 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine- interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such "microthreading" provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.
摘要翻译：在允许每个等级的时钟分配树被允许在宽范围内漂移（例如，低功率存储器系统）的多存储器存储器系统中，通过使用引起每个寻址的技术来促进等级之间的命令的精细交错排名适当地采样旨在该等级的命令，尽管有漂移。执行这种“微线程”的能力提供了显着增强的存储器容量，而不牺牲单级系统的性能。本公开提供了适于这些目的的方法，存储器控制器，存储器件和系统设计。

6. 发明申请

WO2012125719A2 METHODS AND APPARATUS FOR TESTING INACCESSIBLE INTERFACE CIRCUITS IN A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于测试半导体器件中不可接受的接口电路的方法和装置
公开(公告)号：WO2012125719A2
公开(公告)日：2012-09-20
申请号：PCT/US2012/029071
申请日：2012-03-14
申请人： RAMBUS INC. , WARE, Frederick, A.
发明人： WARE, Frederick, A.
IPC分类号： G01R31/3183
CPC分类号： G01R31/2882 , G01R31/2607 , G01R31/31726 , G11C29/022 , G11C29/12015 , G11C29/16 , G11C29/50012 , G11C2029/0401 , H03L7/00
摘要： A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.
摘要翻译：半导体IC器件包括用于传送定时信号的定时电路，定时电路被配置为接收第一测试信号并且响应于第一测试信号实现定时信号的延迟，第一测试信号包括第一定时事件。半导体IC器件还包括接口电路，被配置为响应于定时信号传送数据信号，接口电路还被配置为接收第二测试信号并且响应于第二测试信号来实现数据信号的延迟所述第二测试信号包括根据测试标准与所述第一定时事件相关的第二定时事件。

7. 发明申请

WO2010101754A2 MEMORY INTERFACE WITH INTERLEAVED CONTROL INFORMATION 审中-公开
标题翻译：具有交互控制信息的记忆接口
公开(公告)号：WO2010101754A2
公开(公告)日：2010-09-10
申请号：PCT/US2010/025316
申请日：2010-02-25
申请人： RAMBUS INC. , WARE, Frederick, A.
发明人： WARE, Frederick, A.
IPC分类号： G11C7/10 , G11C7/22 , G11C8/04
CPC分类号： G11C7/1006 , G06F13/1647 , G11C7/1009 , G11C7/1012 , G11C8/04 , Y02D10/14
摘要： A memory system communicates at least partially temporally overlapping write-data sequences associated with independent column write accesses on data links from a memory controller to a memory device via bidirectional links. Each of these write-data sequences may be associated with a different bank set in the memory IC. These bank sets may be micro-threaded so that each bank set is independently addressable and can concurrently perform operations associated with independent commands, including simultaneous column read/write. Furthermore, temporally interleaved data-mask information for the write-data sequences may be communicated from the memory controller to the memory IC via a data-mask link, so that alternate bits in the interleaved data-mask information may correspond to different write sequences.
摘要翻译：存储器系统通过双向链路将与数据链路上的独立列写访问相关联的至少部分时间上重叠的写数据序列从存储器控制器传送到存储器设备。这些写入数据序列中的每一个可以与存储器IC中的不同的存储体组相关联。这些存储体组可以是微线程的，使得每个存储体集可独立地寻址，并且可以同时执行与独立命令相关联的操作，包括同时列读/写。此外，用于写数据序列的时间交织的数据掩码信息可以经由数据掩码链路从存储器控制器传送到存储器IC，使得交错数据掩码信息中的交替位可对应于不同的写序列。

8. 发明申请

WO2008057557A2 MEMORY SYSTEM SUPPORTING NONVOLATILE PHYSICAL MEMORY 审中-公开
标题翻译：支持非易失性物理内存的存储器系统
公开(公告)号：WO2008057557A2
公开(公告)日：2008-05-15
申请号：PCT/US2007/023432
申请日：2007-11-06
申请人： RAMBUS INC. , WARE, Frederick, A. , TSERN, Ely, K.
发明人： WARE, Frederick, A. , TSERN, Ely, K.
CPC分类号： G06F12/0253 , G06F12/0246 , G06F12/08 , G06F12/0802 , G06F12/0804 , G06F12/0891 , G06F12/1009 , G06F2212/1036 , G06F2212/2022 , G06F2212/60 , G06F2212/7201 , G06F2212/7205 , G06F2212/7211
摘要： A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.
摘要翻译：存储器系统包括非易失性物理存储器，例如闪存，其呈现与写入操作不对称关联的磨损机制。易失性存储器的相对较小的缓存减少了写入次数，并且耗损均衡的存储器访问方法均匀地将写入分散在非易失性存储器中。

9. 发明申请

WO2008014189A2 PARTITIONED GAME CONSOLE SYSTEM 审中-公开
标题翻译：分区游戏控制台系统
公开(公告)号：WO2008014189A2
公开(公告)日：2008-01-31
申请号：PCT/US2007/073964
申请日：2007-07-20
申请人： RAMBUS INC. , WARE, Frederick, A. , TSERN, Ely, K.
发明人： WARE, Frederick, A. , TSERN, Ely, K.
IPC分类号： G06F1/20
CPC分类号： A63F13/23 , A63F13/00 , A63F2300/203 , A63F2300/405 , A63F2300/538 , G06F1/20
摘要： The game console system includes a user interface module and a graphics processing module that are remotely situated from one another and solely coupled to one another via one or more communication links. The graphics processing module is positioned within a controlled environment chamber that thermally and acoustically isolates the user interface module from the graphics processing module. The user interface module includes a controller and a console coupled to the controller. The console also is configured to be coupled to a display.
摘要翻译：游戏控制台系统包括用户界面模块和图形处理模块，它们彼此远离地定位并且经由一个或多个通信链路彼此单独耦合。图形处理模块位于受控环境室内，该受控环境室将用户界面模块与图形处理模块热和声学隔离。用户界面模块包括控制器和耦合到控制器的控制台。控制台也被配置为连接到显示器。

10. 发明申请

WO2005072329A3 COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS 审中-公开
公开(公告)号：WO2005072329A3
公开(公告)日：2005-08-11
申请号：PCT/US2005/002301
申请日：2005-01-25
申请人： RAMBUS, INC. , WARE, Frederick, A. , PEREGO, Richard, E. , HAMPEL, Craig, E.
发明人： WARE, Frederick, A. , PEREGO, Richard, E. , HAMPEL, Craig, E.
IPC分类号： H04B3/00
摘要： A method provides for execution of calibration cycles during normal operation of the communication channel (1002). A calibration cycle includes de-coupling the normal data source (1010) from the transmitter (1003) and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver (1004) on the second component (1001). A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel (1002). For bidirectional links, calibration cycles are executed which include the step of storing received calibration pattern on the second component (1001), and retransmitting such calibration back to the first component (1000) for use in adjusting parameter of the channel at first component (1000).

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