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1. 发明申请

WO2003058164A1 MACHINE AND METHOD OF INSPECTING INPUT SHAFT OF POWER STEERING SYSTEM 审中-公开
标题翻译：检查动力转向系统输入轴的机器和方法
公开(公告)号：WO2003058164A1
公开(公告)日：2003-07-17
申请号：PCT/KR2002/002255
申请日：2002-11-30
申请人： PAHK, Heui-Jae , HWANG, Moon-Tae , KIM, Jin-Ki
发明人： PAHK, Heui-Jae , HWANG, Moon-Tae , KIM, Jin-Ki
IPC分类号： G01B11/30
CPC分类号： G01B11/00
摘要： Provided is a machine and a method for inspecting an input shaft of a power system. First an second cameras take a photograph of first and second champer of the input shaft from directions perpendicular to the chamfers to capture image data of the chamfers. The input shaft is rotated by an indexing drive until overlapping a central line of first and second chamfers of an input shaft on a standard line of image array coordinate system of a computer. Then, widths of the first and second chamfers of the input shaft is calculated. Thereafter, the indexing drive rotates the input shaft by predetermined degrees. The computer processes image data of another first and second chamfers captured by the first and second cameras and calculates widths of the another first and second chamfers. Continuously, widths of remaining chamfers of the input shaft are calculated.
摘要翻译：提供了一种用于检查电力系统的输入轴的机器和方法。首先，第二台摄像机从垂直于倒角的方向拍摄输入轴的第一和第二个遮阳篷，以捕获倒角的图像数据。输入轴通过分度驱动器旋转，直到在计算机的图像阵列坐标系的标准线上的输入轴的第一和第二倒角的中心线重叠。然后，计算输入轴的第一和第二倒角的宽度。此后，分度驱动器将输入轴旋转一定程度。计算机处理由第一和第二相机捕获的另一个第一和第二倒角的图像数据，并计算另一个第一和第二倒角的宽度。连续地计算输入轴的剩余倒角的宽度。

2. 发明申请

WO2010043032A1 A COMPOSITE MEMORY HAVING A BRIDGING DEVICE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM 审中-公开
标题翻译：具有用于将分离存储器件连接到系统的桥接器件的复合存储器
公开(公告)号：WO2010043032A1
公开(公告)日：2010-04-22
申请号：PCT/CA2009/001451
申请日：2009-10-14
申请人： MOSAID TECHNOLOGIES INCORPORATED , KIM, Jin-Ki , PYEON, Hong, Beom
发明人： KIM, Jin-Ki , PYEON, Hong, Beom
IPC分类号： G11C7/10 , G11C16/06 , G11C5/06 , G11C7/22
CPC分类号： G11C7/00 , G11C5/02 , G11C5/025
摘要： A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices which respond to native, or local memory control signals. The global and local memory control signals include commands and command signals each having different formats. The composite memory device includes a system in package including the semiconductor dies of the discrete memory devices and the bridge device, or can include a printed circuit board having packaged discrete memory devices and a packaged bridge device mounted thereto.
摘要翻译：一种复合存储器件，包括分立存储器件和用于响应具有与存储器件不兼容的格式或协议的全局存储器控制信号来控制分立存储器件的桥接器件。分立存储器件可以是对现有或本地存储器控制信号进行响应的商业现成存储器件或定制存储器件。全局和本地存储器控制信号包括各自具有不同格式的命令和命令信号。复合存储器件包括包括分立存储器件和桥接器件的半导体管芯的封装的系统，或者可以包括具有封装的分立存储器件的印刷电路板和安装在其上的封装桥接器件。

3. 发明申请

WO2008101318A1 SYSTEM AND METHOD OF PAGE BUFFER OPERATION FOR MEMORY DEVICES 审中-公开
标题翻译：用于存储器件的页面缓冲器操作的系统和方法
公开(公告)号：WO2008101318A1
公开(公告)日：2008-08-28
申请号：PCT/CA2008/000287
申请日：2008-02-15
申请人： MOSAID TECHNOLOGIES INCORPORATED , PYEON, Hong Beom , KIM, Jin-Ki , OH, HakJune
发明人： PYEON, Hong Beom , KIM, Jin-Ki , OH, HakJune
IPC分类号： G11C7/10 , G06F12/00 , G11C16/02
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/1044 , G06F2212/2022 , G06F2212/3042 , G06F2212/7203 , G06F2212/7208 , G11C7/1039 , G11C7/106 , G11C7/1087 , G11C2207/2245
摘要： Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.
摘要翻译：提供了系统和方法，用于使用通过公共总线连接到存储器控制器的存储器件的页缓冲器。使用存储器件的页缓冲器作为写入存储器件的存储单元的数据的临时高速缓存。这可以允许内存控制器使用内存设备作为临时缓存，以便内存控制器可以释放自己内存中的空间。

4. 发明申请

WO2008064480A1 FLASH MEMORY PROGRAM INHIBIT SCHEME 审中-公开
标题翻译：闪存存储器程序禁止方案
公开(公告)号：WO2008064480A1
公开(公告)日：2008-06-05
申请号：PCT/CA2007/002149
申请日：2007-11-29
申请人： MOSAID TECHNOLOGIES INCORPORATED , KIM, Jin-Ki
发明人： KIM, Jin-Ki
IPC分类号： G11C7/12 , G11C16/24
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/24 , G11C16/3418 , G11C16/3427
摘要： A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a NAND string where no programming is desired, is decoupled from the other cells in the NAND string. This allows the channel of the decoupled cell to be locally boosted to a voltage level sufficient for inhibiting F-N tunneling when the corresponding wordline is raised to a programming voltage. Due to the high boosting efficiency, the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming.
摘要翻译：一种用于最小化闪存中程序干扰的方法。为了减少在不需要擦除状态的编程的NAND闪存单元串中的程序干扰，使用局部增强的通道抑制方案。在本地提升通道禁止方案中，在NAND串中未选择编程的NAND串中选择的存储单元与NAND串中的其它单元解耦。这使得解耦单元的通道在相应的字线升高到编程电压时被局部提升到足以抑制F-N隧穿的电压电平。由于高的提升效率，相对于现有技术的方案，可以减少施加到NAND串中的剩余存储单元的栅极的通过电压，从而最小化程序干扰同时允许随机页面编程。

5. 发明申请

WO2008022454A1 SCALABLE MEMORY SYSTEM 审中-公开
标题翻译：可扩展存储系统
公开(公告)号：WO2008022454A1
公开(公告)日：2008-02-28
申请号：PCT/CA2007/001469
申请日：2007-08-22
申请人： MOSAID TECHNOLOGIES INCORPORATED , KIM, Jin-Ki , OH, HakJune , PYEON, Hong Beom , PRZYBYLSKI, Steven
发明人： KIM, Jin-Ki , OH, HakJune , PYEON, Hong Beom , PRZYBYLSKI, Steven
IPC分类号： G11C7/10 , G11C5/14 , G11C8/18
CPC分类号： G11C7/1042 , G11C7/10 , G11C7/1072 , G11C7/1078 , G11C7/20 , G11C8/04 , G11C16/0483
摘要： A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.
摘要翻译：存储器系统架构具有串行连接的存储器件。内存系统是可扩展的，可以包括任何数量的内存设备，而不会造成任何性能下降或重新设计。每个存储器件具有用于在其他存储器件和存储器控制器之间通信的串行输入/输出接口。存储器控制器在至少一个比特流中发出命令，其中比特流遵循模块化命令协议。该命令包括具有可选地址信息和设备地址的操作代码，使得只有寻址的存储器件对该命令起作用。分别提供与每个输出数据流和输入命令数据流并行提供的数据输出选通信号和命令输入选通信号，用于识别数据的类型和数据的长度。模块化命令协议用于在每个存储设备中执行并发操作，以进一步提高性能。

6. 发明申请

WO2007112555A1 FLASH MEMORY SYSTEM CONTROL SCHEME 审中-公开
标题翻译：闪存存储器系统控制方案
公开(公告)号：WO2007112555A1
公开(公告)日：2007-10-11
申请号：PCT/CA2007/000501
申请日：2007-03-29
申请人： MOSAID TECHNOLOGIES INCORPORATED , KIM, Jin-Ki
发明人： KIM, Jin-Ki
IPC分类号： G11C7/10 , G11C11/4193 , G11C16/00
CPC分类号： G11C7/1042 , G06F12/0246 , G06F2212/1036 , G06F2212/7211 , G11C7/1021 , G11C16/10 , G11C16/32 , G11C2216/22 , G11C2216/24
摘要： A Flash memory system architecture having serially connected Flash memory devices to achieve high speed programming of data. High speed programming of data is achieved by interleaving pages of the data to be programmed amongst the memory devices in the system, such that different pages of data are stored in different memory devices. A memory controller issues program commands for each memory device. As each memory device receives a program command, it either begins a programming operation or passes the command to the next memory device. Therefore, the memory devices in the Flash system sequentially program pages of data one after the other, thereby minimizing delay in programming each page of data into the Flash memory system. The memory controller can execute a wear leveling algorithm to maximize the endurance of each memory device, or to optimize programming performance and endurance for data of any size.
摘要翻译：闪存系统架构具有串行连接的闪存设备，以实现数据的高速编程。通过将要编程的数据的页面交织在系统中的存储器件中来实现数据的高速编程，使得不同的数据页被存储在不同的存储器件中。存储器控制器为每个存储器件发出程序命令。当每个存储器件接收到程序命令时，它开始编程操作或将命令传递到下一个存储器件。因此，闪存系统中的存储器件一个接一个地顺序地编程数据页面，从而最小化将每一页数据编程到闪存系统中的延迟。存储器控制器可以执行磨损均衡算法以最大化每个存储器件的耐久性，或优化任何尺寸的数据的编程性能和耐久性。

7. 发明申请

WO2011134055A1 WRITE SCHEME IN PHASE CHANGE MEMORY 审中-公开
标题翻译：相变记忆中的写入方案
公开(公告)号：WO2011134055A1
公开(公告)日：2011-11-03
申请号：PCT/CA2011/000472
申请日：2011-04-26
申请人： MOSAID TECHNOLOGIES INCORPORATED , KIM, Jin-Ki
发明人： KIM, Jin-Ki
IPC分类号： G11C7/00 , G11C13/00 , G11C7/22
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0035 , G11C13/0061 , G11C13/0064 , G11C2013/0054 , G11C2013/0076 , G11C2013/0088 , G11C2213/72
摘要： In a phase change memory, an input data corresponding to a plurality of memory cells is received and a previous data is read from the plurality of memory cells. The input data is compared with the previous data. In the case where the input data is different from the previous data for one or more of the plurality of memory cells and a write count is less than a maximum value, one or more of the plurality of memory cells is programmed with the input data and the write count is updated or incremented. Such operations of data comparison and update of the write count are repeated. If the write count reaches the maximum value, it will be determined that the writing is falied.
摘要翻译：在相变存储器中，接收对应于多个存储单元的输入数据，并从多个存储单元读取先前的数据。将输入数据与先前的数据进行比较。在输入数据与多个存储单元中的一个或多个的先前数据不同且写入数小于最大值的情况下，多个存储器单元中的一个或多个用输入数据编程，并且写入计数更新或增加。重复数据比较和更新写入次数的这种操作。如果写入计数达到最大值，则会确定写入是否成功。

8. 发明申请

WO2010054478A1 SOLID STATE DRIVE OR OTHER STORAGE APPARATUS THAT INCLUDES A PLURALITY OF ENCAPSULATED SEMICONDUCTOR CHIPS 审中-公开
标题翻译：固态驱动器或其他存储设备，包括多个封装的半导体芯片
公开(公告)号：WO2010054478A1
公开(公告)日：2010-05-20
申请号：PCT/CA2009/001638
申请日：2009-11-13
申请人： MOSAID TECHNOLOGIES INCORPORATED , KIM, Jin-Ki
发明人： KIM, Jin-Ki
IPC分类号： H01L25/065 , G06F3/06 , G11C16/02 , G11C5/02 , G11C7/10 , H01L27/115 , H05K3/06
CPC分类号： G06F1/16 , G06F3/0626 , G06F3/0658 , G06F3/0679 , H01L23/3121 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L2224/45014 , H01L2224/48091 , H01L2224/48137 , H01L2224/49175 , H01L2924/00014 , H01L2924/14 , H05K3/284 , H05K2201/10159 , H05K2203/049 , H01L2224/45099 , H01L2924/00
摘要： A solid state drive is disclosed. The solid state drive includes a circuit board having opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the circuit board of the solid state drive, and the plurality of semiconductor chips of the solid state drive include at least one memory chip that is at least substantially encapsulated in a resin. An in-line memory module-type form factor circuit board is also disclosed. The in-line memory module-type form factor circuit board has opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the in-line memory module-type form factor circuit board, and these semiconductor chips include at least one memory chip that is at least substantially encapsulated in a resin.
摘要翻译：公开了一种固态驱动器。固态驱动器包括具有相对的第一和第二表面的电路板。多个半导体芯片附接到固态驱动器的电路板的第一表面，并且固态驱动器的多个半导体芯片包括至少基本上封装在树脂中的至少一个存储器芯片。还公开了一种在线存储器模块型形状电路板。在线存储器模块型外形电路板具有相对的第一和第二表面。多个半导体芯片附接到直列式存储模块型形状电路板的第一表面，并且这些半导体芯片包括至少基本上封装在树脂中的至少一个存储芯片。

9. 发明申请

WO2010000062A1 MULTIPLE-BIT PER CELL (MBC) NON-VOLATILE MEMORY APPARATUS AND SYSTEM HAVING POLARITY CONTROL AND METHOD OF PROGRAMMING SAME 审中-公开
标题翻译：多单元单元（MBC）非易失性存储器装置和具有极性控制的系统及其编程方法
公开(公告)号：WO2010000062A1
公开(公告)日：2010-01-07
申请号：PCT/CA2009/000892
申请日：2009-06-30
申请人： MOSAID TECHNOLOGIES INCORPORATED , KIM, Jin-Ki , PETRIE, William
发明人： KIM, Jin-Ki , PETRIE, William
IPC分类号： G11C16/02 , G11C11/56 , G11C16/10 , G11C16/26
CPC分类号： G11C16/10 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C29/00 , G11C2211/5646 , G11C2211/5647
摘要： A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M-1) virtual pages and selectively inverts data words to minimize a number of bits to be programmed in an Mth virtual page where M is the number of bits per cell. A corresponding polarity control flag is set when a data word is inverted. Data is selectively inverted according the corresponding polarity flag when being read from the M virtual pages. A number of the highest threshold voltage programming states in reduced. This provides tighter distribution of programmed cell threshold voltage, reduced power consumption, reduced programming time, and enhanced device reliability.
摘要翻译：一种多位单元（MBC）非易失性存储装置，方法和系统，其中用于向/从存储器阵列写入/读取数据的控制器通过选择性地反转数据字来控制数据的极性，以使位的数量最大化为（M-1）个虚拟页面内编程，并选择性地反转数据字以最小化要在第M个虚拟页面中编程的位数，其中M是每个单元的位数。当数据字反转时，设置相应的极性控制标志。当从M个虚拟页面读取时，根据相应的极性标志选择性地反转数据。一些最高阈值电压编程状态在减少。这提供了编程单元阈值电压的更严格的分配，降低的功耗，减少的编程时间和增强的器件可靠性。

10. 发明申请

WO2009092152A8 NAND FLASH MEMORY ACCESS WITH RELAXED TIMING CONSTRAINTS 审中-公开
公开(公告)号：WO2009092152A8
公开(公告)日：2009-07-30
申请号：PCT/CA2008/002155
申请日：2008-12-15
申请人： MOSAID TECHNOLOGIES INCORPORATED , KIM, Jin-Ki
发明人： KIM, Jin-Ki
IPC分类号： G11C16/06
摘要： Timing constraints on data transfers during access of a NAND flash memory can be relaxed by providing a plurality of data paths that couple the NAND flash memory to a buffer that provides external access to the memory. The buffer defines a bit width associated with the external access, and each of the data paths accommodates that bit width.

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