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1. 发明申请

WO2005119753A2 SYSTEMS AND METHODS FOR NANOWIRE GROWTH AND HARVESTING 审中-公开
标题翻译：用于纳米生长和收获的系统和方法
公开(公告)号：WO2005119753A2
公开(公告)日：2005-12-15
申请号：PCT/US2005/014923
申请日：2005-04-29
申请人： NANOSYS, INC. , PAN, Yaoling , DUAN, Xiangfeng , DUBROW, Bob , GOLDMAN, Jay , MOSTARSHED, Shahriar , NIU, Chunming , ROMANO, Linda T. , STUMBO, Dave
发明人： PAN, Yaoling , DUAN, Xiangfeng , DUBROW, Bob , GOLDMAN, Jay , MOSTARSHED, Shahriar , NIU, Chunming , ROMANO, Linda T. , STUMBO, Dave
IPC分类号： H01L21/425
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/162 , C01B32/18 , C30B11/12 , C30B25/00 , C30B29/06 , C30B29/60 , C30B29/605 , H01L21/0237 , H01L21/02381 , H01L21/02422 , H01L21/02521 , H01L21/02573 , H01L21/02603 , H01L21/0262 , H01L21/02645 , H01L21/02653 , H01L29/0665 , H01L29/66477 , H01L29/78 , H01L29/7854 , H01L2924/0002 , Y10S438/962 , Y10S977/742 , Y10S977/743 , Y10S977/843 , Y10S977/891 , H01L2924/00
摘要： The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrifical growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.
摘要翻译：本发明涉及用于纳米线生长和收获的系统和方法。在一个实施方案中，提供了纳米线生长和掺杂的方法，包括使用硅前体的组合的用于外延取向的纳米线生长的方法。在本发明的另一方面，提供了通过使用牺牲生长层来提高纳米线质量的方法。在本发明的另一方面，提供了将纳米线从一个衬底转移到另一个衬底的方法。

2. 发明申请

WO2007136412A2 METHODS FOR ORIENTED GROWTH OF NANOWIRES ON PATTERNED SUBSTRATES 审中-公开
标题翻译：用于在图案化基底上的纳米线的生长的方法
公开(公告)号：WO2007136412A2
公开(公告)日：2007-11-29
申请号：PCT/US2006/048456
申请日：2006-12-20
申请人： NANOSYS, INC. , PAN, Yaoling , DUAN, Xiangfeng , DUBROW, Robert, S. , GOLDMAN, Jay, L. , MOSTARSHED, Shahriar , NIU, Chunming , ROMANO, Linda, T. , STUMBO, David, P. , FISCHER-COLBRIE, Alice , SAHI, Vijendra , ROBBINS, Virginia
发明人： PAN, Yaoling , DUAN, Xiangfeng , DUBROW, Robert, S. , GOLDMAN, Jay, L. , MOSTARSHED, Shahriar , NIU, Chunming , ROMANO, Linda, T. , STUMBO, David, P. , FISCHER-COLBRIE, Alice , SAHI, Vijendra , ROBBINS, Virginia
IPC分类号： B21C1/00
CPC分类号： C30B29/605 , B82Y30/00 , C30B11/12 , C30B29/06 , Y10T428/24917
摘要： The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors, as well as us of patterned substrates to grow oriented nanowires. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrifical growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.
摘要翻译：本发明涉及用于纳米线生长和收获的系统和方法。在一个实施例中，提供了用于纳米线生长和掺杂的方法，包括使用硅前体的组合的外延取向纳米线生长的方法，以及我们用于生长取向的纳米线的图案化衬底。在本发明的另一方面，提供了通过使用牺牲生长层来提高纳米线质量的方法。在本发明的另一方面，提供了将纳米线从一个衬底转移到另一个衬底的方法。

3. 发明申请

WO2007030126A2 METHOD, SYSTEM, AND APPARATUS FOR GATING CONFIGURATIONS AND IMPROVED CONTACTS IN NANOWIRE-BASED ELECTRONIC DEVICES 审中-公开
标题翻译：用于在纳米级电子设备中进行配置和改进联系的方法，系统和设备
公开(公告)号：WO2007030126A2
公开(公告)日：2007-03-15
申请号：PCT/US2005/037237
申请日：2005-10-14
申请人： NANOSYS, INC. , MOSTARSHED, Shahriar , CHEN, Jian , LEON, Francisco , PAN, Yaoling , ROMANO, Linda T.
发明人： MOSTARSHED, Shahriar , CHEN, Jian , LEON, Francisco , PAN, Yaoling , ROMANO, Linda T.
IPC分类号： H01L29/76
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/775 , H01L29/785 , H01L29/78645 , H01L29/78681 , H01L29/7869 , Y10S977/762 , Y10S977/932 , Y10S977/938
摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.
摘要翻译：描述了具有改进的门结构的电子设备的方法，系统和装置。电子装置包括至少一个纳米线。栅极接触沿至少一个纳米线的长度的至少一部分定位。介电材料层在栅极接触和至少一个纳米线之间。源极触点和漏极触点与至少一个纳米线接触。源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。环形第一栅极区域沿着纳米线长度的一部分包围纳米线。第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

4. 发明申请

WO2007038164A3 METHODS FOR NANOSTRUCTURE DOPING 审中-公开
公开(公告)号：WO2007038164A3
公开(公告)日：2007-04-05
申请号：PCT/US2006/036738
申请日：2006-09-21
申请人： NANOSYS, INC. , PAN, Yaoling , CHEN, Jian , LEON, Francisco , MOSTARSHED, Shahriar , ROMANO, Linda T. , SAHI, Vijendra , STUMBO, David P.
发明人： PAN, Yaoling , CHEN, Jian , LEON, Francisco , MOSTARSHED, Shahriar , ROMANO, Linda T. , SAHI, Vijendra , STUMBO, David P.
IPC分类号： H01L29/06 , H01L21/225
摘要： Methods of doping nanostructures, such as nanowires, are disclosed. The methods provide a variety of approaches for improving existing methods of doping nanostructures. The embodiments include the use of a sacrificial layer to promote uniform dopant distribution within a nanostructure during post-nanostructure synthesis doping. In another embodiment, a high temperature environment is used to anneal nanostructure damage when high energy ion implantation is used. In another embodiment rapid thermal annealing is used to drive dopants from a dopant layer on a nanostructure into the nanostructure. In another embodiment a method for doping nanowires on a plastic substrate is provided that includes depositing a dielectric stack on a plastic substrate to protect the plastic substrate from damage during the doping process. An embodiment is also provided that includes selectively using high concentrations of dopant materials at various times in synthesizing nanostructures to realize novel crystallographic structures within the resulting nanostructure.

5. 发明申请

WO2004003535A1 PLANAR NANOWIRE BASED SENSOR ELEMENTS, DEVICES, SYSTEMS AND METHODS FOR USING AND MAKING SAME 审中-公开
标题翻译：基于平面的纳米级传感器元件，设备，系统和使用和制造它们的方法
公开(公告)号：WO2004003535A1
公开(公告)日：2004-01-08
申请号：PCT/US2003/020336
申请日：2003-06-26
申请人： NANOSYS INC. , PONTIS, George , STONAS, Walter , CHOW, Calvin , PARCE, Wallace, J. , PAN, Yaoling , ROMANO, Linda, T. , MOSTARSHED, Shahriar
发明人： PONTIS, George , STONAS, Walter , CHOW, Calvin , PARCE, Wallace, J. , PAN, Yaoling , ROMANO, Linda, T. , MOSTARSHED, Shahriar
IPC分类号： G01N27/04
CPC分类号： H01L29/0665 , B82Y10/00 , C30B29/605 , G01N27/4146 , H01L29/0673
摘要： Sensor elements and devices that incorporate those elements are provided, where the sensor comprises a thin semiconductor nanowire (202) that is disposed upon, and integral to, an insulating substrate (204), where the nanowire (202) is electrically coupled to a sensing surface (210) that binds or otherwise interacts with an analyte (114) of interest to yield a measurable effect on the nanowire element (202). The methods utilize extremely thin semiconductor (020) on insulator substrates (204) to provide nanowire dimensions for sensing elements that are fabricated using conventional semiconductor fabrication processes.
摘要翻译：提供了包含这些元件的传感器元件和器件，其中传感器包括薄的半导体纳米线（202），该半导体纳米线设置在绝缘衬底（204）上并且与绝缘衬底（204）成一体，其中纳米线（202）电耦合到感测表面（210），其结合或以其它方式与感兴趣的分析物（114）相互作用以产生对纳米线元件（202）的可测量的影响。这些方法利用绝缘体上的非常薄的半导体（020）（204）来提供用于使用传统半导体制造工艺制造的感测元件的纳米线尺寸。

6. 发明申请

WO2007056257A2 SEMI-AUTOMATIC MULTIPLEXING SYSTEM FOR AUTOMATED SEMICONDUCTOR WAFER TESTING 审中-公开
标题翻译：用于自动半导体波形测试的半自动多路复用系统
公开(公告)号：WO2007056257A2
公开(公告)日：2007-05-18
申请号：PCT/US2006/043148
申请日：2006-11-03
申请人： QUALITAU, INC. , MOSTARSHED, Shahriar , ANDERSON, Michael, L.
发明人： MOSTARSHED, Shahriar , ANDERSON, Michael, L.
IPC分类号： G01R31/02
CPC分类号： G01R31/2889 , G01R1/07385
摘要： A semi-automatic multiplexing system for automated semiconductor wafer testing employs a jumper block for each device type in the semiconductor wafer to be tested, each jumper block having inputs for receiving a test input/output line, a plurality of block contacts corresponding to pads of a device to be tested, and manually set connectors or jumper cables for selectively interconnecting jumper block inputs to block contacts. A multiplexer is then used for selectively connecting tester input/output lines to the jumper blocks, thereby reducing the number of relays required for connecting test signals to the devices in the semiconductor wafer.
摘要翻译：用于自动化半导体晶片测试的半自动多路复用系统对要测试的半导体晶片中的每种器件类型使用跳线块，每个跳线块具有用于接收测试输入/输出线的输入，对应于测试输入/输出线的多个块触点要测试的设备，并手动设置连接器或跳线，用于选择性地将跳线块输入连接到阻塞触点。然后，多路复用器用于将测试器输入/输出线选择性地连接到跳线块，从而减少将测试信号连接到半导体晶片中的器件所需的继电器数量。

7. 发明申请

WO2007019072A2 VERTICAL PROBE CARD AND AIR COOLED PROBE HEAD SYSTEM 审中-公开
标题翻译：垂直探头卡和空气冷却探头系统
公开(公告)号：WO2007019072A2
公开(公告)日：2007-02-15
申请号：PCT/US2006/029245
申请日：2006-07-25
申请人： QUALITAU, INC. , ANDERSON, Michael L. , MCCLOUD, Edward A. , MOSTARSHED, Shahriar , CASOLO, Michael A.
发明人： ANDERSON, Michael L. , MCCLOUD, Edward A. , MOSTARSHED, Shahriar , CASOLO, Michael A.
IPC分类号： G01R31/02
CPC分类号： G01R1/07342 , G01R1/06727
摘要： A probe card is vertically mounted generally perpendicular to a wafer undergoing life tests in a heated environment to limit exposure of the probe card to heat from the wafer chuck. The probe card and probe head assembly are mounted on a support rail which has one or more channels for the flow of cool air to a probe head assembly and the probe card, while it shields the flex cable from the hot chuck. The cool air flow disrupts convective hot air flow upwards from the heated chuck to the probe card and probe head and facilitates cooling of the probe card and probe head.
摘要翻译：探针卡通常垂直于垂直于在加热环境中进行寿命测试的晶片垂直安装，以限制探针卡暴露于晶片卡盘的热量。探针卡和探针头组件安装在支撑轨道上，该支撑轨道具有一个或多个通道，用于将冷空气流动到探头头部组件和探针卡，同时屏蔽柔性电缆与热卡盘。冷气流破坏对流热气流从加热卡盘向上探针卡和探针头，并有助于冷却探针卡和探针头。

8. 发明申请

WO2008121155A1 AUTOMATIC MULTIPLEXING SYSTEM FOR AUTOMATED WAFER TESTING 审中-公开
标题翻译：自动多路复用系统自动测试
公开(公告)号：WO2008121155A1
公开(公告)日：2008-10-09
申请号：PCT/US2007/080389
申请日：2007-10-04
申请人： QUALITAU, INC. , MOSTARSHED, Shahriar , ANDERSON, Michael, L.
发明人： MOSTARSHED, Shahriar , ANDERSON, Michael, L.
IPC分类号： G01R31/02
CPC分类号： G01R31/2889 , G01R1/07385 , G01R31/2834
摘要： A parametric test system is for testing devices in dice in a semiconductor wafer, each die having a plurality of pads for electrically connecting to the device in the die. A tester of the system has a plurality of input/output lines for providing and receiving electrical signals during a device test. Multiplexer circuitry of the test system includes a plurality of networks of automated switches. The multiplexer circuitry is configured to receive electrical signals on the input lines from the tester and to provide the electrical signals to a wafer prober, wherein the multiplexer circuitry is configured to restrict how the electrical signals can be provided to the networks of automated switches. As a result of the multiplexer being configured to restrict how the electrical signals can be provided to the networks of automated switches, the configuration of the networks of automated switches can be simplified.
摘要翻译：参数测试系统用于在半导体晶片中的骰子中测试器件，每个管芯具有用于电连接到管芯中的器件的多个焊盘。系统的测试器具有多个输入/输出线，用于在器件测试期间提供和接收电信号。测试系统的多路复用器电路包括多个自动开关网络。多路复用器电路被配置为从测试器接收输入线路上的电信号，并将电信号提供给晶片探测器，其中多路复用器电路被配置为限制如何将电信号提供给自动切换器的网络。由于多路复用器被配置为限制如何将电信号提供给自动交换机的网络，所以可以简化自动交换机网络的配置。

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