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1. 发明申请

WO2018063335A1 TUNNELING TRANSISTORS INCLUDING SOURCE/DRAIN REGIONS EMPLOYING CARBON-BASED ETCH STOP LAYER 审中-公开
标题翻译：包括源/漏区在内的隧道晶体管使用碳基蚀刻停止层
公开(公告)号：WO2018063335A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054810
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： GLASS, Glenn A. , MURTHY, Anand S. , YOUNG, Ian A. , AVCI, Uygar E.
IPC分类号： H01L29/78 , H01L29/73 , H01L29/66 , H01L21/8238 , H01L29/423
CPC分类号： H01L29/7391 , B82Y10/00 , H01L21/8238 , H01L29/0673 , H01L29/0834 , H01L29/165 , H01L29/205 , H01L29/417 , H01L29/41725 , H01L29/66356 , H01L29/775 , H01L29/785
摘要： Techniques are disclosed for forming tunneling transistors including source and drain (S/D) regions employing a carbon-based etch stop layer. The carbon-based etch stop layer may be formed on an S/D region to help prevent S/D contact trench etch processing from undesirably etching into the S/D region. In addition, in some cases, material bandgap engineering may be used to enhance the ability of tunneling transistor devices, such as tunnel field-effect transistors (TFETs) and Fermi filter FETs (FFFETs), to resist off-state leakage currents from source to drain (through the channel) and from source to ground/substrate. Such material bandgap engineering can incorporate a material-based band offset component by using different material in the S/D regions to control off-state leakage, to expand upon the limited energy band offset achievable using single-composition material configurations. Increasing the band offset can increase the barrier that carriers must overcome to reach the channel region, thereby reducing off-state leakage.
摘要翻译：公开了用于形成包括采用碳基蚀刻停止层的源极和漏极（S / D）区域的隧穿晶体管的技术。基于碳的蚀刻停止层可以形成在S / D区上以帮助防止S / D接触沟槽蚀刻处理不希望地蚀刻到S / D区中。另外，在一些情况下，可以使用材料带隙工程来增强诸如隧道场效应晶体管（TFET）和费米滤波器FET（FFFET）之类的隧道晶体管器件的能力以抵抗来自源的截止状态漏电流到漏极（通过通道）和从源极到地/基板。这种材料带隙工程可以通过使用S / D区域中的不同材料来控制截止状态泄漏，从而在使用单组分材料构造可实现的有限能带偏移时扩展基于材料的带偏移分量。增加频带偏移可以增加载波必须克服的到达信道区域的屏障，从而减少关闭状态泄漏。

2. 发明申请

WO2018063270A1 QUANTUM DOT DEVICES WITH SINGLE ELECTRON TRANSISTOR DETECTORS 审中-公开
标题翻译：具有单电子晶体管探测器的量子点器件
公开(公告)号：WO2018063270A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054615
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： GEORGE, Hubert C. , PILLARISETTY, Ravi , THOMAS, Nicole K. , ROBERTS, Jeanette M. , CLARKE, James S.
IPC分类号： H01L29/66 , H01L29/78 , H01L29/80
CPC分类号： H01L29/122 , H01L29/42356 , H01L29/66469 , H01L29/66977 , H01L29/7613 , H01L29/775 , H01L29/7781 , H01L29/82
摘要： Disclosed herein are quantum dot devices with single electron transistor (SET) detectors. In some embodiments, a quantum dot device may include: a quantum dot formation region; a group of gates disposed on the quantum dot formation region, wherein the group of gates includes at least first, second, and third gates, spacers are disposed on sides of the first and second gates, wherein a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate, and the third gate is disposed between the first and second gates and extends between the first and second spacers; and a SET disposed on the quantum dot formation region, proximate to the group of gates.
摘要翻译：这里公开的是具有单电子晶体管（SET）检测器的量子点器件。在一些实施例中，量子点器件可以包括：量子点形成区域; 设置在所述量子点形成区域上的一组栅极，其中所述栅极组至少包括第一栅极，第二栅极和第三栅极，所述第一栅极和所述第二栅极的侧面设置有间隔物，其中第一间隔物设置在所述量子点的一侧靠近第二栅极的第一栅极和与第一栅极物理分离的第二栅极布置在靠近第一栅极的第二栅极的一侧上，并且第三栅极布置在第一和第二栅极之间并延伸在第一和第二隔离物之间; 以及设置在量子点形成区域上的SET，靠近该组栅极。

3. 发明申请

WO2017191356A1 AN APPARATUS AND METHOD OF FORMING AN APPARATUS COMPRISING A GRAPHENE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：一种形成包括石墨场效应晶体管的装置的设备和方法
公开(公告)号：WO2017191356A1
公开(公告)日：2017-11-09
申请号：PCT/FI2017/050299
申请日：2017-04-20
申请人： NOKIA TECHNOLOGIES OY
发明人： HARRIS, Nadine , WHITE, Richard
IPC分类号： H01L31/0352 , H01L31/112
CPC分类号： H01L29/1606 , B82Y10/00 , B82Y15/00 , H01L29/151 , H01L29/66439 , H01L29/66977 , H01L29/775 , H01L31/0203 , H01L31/02161 , H01L31/02165 , H01L31/028 , H01L31/035218 , H01L31/1129 , H01L31/1804
摘要： An apparatus and method of forming an apparatus, the apparatus comprising: a graphene field effect transistor where the graphene field effect transistor comprises a graphene channel and quantum dots provided overlaying the graphene channel, wherein the quantum dots comprise a first layer comprising quantum dots connected to a first ligand and a second layer comprising quantum dots connected to a second ligand, and wherein the first ligand is configured to cause the first layer to have a first refractive index and the second ligand is configured to cause the second layer to have a second refractive index wherein the second refractive index is different to the first refractive index.
摘要翻译：一种形成装置的设备和方法，所述设备包括：石墨烯场效应晶体管，其中所述石墨烯场效应晶体管包括石墨烯沟道和提供的覆盖所述石墨烯沟道的量子点，其中所述量子点包括包含连接到第一配体的量子点的第一层和包含连接到第二配体的量子点的第二层，并且其中所述第一配体被配置成使所述第一层具有第一折射率，并且所述第二配体被配置为引起第二层具有第二折射率，其中第二折射率不同于第一折射率。

4. 发明申请

WO2017171759A1 GEOMETRY TUNING OF FIN BASED TRANSISTOR 审中-公开
标题翻译：基于FIN晶体管的几何调谐
公开(公告)号：WO2017171759A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025070
申请日：2016-03-30
申请人： INTEL CORPORATION
发明人： GLASS, Glenn A. , MURTHY, Anand S. , JAMBUNATHAN, Karthik , MOHAPATRA, Chandra S. , KAM, Hei , MISTKAWI, Nabil G. , KANG, Jun Sung , GUHA, Biswajeet
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7851 , B82Y10/00 , H01L21/3081 , H01L21/823807 , H01L21/823821 , H01L21/8258 , H01L27/0924 , H01L29/0669 , H01L29/0673 , H01L29/0847 , H01L29/1037 , H01L29/4232 , H01L29/66439 , H01L29/66545 , H01L29/6681 , H01L29/66818 , H01L29/775 , H01L29/78
摘要： A trench is formed in an insulating layer to expose a native fin on a substrate. A replacement fin is deposited on the native fin in the trench. The replacement fin is trimmed laterally.
摘要翻译：沟槽形成在绝缘层中以暴露衬底上的自然鳍。替换翅片放置在沟槽中的原生翅片上。替换翅片横向修剪。

5. 发明申请

WO2017116545A1 NANOWIRE TRANSISTOR WITH REDUCED PARASITICS AND METHOD FOR MAKING SUCH A TRANSISTOR 审中-公开
标题翻译：具有减少的寄生虫的纳米晶体晶体管及制造这种晶体管的方法
公开(公告)号：WO2017116545A1
公开(公告)日：2017-07-06
申请号：PCT/US2016/059219
申请日：2016-10-27
申请人： QUALCOMM INCORPORATED
发明人： BADAROGLU, Mustafa , MACHKAOUTSAN, Vladimir , SONG, Stanley Seungchul , XU, Jeffrey Junhao , NOWAK, Matthew Michael , YEAP, Choh Fei
IPC分类号： B82Y10/00 , H01L29/66 , H01L29/775 , H01L29/06 , H01L29/08
CPC分类号： H01L29/42392 , B82Y10/00 , H01L21/02507 , H01L21/02532 , H01L21/762 , H01L29/0653 , H01L29/0673 , H01L29/086 , H01L29/0878 , H01L29/165 , H01L29/4966 , H01L29/66439 , H01L29/66484 , H01L29/66545 , H01L29/66795 , H01L29/775 , H01L29/7831
摘要： A nanowire (130) transistor is provided that includes a well implant having a local isolation region (120) for insulating a replacement metal gate (405) from a parasitic channel and oxidized caps (125) in the extension regions that inhibit parasitic gate-to-source and gate- to-drain capacitances. The method for making the device includes forming a fin of alternating selectively etchable layers (eg. Si and SiGe); doping the extension (source / drain) regions of these layers with an etch stop dopant (carbon); performing a selective etch for one of the materials; and selectively oxidizing the extension region (215) corresponding to the sacrificial layer, thus forming an oxidized cap (125).
摘要翻译：提供纳米线（130）晶体管，其包括具有局部隔离区（120）的阱注入物，所述局部隔离区（120）用于使替代金属栅极（405）与寄生沟道中的绝缘层和绝缘沟道中的氧化帽（125）扩展区域，可抑制寄生栅极至源极和栅极至漏极电容。用于制造器件的方法包括形成交替选择性蚀刻层（例如，Si和SiGe）的鳍; 用蚀刻停止掺杂剂（碳）掺杂这些层的延伸区（源极/漏极）区域; 对其中一种材料进行选择性蚀刻; 并选择性氧化对应于牺牲层的延伸区域（215），从而形成氧化帽（125）。

6. 发明申请

WO2017111797A1 FABRICATION OF NON-PLANAR IGZO DEVICES FOR IMPROVED ELECTROSTATICS 审中-公开
标题翻译：非平面IGZO装置的制造以改进静电学
公开(公告)号：WO2017111797A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000319
申请日：2015-12-23
申请人： INTEL CORPORATION
发明人： LE, Van, H. , DEWEY, Gilbert , RIOS, Rafael , KAVALIEROS, Jack, T. , RADOSAVLJEVIC, Marko , MILLARD, Kent, E. , FRENCH, Marc, C. , AGRAWAL, Ashish , CHU-KUNG, Benjamin , ARCH, Ryan, E.
IPC分类号： H01L27/12 , H01L29/78 , H01L21/336
CPC分类号： H01L27/12 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/78
摘要： Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.
摘要翻译：本发明的实施例包括非平面InGaZnO（IGZO）晶体管和形成这种器件的方法。在一个实施例中，IGZO晶体管可以包括衬底以及形成在衬底上的源极区和漏极区。根据一个实施例，IGZO层可以形成在衬底上方并且可以电耦合到源极区域和漏极区域。其他实施例包括通过栅极电介质与IGZO层分离的栅电极。在一个实施例中，栅极电介质接触IGZO层的多于一个表面。在一个实施例中，IGZO晶体管是finfet晶体管。在另一个实施例中，IGZO晶体管是纳米线或纳米带晶体管。本发明的实施例还可以包括形成在集成电路芯片的线堆栈（BEOL）的后端的非平面IGZO晶体管。

7. 发明申请

WO2017052617A1 SEMICONDUCTOR DEVICE CONTACTS WITH INCREASED CONTACT AREA 审中-公开
标题翻译：半导体器件与增加的接触面接触
公开(公告)号：WO2017052617A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052330
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： MEHANDRU, Rishabh , GHANI, Tahir , LIAO, Szuya S.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , B82Y10/00 , H01L29/0673 , H01L29/41725 , H01L29/66439 , H01L29/775
摘要： Semiconductor contact architectures are provided, wherein contact metal extends into the semiconductor layer to which contact is being made, thereby increasing contact area. An offset spacer allows a relatively deep etch into the semiconductor material to be achieved. Thus, rather than just a flat horizontal surface of the semiconductor being exposed for contact area, relatively long vertical trench sidewalls and a bottom wall are exposed and available for contact area. The trench can then be filled with the desired contact metal. Doping of the semiconductor layer into which the contact is being formed can be carried out in a manner that facilitates an efficient contact trench etch process, such as by, for example, utilization of post trench etch doping or a semiconductor layer having an upper undoped region through which the contact trench etch passes and a lower doped S/D region. The offset spacer may be removed from final structure.
摘要翻译：提供半导体接触结构，其中接触金属延伸到正在形成接触的半导体层中，从而增加接触面积。偏移间隔物允许实现对半导体材料的相对深的蚀刻。因此，不仅仅是半导体的平坦的水平表面暴露于接触区域，相对长的垂直沟槽侧壁和底壁被暴露并且可用于接触区域。然后可以用期望的接触金属填充沟槽。可以以促进有效的接触沟槽蚀刻工艺的方式来进行其中形成接触的半导体层的掺杂，例如通过使用后沟槽蚀刻掺杂或具有上部未掺杂区域的半导体层接触沟槽蚀刻通过该沟槽蚀刻和较低掺杂的S / D区域。可以从最终结构中去除偏移间隔物。

8. 发明申请

WO2016209210A1 INDIUM-RICH NMOS TRANSISTOR CHANNELS 审中-公开
标题翻译： INDIUM-RICH NMOS晶体管通道
公开(公告)号：WO2016209210A1
公开(公告)日：2016-12-29
申请号：PCT/US2015/037141
申请日：2015-06-23
申请人： INTEL CORPORATION
发明人： MOHAPATRA, Chandra S. , MURTHY, Anand S. , GLASS, Glenn A. , GHANI, Tahir , RACHMADY, Willy , KAVALIEROS, Jack T. , DEWEY, Gilbert , METZ, Matthew V. , KENNEL, Harold W.
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L27/0886 , H01L29/1054 , H01L29/125 , H01L29/205 , H01L29/66795 , H01L29/775
摘要： Techniques are disclosed for forming high mobility NMOS fin-based transistors having an indium-rich channel region electrically isolated from the sub-fin by an aluminum-containing layer. The aluminum aluminum-containing layer may be provisioned within an indium-containing layer that includes the indium-rich channel region, or may be provisioned between the indium-containing layer and the sub-fin. The indium concentration of the indium-containing layer may be graded from an indium-poor concentration near the aluminum-containing barrier layer to an indium-rich concentration at the indium-rich channel layer. The indium-rich channel layer is at or otherwise proximate to the top of the fin, according to some example embodiments. The grading can be intentional and/or due to the effect of reorganization of atoms at the interface of indium-rich channel layer and the aluminum-containing barrier layer. Numerous variations and embodiments will be appreciated in light of this disclosure.
摘要翻译：公开了用于形成具有通过含铝层与子鳍电隔离的富铟沟道区的高迁移率的NMOS鳍状晶体管的技术。含铝的铝层可以设置在包含富铟沟道区域的含铟层内，或者可以在含铟层和副散热片之间设置。含铟层的铟浓度可以从富含铟的沟道层的含铝阻挡层附近的铟 - 贫的浓度分级为富铟浓度。根据一些示例性实施例，富铟通道层处于或接近翅片的顶部。分级可以是有意的和/或由于在富铟沟道层和含铝阻挡层的界面处重组原子的作用。根据本公开将理解许多变型和实施例。

9. 发明申请

WO2016085570A1 CONTACT WRAP AROUND STRUCTURE 审中-公开
标题翻译：接缝带结构
公开(公告)号：WO2016085570A1
公开(公告)日：2016-06-02
申请号：PCT/US2015/053305
申请日：2015-09-30
申请人： QUALCOMM INCORPORATED
发明人： XU, Jeffrey Junhao , SONG, Stanley Seungchul , MACHKAOUTSAN, Valdimir , BADAROGLU, Mustafa , BAO, Junjing , ZHU, John Jianhong , YANG, Da , YEAP, Choh Fei
IPC分类号： H01L29/417 , H01L29/66 , H01L29/78
CPC分类号： H01L27/0924 , H01L21/285 , H01L21/76897 , H01L21/823821 , H01L29/0673 , H01L29/0847 , H01L29/41791 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78696 , H01L2029/7858
摘要： A semiconductor device includes a gate stack. The semiconductor device also includes a wrap-around contact arranged around and contacting substantially all surface area of a regrown source/drain region of the semiconductor device proximate to the gate stack.
摘要翻译：半导体器件包括栅极堆叠。半导体器件还包括环绕接触件，该环绕触点布置在接近栅极堆叠处的半导体器件的再生长源极/漏极区域的基本上所有的表面区域周围。

10. 发明申请

WO2016048336A1 SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译：半导体器件的选择栅极间隔
公开(公告)号：WO2016048336A1
公开(公告)日：2016-03-31
申请号：PCT/US2014/057585
申请日：2014-09-26
申请人： INTEL CORPORATION , CLENDENNING, Scott B. , LIAO, Szuya S. , GSTREIN, Florian , HOURANI, Rami , ROMERO, Patricio E. , KLOSTER, Grant M. , MITAN, Martin M.
发明人： CLENDENNING, Scott B. , LIAO, Szuya S. , GSTREIN, Florian , HOURANI, Rami , ROMERO, Patricio E. , KLOSTER, Grant M. , MITAN, Martin M.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0673 , H01L21/265 , H01L21/28247 , H01L29/42364 , H01L29/4983 , H01L29/51 , H01L29/66439 , H01L29/66545 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.
摘要翻译：讨论了与形成用于半导体器件和晶体管结构的选择性栅极间隔物以及使用这种技术形成的器件有关的技术。这样的技术包括在半导体鳍片上形成阻挡材料，在阻挡材料的一部分上设置具有与阻挡材料不同的表面化学性质的栅极，在栅极上形成选择性共形层，而不是在阻挡材料的一部分上，以及去除封闭材料的暴露部分。

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