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    • 2. 发明申请
    • TWIN-CLUTCH DEVICE
    • 双离合器件
    • WO2010004410A1
    • 2010-01-14
    • PCT/IB2009/006187
    • 2009-07-08
    • TOYOTA JIDOSHA KABUSHIKI KAISHAOGAWA, HiroyukiMURAKAMI, Akira
    • OGAWA, HiroyukiMURAKAMI, Akira
    • F16D37/02
    • F16D37/02Y10T74/19228
    • In a twin-clutch device that selectively transmits torque from a driving wheel (9) to a first driven wheel (10) and/or a second driven wheel (11), the first and second driven wheels (10, 11) are arranged respectively on both sides of the driving wheel (9), a functional fluid (23) that decreases its flowability as an applied stimulus is increased and that increases its flowability as the applied stimulus is reduced fills gaps between the driving wheel (9) and the first and second driven wheels (10, 11), the driving wheel (9) includes a stimulus generating member (17) electrically controlled to generate a stimulus, and flowability of the functional fluid (23) between the driving wheel (9) and one of the first and second driven wheels (10, 11) is decreased with an increase in stimulus applied to the functional fluid (23) by the stimulus generating member (17) to couple the driving wheel (9) to the one of the first and second driven wheels (10, 11), thus allowing torque transmission therebetween.
    • 在从驱动轮(9)到第一从动轮(10)和/或第二从动轮(11)选择性地传递扭矩的双离合器装置中,分别布置第一和第二从动轮(10,11) 在驱动轮(9)的两侧,随着施加的刺激而降低其流动性的功能流体(23)增加,并且随着施加的刺激被减小而增加其流动性填充驱动轮(9)和第一 和第二从动轮(10,11),所述驱动轮(9)包括电控制以产生刺激的刺激产生构件(17)和所述驱动轮(9)之间的功能流体(23)之间的流动性 随着由刺激产生构件(17)施加到功能流体(23)的刺激的增加,第一和第二从动轮(10,11)减小,以将驱动轮(9)联接到第一和第二驱动轮 从动轮(10,11),从而允许扭矩传递 切口白内障手术挽。
    • 4. 发明申请
    • SPACERS BETWEEN BITLINES IN VIRTUAL GROUND MEMORY ARRAY
    • 虚拟地面记忆阵列中的位置之间的间距
    • WO2007035245A1
    • 2007-03-29
    • PCT/US2006/034508
    • 2006-09-06
    • SPANSION LLCOGAWA, Hiroyuki
    • OGAWA, Hiroyuki
    • H01L27/115H01L21/8247
    • H01L27/11521H01L27/115
    • According to one exemplary embodiment, a method of fabricating a virtual ground memory array, which includes bitlines (402,404,406) situated in a substrate (434), includes forming (370) at least one recess (436,438) in the substrate (434) between two adjacent bitlines (402,404,406), where the at least one recess (436,438) is situated in a bitline contact region (132) of the virtual ground memory array, and where the at least one recess (436,438) defines sidewalls (452) and a bottom surface (454) in the substrate (434). The step of forming (370) the at least one recess (436,438) includes using hard mask segments (208,210,212) as a mask, where each of the hard mask segments (208,210,212) is situated over a bitline (202,204,206). The method further includes forming (374) a spacer (460,462) in the at least one recess (436,438), where the spacer (460,462) reduces bitline-to-bitline leakage between the adjacent bitlines (402,404,406). The method further includes forming stacked gate structures (114,116,118) before forming (370) the at least one recess (436,438), where each stacked gate structure (114,116,118) is situated over and perpendicular to the bitlines (102,104,106).
    • 根据一个示例性实施例,制造虚拟接地存储器阵列的方法,其包括位于衬底(434)中的位线(402,404,406),包括在衬底(434)中形成(370)至少一个凹部(436,438) 相邻位线(402,404,406),其中所述至少一个凹部(436,438)位于所述虚拟接地存储器阵列的位线接触区域(132)中,并且其中所述至少一个凹部(436,438)限定侧壁(452)和底部 衬底(434)中的表面(454)。 形成(370)所述至少一个凹部(436,438)的步骤包括使用硬掩模段(208,210,212)作为掩模,其中每个硬掩模段(208,210,212)位于位线(202,204,206)之上。 所述方法还包括在所述至少一个凹部(436,438)中形成(374)间隔物(460,462),其中所述间隔物(460,462)减少相邻位线之间的位线到位线泄漏(402,404,406)。 该方法还包括在形成(370)所述至少一个凹部(436,438)之前形成堆叠的栅极结构(114,116,118),其中每个堆叠的栅极结构(114,116,118)位于并垂直于位线(102,104,106)。
    • 6. 发明申请
    • WORD LINES IN A FLASH MEMORY ARRAY
    • WASH LINES IN FLASH MEMORY ARRAY
    • WO2006138169A1
    • 2006-12-28
    • PCT/US2006/022509
    • 2006-06-07
    • SPANSION LLCFANG, ShenqingOGAWA, HiroyukiCHANG, Kuo-TungFASTENKO, PavelMIZUTANI, KazuhiroWANG, Zhigang
    • FANG, ShenqingOGAWA, HiroyukiCHANG, Kuo-TungFASTENKO, PavelMIZUTANI, KazuhiroWANG, Zhigang
    • H01L21/8247H01L27/115H01L21/336H01L29/788
    • H01L29/7883H01L21/2652H01L27/115H01L27/11521H01L29/66825
    • Embodiments of the present invention disclose a memory device having an array [200] of flash memory cells with source contacts [280] that facilitate straight word lines [230], and a method [600] for producing the same. The array [200] is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions [250] that isolate a plurality of memory cell columns. A source column [260] is implanted with n- type dopants after the formation of a tunnel oxide layer [340] and a first polysilicon layer [330]. The implanted source column [260] is coupled to a plurality of common source lines [240] that are coupled to a plurality of source regions [350] associated with memory cells in the array [200]. A source contact [280] is coupled to the implanted source column [260] for providing electrical coupling with the plurality of source regions [350]. The source contact [280] is collinear with a row of drain contacts [275] that are coupled to drain regions [360] associated with a row of memory cells. The arrangement of source contacts [280] collinear with the row of drain contacts [275] allows for straight word line [230] formation.
    • 本发明的实施例公开了一种具有阵列[200]的存储器件,其具有促进直线字线[230]的源触点[280]的闪存单元,以及用于制造其的方法[600]。 阵列[200]由隔离多个存储单元列的多个不相交的浅沟槽隔离(STI)区域[250]组成。 在形成隧道氧化物层[340]和第一多晶硅层[330]之后,源极列[260]注入n型掺杂剂。 注入源列[260]耦合到多个公共源极线[240],其耦合到与阵列[200]中的存储器单元相关联的多个源极区域[350]。 源极触点[280]耦合到注入源极柱[260],用于提供与多个源极区域[350]的电耦合。 源极触点280与一排漏极触点[275]共线,耦合到与一行存储器单元相关联的漏极区域[360]。 与漏极触点排[275]共线的源极触点[280]的布置允许形成直线字线[230]。