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1. 发明申请

WO2005074018A1 STRUCTURE AND METHOD FOR LOW VSS RESISITANCE AND REDUCED DIBL IN A FLOATING GATE MEMORY CELL 审中-公开
标题翻译：浮动栅格存储单元中低VSS电阻和减少的数据库的结构和方法
公开(公告)号：WO2005074018A1
公开(公告)日：2005-08-11
申请号：PCT/US2004/042870
申请日：2004-12-17
申请人： SPANSION LLC , FANG, Shenqing , THURGATE, Timothy , CHANG, Kuo-Tung , FASTOW, Richard , HUI, Angela, T. , MIZUTANI, Kazuhiro , KO, Kelwin , KINOSHITA, Hiroyuki , SUN, Yu , OGAWA, Hiroyuki
发明人： FANG, Shenqing , THURGATE, Timothy , CHANG, Kuo-Tung , FASTOW, Richard , HUI, Angela, T. , MIZUTANI, Kazuhiro , KO, Kelwin , KINOSHITA, Hiroyuki , SUN, Yu , OGAWA, Hiroyuki
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/743 , H01L29/41766 , H01L29/66636
摘要： According to one exemplary embodiment, a floating gate memory cell (202) comprises a stacked gate structure (208) situated on a substrate (204) and situated over a channel region (222) in the substrate (204). The floating gate memory cell (202) further comprises a recess (228) formed in the substrate (204) adjacent to the stacked gate structure (208), where the recess (228) has a sidewall (230), a bottom (232), and a depth (236). According to this exemplary embodiment, the floating gate memory cell (202) further comprises a source (234) situated adjacent to the sidewall (230) of the recess (228) and under the stacked gate structure (208). The floating gate memory cell (202) further comprises a Vss connection region (238) situated under the bottom (232) of the recess (228) and under the source (234), where the Vss connection region (238) is connected to the source (234). The Vss connection region (238) being situated under the bottom (232) of the recess (228) causes the source (234) to have a reduced lateral diffusion in the channel region (222).
摘要翻译：根据一个示例性实施例，浮动栅极存储单元（202）包括位于衬底（204）上且位于衬底（204）中的沟道区域（222）之上的层叠栅极结构（208）。浮动栅极存储单元（202）还包括形成在与堆叠的栅极结构（208）相邻的衬底（204）中的凹部（228），其中凹部（228）具有侧壁（230），底部（232），和深度（236）。根据该示例性实施例，浮动栅极存储单元（202）还包括位于与凹部（228）的侧壁（230）相邻并位于堆叠栅极结构（208）下方的源极（234）。浮动栅极存储单元（202）还包括位于凹部（228）的底部（232）下方并且在源极（234）下方的Vss连接区域（238），其中Vss连接区域（238）连接到来源（234）。位于凹部（228）的底部（232）下面的Vss连接区域（238）使得源极（234）在沟道区域（222）中具有减小的横向扩散。

2. 发明申请

WO2006138169A1 WORD LINES IN A FLASH MEMORY ARRAY 审中-公开
标题翻译： WASH LINES IN FLASH MEMORY ARRAY
公开(公告)号：WO2006138169A1
公开(公告)日：2006-12-28
申请号：PCT/US2006/022509
申请日：2006-06-07
申请人： SPANSION LLC , FANG, Shenqing , OGAWA, Hiroyuki , CHANG, Kuo-Tung , FASTENKO, Pavel , MIZUTANI, Kazuhiro , WANG, Zhigang
发明人： FANG, Shenqing , OGAWA, Hiroyuki , CHANG, Kuo-Tung , FASTENKO, Pavel , MIZUTANI, Kazuhiro , WANG, Zhigang
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336 , H01L29/788
CPC分类号： H01L29/7883 , H01L21/2652 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： Embodiments of the present invention disclose a memory device having an array [200] of flash memory cells with source contacts [280] that facilitate straight word lines [230], and a method [600] for producing the same. The array [200] is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions [250] that isolate a plurality of memory cell columns. A source column [260] is implanted with n- type dopants after the formation of a tunnel oxide layer [340] and a first polysilicon layer [330]. The implanted source column [260] is coupled to a plurality of common source lines [240] that are coupled to a plurality of source regions [350] associated with memory cells in the array [200]. A source contact [280] is coupled to the implanted source column [260] for providing electrical coupling with the plurality of source regions [350]. The source contact [280] is collinear with a row of drain contacts [275] that are coupled to drain regions [360] associated with a row of memory cells. The arrangement of source contacts [280] collinear with the row of drain contacts [275] allows for straight word line [230] formation.
摘要翻译：本发明的实施例公开了一种具有阵列[200]的存储器件，其具有促进直线字线[230]的源触点[280]的闪存单元，以及用于制造其的方法[600]。阵列[200]由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域[250]组成。在形成隧道氧化物层[340]和第一多晶硅层[330]之后，源极列[260]注入n型掺杂剂。注入源列[260]耦合到多个公共源极线[240]，其耦合到与阵列[200]中的存储器单元相关联的多个源极区域[350]。源极触点[280]耦合到注入源极柱[260]，用于提供与多个源极区域[350]的电耦合。源极触点280与一排漏极触点[275]共线，耦合到与一行存储器单元相关联的漏极区域[360]。与漏极触点排[275]共线的源极触点[280]的布置允许形成直线字线[230]。

3. 发明申请

WO2008079775A1 A SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHODS FOR ITS FABRICATION 审中-公开
标题翻译：包含双充电储存库的半导体存储器及其制造方法
公开(公告)号：WO2008079775A1
公开(公告)日：2008-07-03
申请号：PCT/US2007/087769
申请日：2007-12-17
申请人： SPANSION LLC , LEE, Chungho , MELIK-MARTIROSIAN, Ashot , ZHENG, Wei , THURGATE, Timothy , CHANG, Chi , KINOSHITA, Hiroyuki , CHANG, Kuo-Tung , KIM, Unsoon
发明人： LEE, Chungho , MELIK-MARTIROSIAN, Ashot , ZHENG, Wei , THURGATE, Timothy , CHANG, Chi , KINOSHITA, Hiroyuki , CHANG, Kuo-Tung , KIM, Unsoon
IPC分类号： H01L29/788 , H01L29/792 , H01L27/115 , H01L21/8247 , H01L21/8246
CPC分类号： H01L29/42332 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42348 , H01L29/7887 , H01L29/7923
摘要： A dual charge storage node memory device 50 and methods for its fabrication are provided. In one embodiment a dielectric plug 70 is formed comprising a first portion 72 recessed into a semiconductor substrate and a second portion 74 extending above the substrate. A layer of semiconductor material 82 is formed overlying the second portion. A first layered structure 104 is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure 106 is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer 86 between first 84 and second 102 dielectric layers. Ions are implanted into the substrate to form a first bit line 94 and second bit line 96, and a layer of conductive material 110 is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.
摘要翻译：提供双电荷存储节点存储器件50及其制造方法。在一个实施例中，形成包括凹入半导体衬底的第一部分72和在衬底上延伸的第二部分74的电介质塞70。形成覆盖第二部分的半导体材料层82。第一层状结构104形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构106，每个层叠结构覆盖在半导体材料层上并且包括电荷存储层 86介于第一和第二绝缘层之间。将离子注入到衬底中以形成第一位线94和第二位线96，并且沉积和图案化导电材料层110以形成覆盖在电介质插塞和第一和第二分层结构上的控制门。

4. 发明申请

WO2005071749A1 EFFICIENT USE OF WAFER AREA WITH DEVICE UNDER THE PAD APPROACH 审中-公开
标题翻译：有效地利用了基于方法的装置
公开(公告)号：WO2005071749A1
公开(公告)日：2005-08-04
申请号：PCT/US2004/042879
申请日：2004-12-17
申请人： SPANSION, LLC , YANG, Nian , OGAWA, Hiroyuki , WU, Yider , CHANG, Kuo-Tung , SUN, Yu , HAMILTON, Darlene, G.
发明人： YANG, Nian , OGAWA, Hiroyuki , WU, Yider , CHANG, Kuo-Tung , SUN, Yu , HAMILTON, Darlene, G.
IPC分类号： H01L23/485
CPC分类号： H01L27/0203 , H01L24/05 , H01L24/06 , H01L2224/02166 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/14 , H01L2924/19043 , H01L2924/00014
摘要： More efficient use of silicon area is achieved by incorporating an active device (25) beneath a pad area (21) of a semiconductor structure (20). The pad area (21) includes a substrate (22) having a first metal layer (23) above it. A second metal layer (26) is below the first metal layer (23). The active device (25) resides in the substrate (22) below the second metal layer (26). A layet of dielectric layer (24) separates the first (26) and second metal layers (23). A via (27) within the dielectric layer (24) electrically couples the first (23) and second metal layers (26). A via (27) connects to the active component (25). Subsequent metal layers (424, 425, 426) can be arranged between the first (23) and second metal layers (26).
摘要翻译：通过在半导体结构（20）的焊盘区域（21）的下方并入有源器件（25）来实现硅面积的更有效的使用。焊盘区域（21）包括在其上方具有第一金属层（23）的基板（22）。第二金属层（26）位于第一金属层（23）的下方。有源器件（25）位于第二金属层（26）下面的衬底（22）中。电介质层（24）的层叠体分离第一（26）和第二金属层（23）。电介质层（24）内的通孔（27）电耦合第一（23）和第二金属层（26）。通孔（27）连接到有源部件（25）。随后的金属层（424,425,426）可以布置在第一（23）和第二金属层（26）之间。

5. 发明申请

WO2008016514A3 NAND MEMORY WITH SILICON-RICH CHARGE STORAGE LAYERS AND MANUFACTURING METHOD THEREOF USING SELF-ALIGNED SHALLOW-TRENCH ISOLATION 审中-公开
公开(公告)号：WO2008016514A3
公开(公告)日：2008-02-07
申请号：PCT/US2007/016620
申请日：2007-07-24
申请人： ADVANCED MICRO DEVICES, INC. , SPANSION LLC , JOSHI, Amol, Ramesh , SACHAR, Harpreet , SUH, Youseok , FANG, Shenqing , YANG, Chih-Yuh , SINGH, Lovejeet , SHIRAIWA, Hidehiko , CHANG, Kuo-Tung , BELL, Scott, A. , HOLBROOK, Allison , TORII, Satoshi , MATSUMOTO, David, H.
发明人： JOSHI, Amol, Ramesh , SACHAR, Harpreet , SUH, Youseok , FANG, Shenqing , YANG, Chih-Yuh , SINGH, Lovejeet , SHIRAIWA, Hidehiko , CHANG, Kuo-Tung , BELL, Scott, A. , HOLBROOK, Allison , TORII, Satoshi , MATSUMOTO, David, H.
IPC分类号： H01L21/8247 , H01L21/762 , H01L27/115 , H01L21/336
摘要： An integrated circuit memory system [100] is formed by using a self-aligned shallow-trench isolation (SASTI) that includes: providing a substrate [102]; forming a silicon rich charge storage layer [204, 804] over the substrate [102]; forming a first isolation trench [400] through the silicon rich charge storage layer [204] in a first direction [900]; and forming a second isolation trench [800] through the silicon rich charge storage layer [204, 804] in a second direction [902] the system thus formed is a NAND memory with bit lines (426, 428) and word lines (802).

6. 发明申请

WO2008140661A1 FLASH MEMORY CELL WITH A GATE HAVING A FLARING SHAPE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有具有变形形状的门的闪存单元及其制造方法
公开(公告)号：WO2008140661A1
公开(公告)日：2008-11-20
申请号：PCT/US2008/004667
申请日：2008-04-10
申请人： SPANSION LLC , DING, Meng , SUH, YouSeok , FANG, Shenqing , CHANG, Kuo-Tung
发明人： DING, Meng , SUH, YouSeok , FANG, Shenqing , CHANG, Kuo-Tung
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L23/528 , H01L27/02
CPC分类号： H01L29/788 , H01L21/28273 , H01L21/28282 , H01L21/762 , H01L21/76224 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/792
摘要： An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an actxve region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width. An electrical current (330) flows along the bitlines (310) that are covered by wordlines (320).
摘要翻译：本发明的实施例涉及一种形成存储单元的方法。该方法包括蚀刻衬底中的沟槽并用氧化物填充沟槽以形成浅沟槽隔离（STI）区域。与STI区域接触的衬底的actxve区域的一部分形成位线STI边缘。该方法还包括在衬底的有源区上方和STI区上方形成栅极结构。栅极结构具有基本上在衬底的有源区域的中心上方的第一宽度和基本上位于STI边缘的第二宽度，并且第二宽度大于第一宽度。电流（330）沿着由字线（320）覆盖的位线（310）流动。

7. 发明申请

WO2006022907A1 FLOATING GATE MEMORY CELL 审中-公开
标题翻译：浮动门存储单元
公开(公告)号：WO2006022907A1
公开(公告)日：2006-03-02
申请号：PCT/US2005/014978
申请日：2005-04-29
申请人： SPANSION LLC , FANG, Shenqing , CHANG, Kuo-Tung , FASTENKO, Pavel , WANG, Zhigang
发明人： FANG, Shenqing , CHANG, Kuo-Tung , FASTENKO, Pavel , WANG, Zhigang
IPC分类号： H01L21/336
CPC分类号： H01L29/66825
摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory cell (202) on substrate (204) comprises a step of forming (172) a spacer (230) adjacent to a source sidewall (234) of a stacked gate structure (208), where the stacked gate structure (208) is situated over a channel region (226) in substrate (204). The method further comprises forming (172) a high energy implant doped region (240) adjacent to the spacer (230) in the source region (222) of substrate (204). The method further comprises forming (174) a recess (246) in a source region (222) of the substrate (204), where the recess (246) has a sidewall (248), a bottom (250), and a depth (252), and where the sidewall (248) of the recess (246) is situated adjacent to a source (254) of the floating gate memory cell (202). According to this exemplary embodiment, the spacer (230) causes the source (254) to have a reduced lateral straggle and diffusion in the channel region (226), which causes a reduction in drain induced barrier lowering (DIBL) in the floating gate memory cell (202).
摘要翻译：根据一个示例性实施例，用于在衬底（204）上制造浮动栅极存储单元（202）的方法包括：形成（172）邻近层叠栅极结构的源极侧壁（234）的间隔物（230）的步骤 208），其中堆叠的栅极结构（208）位于衬底（204）中的沟道区（226）之上。该方法还包括在衬底（204）的源区（222）中形成（172）与衬垫（230）相邻的高能注入掺杂区（240）。该方法还包括在衬底（204）的源极区（222）中形成（174）凹部（246），其中凹部（246）具有侧壁（248），底部（250）和深度 252），并且其中凹部（246）的侧壁（248）位于与浮动栅极存储单元（202）的源极（254）相邻的位置。根据该示例性实施例，间隔物（230）使得源极（254）在沟道区域（226）中具有减小的横向分束和扩散，这导致浮动栅极存储器中的漏极引起的屏障降低（DIBL）的减小细胞（202）。

8. 发明申请

WO2008011053A1 MEMORY CELL SYSTEM WITH CHARGE TRAP 审中-公开
标题翻译：带有电荷捕获的存储单元系统
公开(公告)号：WO2008011053A1
公开(公告)日：2008-01-24
申请号：PCT/US2007/016250
申请日：2007-07-17
申请人： SPANSION LLC , ADVANCED MICRO DEVICES, INC. , DING, Meng , JOSHI, Amol, Ramesh , XUE, Lei , ORIMOTO, Takashi , CHANG, Kuo-Tung
发明人： DING, Meng , JOSHI, Amol, Ramesh , XUE, Lei , ORIMOTO, Takashi , CHANG, Kuo-Tung
IPC分类号： H01L21/28 , H01L29/51 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11563 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/513 , H01L29/792
摘要： A memory cell system (1000) is provided including forming a first insulator layer (212) over a semiconductor substrate (204), forming a charge trap layer (216) over the first insulator layer (212), forming an intermediate layer (218) over the charge trap layer (216), and forming a second insulator layer (220) with the intermediate layer (218).
摘要翻译：提供一种存储单元系统（1000），包括在半导体衬底（204）上形成第一绝缘体层（212），在第一绝缘体层（212）上形成电荷陷阱层（216），形成中间层（218）在所述电荷陷阱层（216）之上，以及与所述中间层（218）形成第二绝缘体层（220）。

9. 发明申请

WO2008077125A1 ERASING FLASH MEMORY USING ADAPTIVE DRAIN AND/OR GATE BIAS 审中-公开
标题翻译：使用自适应排水和/或门偏差擦除闪存
公开(公告)号：WO2008077125A1
公开(公告)日：2008-06-26
申请号：PCT/US2007/088206
申请日：2007-12-19
申请人： SPANSION LLP , CHANG, Kuo-Tung , ZHENG, Wei
发明人： CHANG, Kuo-Tung , ZHENG, Wei
IPC分类号： G11C16/34 , G11C29/02
CPC分类号： G11C16/16 , G11C16/04 , G11C16/3468 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50004
摘要： A hot hole erase operation as described herein can be utilized for a flash memory device having an array of m) where the drain bias voltage (500) (and/or the gate bias voltage) is dynamically adjusted in response to an erase pulse count corresponding to a preliminary erase operation (604) during which a relatively small portion of a sector is erased. The adjustment of the erase bias voltage (616) in this manner enables the rest of the sector to be erased using erase bias voltages that are better suited to the current erase characteristics of the sector (518).
摘要翻译：如本文所述的热孔擦除操作可用于具有m阵列的闪存器件，其中漏极偏置电压（500）（和/或栅极偏置电压）响应于相应的擦除脉冲计数动态地调节到初步擦除操作（604），在该擦除操作期间擦除扇区的相对小部分。以这种方式调整擦除偏置电压（616）使得扇区的其余部分能够使用更适合扇区的当前擦除特性的擦除偏置电压（518）来擦除。

10. 发明申请

WO2005027210A1 MEMORY CELL STRUCTURE HAVING NITRIDE LAYER WITH REDUCED CHARGE LOSS AND METHOD FOR FABRICATING SAME 审中-公开
标题翻译：具有减少充电损失的具有氮化物层的存储单元结构及其制造方法
公开(公告)号：WO2005027210A1
公开(公告)日：2005-03-24
申请号：PCT/US2004/028329
申请日：2004-08-31
申请人： ADVANCED MICRO DEVICES, INC , KLUTH, George, Jonathan , CLARK-PHELPS, Robert, B. , JEON, Joong, S. , ZHONG, Huicai , HALLIYAL, Arvind , RAMSBEY, Mark, T. , OGLE, Robert, Bertram, Jr. , CHANG, Kuo-Tung , LI, Wenmei
发明人： KLUTH, George, Jonathan , CLARK-PHELPS, Robert, B. , JEON, Joong, S. , ZHONG, Huicai , HALLIYAL, Arvind , RAMSBEY, Mark, T. , OGLE, Robert, Bertram, Jr. , CHANG, Kuo-Tung , LI, Wenmei
IPC分类号： H01L21/28
CPC分类号： H01L21/28282 , H01L21/28176 , H01L21/28202 , H01L29/513 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： According to one embodiment, a memory cell structure comprises a semiconductor substrate (210), a first silicon oxide layer (215) situated over the semiconductor substrate, a charge storing layer (220) situated over the first silicon oxide layer, a second silicon oxide layer (225) situated over the charge storing layer, and a gate layer (230) situated over the second silicon oxide layer. In the exemplary embodiment, the charge storing layer (220) comprises silicon nitride having reduced hydrogen content, e.g., in the range of about 0 to 0.5 atomic percent. As a result, the reduced hydrogen content reduces the charge loss in the charge storing layer (220). The reduced charge loss in the charge storing layer (220) has the benefit of reducing threshold voltage shifts, prograirnming data loss, and programming capability loss in the memory device, thereby improving memory device performance.
摘要翻译：根据一个实施例，存储单元结构包括半导体衬底（210），位于半导体衬底之上的第一氧化硅层（215），位于第一氧化硅层上方的电荷存储层（220），第二氧化硅位于电荷存储层上方的层（225）和位于第二氧化硅层上方的栅极层（230）。在示例性实施例中，电荷存储层（220）包括具有降低的氢含量的氮化硅，例如在约0至0.5原子百分比的范围内。结果，降低的氢含量降低了电荷存储层（220）中的电荷损失。电荷存储层（220）中的减少的电荷损失有利于降低存储器件中的阈值电压偏移，编程数据丢失和编程能力损失，从而提高存储器件性能。

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