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1. 发明申请

WO2009146008A1 PENETRATING IMPLANT FOR FORMING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于形成半导体器件的移植植入物
公开(公告)号：WO2009146008A1
公开(公告)日：2009-12-03
申请号：PCT/US2009/038710
申请日：2009-03-29
申请人： INTEL CORPORATION , CURELLO, Giuseppe , POST, Ian, R. , LINDERT, Nick , HAFEZ, Walid, M. , JAN, Chia-Hong , BOHR, Mark, T.
发明人： CURELLO, Giuseppe , POST, Ian, R. , LINDERT, Nick , HAFEZ, Walid, M. , JAN, Chia-Hong , BOHR, Mark, T.
IPC分类号： H01L21/265 , H01L21/336
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823425 , H01L21/823456 , H01L21/823493 , H01L29/6659 , H01L29/7833 , Y10S438/918
摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.
摘要翻译：描述了形成半导体器件的半导体器件和方法。半导体包括设置在基板上的栅极堆叠。尖端区域设置在栅极堆叠的任一侧上的衬底中。卤素区域设置在邻近尖端区域的衬底中。阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

2. 发明申请

WO2015047315A1 LOW LEAKAGE NON-PLANAR ACCESS TRANSISTOR FOR EMBEDDED DYNAMIC RANDOM ACCESS MEMEORY (EDRAM) 审中-公开
标题翻译：用于嵌入式动态随机存取存储器的低泄漏非平面访问晶体管（EDRAM）
公开(公告)号：WO2015047315A1
公开(公告)日：2015-04-02
申请号：PCT/US2013/062312
申请日：2013-09-27
申请人： INTEL CORPORATION , PARK, Joodong , BHIMARASETTI, Gopinath , RAMASWAMY, Rahul , JAN, Chia-Hong , HAFEZ, Walid, M. , YEH, Jeng-Ya, D. , TSAI, Curtis
发明人： PARK, Joodong , BHIMARASETTI, Gopinath , RAMASWAMY, Rahul , JAN, Chia-Hong , HAFEZ, Walid, M. , YEH, Jeng-Ya, D. , TSAI, Curtis
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10826 , H01L27/10808 , H01L27/10879 , H01L29/66545 , H01L29/66795 , H01L29/7854
摘要： Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors for eDRAM are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate and including a narrow fin region disposed between two wide fin regions. A gate electrode stack is disposed conformal with the narrow fin region of the semiconductor fin, the gate electrode stack including a gate electrode disposed on a gate dielectric layer. The gate dielectric layer includes a lower layer and an upper layer, the lower layer composed of an oxide of the semiconductor fin. A pair of source/drain regions is included, each of the source/drain regions disposed in a corresponding one of the wide fin regions.
摘要翻译：描述了用于嵌入式动态随机存取存储器（eDRAM）的低泄漏非平面存取晶体管和用于制造用于eDRAM的低泄漏非平面存取晶体管的方法。例如，半导体器件包括设置在衬底上方并且包括设置在两个宽鳍片区域之间的窄鳍区域的半导体鳍片。栅电极堆叠被配置为与半导体鳍片的窄鳍区域共形，栅电极堆叠包括设置在栅介质层上的栅电极。栅介质层包括下层和上层，下层由半导体鳍片的氧化物构成。包括一对源极/漏极区域，每个源极/漏极区域布置在相应的一个宽鳍片区域中。

3. 发明申请

WO2015147782A1 ANTIFUSE ELEMENT USING SPACER BREAKDOWN 审中-公开
标题翻译：防爆元件使用间隔开
公开(公告)号：WO2015147782A1
公开(公告)日：2015-10-01
申请号：PCT/US2014/031592
申请日：2014-03-24
申请人： INTEL CORPORATION , CHANG, Ting , JAN, Chia-Hong , HAFEZ, Walid, M.
发明人： CHANG, Ting , JAN, Chia-Hong , HAFEZ, Walid, M.
IPC分类号： H01L23/62 , G11C29/04
CPC分类号： H01L23/5252 , G11C11/005 , G11C17/143 , G11C17/16 , G11C17/165 , H01L23/62 , H01L27/1021 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, including both non- volatile and volatile memories. The memory circuitry employs an antifuse scheme that includes an array of IT bitcells, wherein each bitcell effectively contains one gate or transistor-like device that provides both an antifuse element and a selector device for that bitcell. In particular, the bitcell device has asymmetric trench-based source/drain contacts such that one contact forms a capacitor in conjunction with the spacer and gate metal, and the other contact forms a diode in conjunction with a doped diffusion area and the gate metal. The capacitor serves as the antifuse element of the bitcell, and can be programmed by breaking down the spacer. The diode effectively provides a Schottky junction that serves as a selector device which can eliminate program and read disturbs from bitcells sharing the same bitline/wordline.
摘要翻译：公开了用于有效实现包括非易失性和易失性存储器的可编程存储器阵列电路架构的技术和电路。存储器电路采用包括IT比特单元阵列的反熔丝方案，其中每个位单元有效地包含一个栅极或类似晶体管的器件，该器件为该位单元提供反熔丝元件和选择器器件。特别地，位单元器件具有不对称的基于沟槽的源极/漏极触点，使得一个触点与间隔物和栅极金属结合形成电容器，而另一个触点与掺杂扩散区域和栅极金属结合形成二极管。电容器用作位单元的反熔断元件，并且可以通过分隔间隔来编程。二极管有效地提供肖特基结，其作为选择器装置，其可以消除共享相同位线/字线的位单元的程序和读取干扰。

4. 发明申请

WO2015047253A1 ISOLATION WELL DOPING WITH SOLID-STATE DIFFUSION SOURCES FOR FINFET ARCHITECTURES 审中-公开
标题翻译：用于FINFET架构的固态扩散源的分离井
公开(公告)号：WO2015047253A1
公开(公告)日：2015-04-02
申请号：PCT/US2013/061732
申请日：2013-09-25
申请人： INTEL CORPORATION , HAFEZ, Walid, M. , JAN, Chia-Hong , YEH, Jeng-Ya, D. , CHANG, Hsu-Yu , DIAS, Neville , MUNASINGHE, Chanaka
发明人： HAFEZ, Walid, M. , JAN, Chia-Hong , YEH, Jeng-Ya, D. , CHANG, Hsu-Yu , DIAS, Neville , MUNASINGHE, Chanaka
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L27/0924 , H01L21/2256 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L21/823892 , H01L27/0928 , H01L29/0649 , H01L29/0847 , H01L29/1095 , H01L29/66803 , H01L29/7851
摘要： An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area. In further embodiments, the impurity source film may provide a source of dopant that renders the sub-fin region complementarily doped relative to a region of the substrate forming a P/N junction that is at least part of an isolation structure electrically isolating the active fin region from a region of the substrate.
摘要翻译：沿着非平面半导体鳍片结构的一部分形成杂质源膜。杂质源膜可以作为从源膜扩散到半导体鳍中而变得电活性的杂质源。在一个实施例中，杂质源膜被布置成邻近鳍片的有源区域和衬底之间的亚鳍片区域的一部分的侧壁表面，并且比与有源区域更靠近衬底。在另外的实施例中，杂质源膜可以提供掺杂源，其相对于形成P / N结的衬底的区域互补掺杂，所述P / N结是隔离结构的至少一部分，电绝缘活性鳍区域。

5. 发明申请

WO2010078189A3 FLASH CELL WITH INTEGRATED HIGH-K DIELECTRIC AND METAL-BASED CONTROL GATE 审中-公开
公开(公告)号：WO2010078189A3
公开(公告)日：2010-07-08
申请号：PCT/US2009/069394
申请日：2009-12-23
申请人： INTEL CORPORATION , JAN, Chia-Hong , HAFEZ, Walid, M.
发明人： JAN, Chia-Hong , HAFEZ, Walid, M.
IPC分类号： H01L27/115 , H01L21/8247 , H01L21/31
摘要： A semiconductor device is described having an integrated high-k dielectric layer and metal control gate. A method of fabricating the same is described. Embodiments of the semiconductor device include a high-k dielectric layer disposed on a floating gate. The high-k dielectric layer defines a recess. A metal control gate is formed in the recess.

6. 发明申请

WO2012082346A1 NON-VOLATILE STORAGE ELEMENT HAVING DUAL WORK-FUNCTION ELECTRODES 审中-公开
标题翻译：具有双功能电极的非易失性存储元件
公开(公告)号：WO2012082346A1
公开(公告)日：2012-06-21
申请号：PCT/US2011/062254
申请日：2011-11-28
申请人： INTEL CORPORATION , HAFEZ, Walid, M. , RAHMAN, Anisur
发明人： HAFEZ, Walid, M. , RAHMAN, Anisur
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L29/792 , G11C16/0466 , H01L21/28282 , H01L28/40 , H01L29/4234 , H01L29/513 , H01L45/00
摘要： A non-volatile storage element and a method of forming the storage element. The non-volatile storage element comprises: a first electrode including a first material having a first work function; a second electrode including a second material having a second work function higher than the first work function; a first dielectric disposed between the first electrode and the second electrode, the first dielectric having a first bandgap; a second dielectric disposed between the first dielectric and the second electrode, the second dielectric having a second bandgap wider than the first bandgap and being disposed such that a quantum well is created in the first dielectric; and a third dielectric disposed between the first electrode and the first dielectric, the third dielectric being thinner than the second dielectric and having a third bandgap wider than the first bandgap.
摘要翻译：非易失性存储元件和形成存储元件的方法。非易失性存储元件包括：第一电极，其包括具有第一功函数的第一材料; 第二电极，包括具有高于第一功函数的第二功函数的第二材料; 设置在所述第一电极和所述第二电极之间的第一电介质，所述第一电介质具有第一带隙; 设置在所述第一电介质和所述第二电极之间的第二电介质，所述第二电介质具有比所述第一带隙宽的第二带隙，并且被布置为使得在所述第一电介质中产生量子阱; 以及设置在所述第一电极和所述第一电介质之间的第三电介质，所述第三电介质比所述第二电介质薄，并且具有比所述第一带隙宽的第三带隙。

7. 发明申请

WO2014046755A1 PRECISION RESISTOR FOR NON-PLANAR SEMICONDUCTOR DEVICE ARCHITECTURE 审中-公开
标题翻译：非平面半导体器件结构精密电阻器
公开(公告)号：WO2014046755A1
公开(公告)日：2014-03-27
申请号：PCT/US2013/046395
申请日：2013-06-18
申请人： INTEL CORPORATION
发明人： YEH, Jeng-Ya, D. , VANDERVOORN, Peter, J. , HAFEZ, Walid, M. , JAN, Chia-Hong , TSAI, Curtis , PARK, Joodong
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823431 , H01L27/0629 , H01L27/0886 , H01L28/20 , H01L29/66545 , H01L29/66795
摘要： Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.
摘要翻译：描述了用于非平面半导体器件结构的精密电阻器。在第一示例中，半导体结构包括设置在基板上方的第一和第二半导体翅片。电阻器结构设置在第一半导体鳍片上方，但不在第二半导体鳍片之上。晶体管结构由第二半导体鳍形成，但不由第一半导体鳍形成。在第二示例中，半导体结构包括设置在基板上方的第一和第二半导体翅片。隔离区设置在基板之上，位于第一和第二半导体翅片之间，并且在小于第一和第二半导体翅片的高度处。电阻器结构设置在隔离区域上方，但不在第一和第二半导体鳍片之上。第一和第二晶体管结构分别由第一和第二半导体鳍形成。

8. 发明申请

WO2017171844A1 TRANSISTOR WITH THERMAL PERFORMANCE BOOST 审中-公开
标题翻译：具有热性能增强的晶体管
公开(公告)号：WO2017171844A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025602
申请日：2016-04-01
申请人： INTEL CORPORATION
发明人： LEE, Chen-Guan , HAFEZ, Walid, M. , PARK, Joodong , JAN, Chia-Hong , CHANG, Hsu-Yu
IPC分类号： H01L29/78 , H01L21/336
摘要： Techniques are disclosed for forming a transistor with enhanced thermal performance. The enhanced thermal performance can be derived from the inclusion of thermal boost material adjacent to the transistor, where the material can be selected based on the transistor type being formed. In the case of PMOS devices, the adjacent thermal boost material may have a high positive linear coefficient of thermal expansion (CTE) (e.g., greater than 5 ppm/ C at around 20 C) and thus expand as operating temperatures increase, thereby inducing compressive strain on the channel region of an adjacent transistor and increasing carrier (e.g., hole) mobility. In the case of NMOS devices, the adjacent thermal boost material may have a negative linear CTE (e.g., less than 0 ppm/ C at around 20 C) and thus contract as operating temperatures increase, thereby inducing tensile strain on the channel region of an adjacent transistor and increasing carrier (e.g., electron) mobility.
摘要翻译：公开了用于形成具有增强的热性能的晶体管的技术。增强的热性能可以通过包括与晶体管相邻的热增强材料来获得，其中材料可以基于正在形成的晶体管类型来选择。在PMOS器件的情况下，相邻的热增强材料可以具有高的正线性热膨胀系数（CTE）（例如，在20℃附近大于5ppm /℃），并且因此随着工作温度增加而膨胀，由此引起压缩在相邻晶体管的沟道区上的应变并且增加载流子（例如，空穴）迁移率。在NMOS器件的情况下，相邻的热增强材料可以具有负的线性CTE（例如，在约20℃下小于0ppm /℃），并且因此随着工作温度增加而收缩，由此在相邻的晶体管和增加的载流子（例如电子）迁移率。

9. 发明申请

WO2017111874A1 DUAL THRESHOLD VOLTAGE (VT) CHANNEL DEVICES AND THEIR METHODS OF FABRICATION 审中-公开
标题翻译：双阈值电压（VT）通道器件及其制造方法
公开(公告)号：WO2017111874A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000506
申请日：2015-12-23
申请人： INTEL CORPORATION
发明人： CHANG, Hsu-Yu , DIAS, Neville, L. , HAFEZ, Walid, M. , JAN, Chia-Hong , OLAC-VAW, Roman, W. , LEE, Chen-Guan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1054 , H01L21/26506 , H01L21/26586 , H01L29/161 , H01L29/165 , H01L29/66545 , H01L29/66636 , H01L29/66659 , H01L29/7848
摘要： Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth. The first recess is deeper than the second recess. A semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.
摘要翻译：本发明的实施例针对双阈值电压（VT）沟道器件及其制造方法。在一个示例中，半导体器件包括设置在衬底上的栅极叠层，该衬底具有第一晶格常数。源极区和漏极区形成在栅电极的相对侧上。沟道区域设置在栅极堆叠之下以及源极区域和漏极区域之间。源极区域设置在具有第一深度的第一凹陷中，漏极区域设置在具有第二深度的第二凹陷中。第一凹陷比第二凹陷更深。具有不同于第一晶格常数的第二晶格常数的半导体材料设置在第一凹槽和第二凹槽中。

10. 发明申请

WO2015099951A1 METAL FUSE BY TOPOLOGY 审中-公开
标题翻译：金属保险丝通过拓扑学
公开(公告)号：WO2015099951A1
公开(公告)日：2015-07-02
申请号：PCT/US2014/067730
申请日：2014-11-26
申请人： INTEL CORPORATION
发明人： LEE, Chen-Guan , HAFEZ, Walid, M. , JAN, Chia-Hong
IPC分类号： H01L23/60 , H01L27/04
CPC分类号： H01L23/62 , H01L21/0217 , H01L21/32055 , H01L23/5256 , H01L2224/16225 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： Embodiments of the present disclosure describe techniques and configurations for overcurrent fuses in integrated circuit (IC) devices. In one embodiment, a device layer of a die may include a first line structure with a recessed portion between opposite end portions and two second line structures positioned on opposite sides of the first line structure. An isolation material may be disposed in the gaps between the line structures and in a first recess defined by the recessed portion. The isolation material may have a recessed portion that defines a second recess in the first recess, and a fuse structure may be disposed in the second recess. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了用于集成电路（IC）装置中的过电流保险丝的技术和配置。在一个实施例中，管芯的器件层可以包括在相对端部之间具有凹陷部分的第一线结构和位于第一线结构的相对侧上的两个第二线结构。隔离材料可以设置在线结构之间的间隙中，并且可以设置在由凹部限定的第一凹部中。隔离材料可以具有限定第一凹部中的第二凹部的凹部，并且熔丝结构可以设置在第二凹部中。可以描述和/或要求保护其他实施例。

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