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1. 发明申请

WO2016204737A1 A TRANSISTOR WITH A SUBFIN LAYER 审中-公开
标题翻译：带有子层的晶体管
公开(公告)号：WO2016204737A1
公开(公告)日：2016-12-22
申请号：PCT/US2015/036087
申请日：2015-06-16
申请人： INTEL CORPORATION
发明人： RACHMADY, Willy , METZ, Matthew V. (Matt) , LE, Van H. , PILLARISETTY, Ravi , DEWEY, Gilbert , KAVALIEROS, Jack T. , AGRAWAL, Ashish
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7851 , H01L21/02639 , H01L21/76224 , H01L29/0649 , H01L29/1037 , H01L29/1054 , H01L29/66522 , H01L29/66545 , H01L29/66795 , H01L29/78 , H01L29/7848 , H01L29/785
摘要： A subfin layer is deposited in a trench in an insulating layer on the substrate. A fin is deposited on the subfin layer. The fin has a top portion and opposing sidewalls. The fin comprises a first semiconductor material. The subfin layer comprises a III-V semiconductor material.
摘要翻译：亚基层沉积在衬底上的绝缘层中的沟槽中。翅片沉积在子层上。翅片具有顶部和相对的侧壁。翅片包括第一半导体材料。亚烯烃层包括III-V族半导体材料。

2. 发明申请

WO2016200402A1 TECHNIQUES FOR FORMING TRANSISTORS ON THE SAME DIE WITH VARIED CHANNEL MATERIALS 审中-公开
标题翻译：用相同的通道材料在相同的模具上形成晶体管的技术
公开(公告)号：WO2016200402A1
公开(公告)日：2016-12-15
申请号：PCT/US2015/035564
申请日：2015-06-12
申请人： INTEL CORPORATION
发明人： GLASS, Glenn A. , MURTHY, Anand S. , KAM, Hei , GHANI, Tahir , JAMBUNATHAN, Karthik , MOHAPATRA, Chandra S.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6681 , H01L21/02532 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L21/8256 , H01L27/0924 , H01L29/0847 , H01L29/66545 , H01L29/7848
摘要： Techniques are disclosed for forming transistors on the same substrate with varied channel materials. The techniques include forming a replacement material region in the substrate, such region used to form a plurality of fins therefrom, the fins used to form transistor channel regions. In an example case, the substrate may comprise Si and the replacement materials may include Ge, SiGe, and/or at least one III-V material. The replacement material regions can have a width sufficient to ensure a substantially planar interface between the replacement material and the substrate material. Therefore, the fins formed from the replacement material regions can also have a substantially planar interface between the replacement material and the substrate material. One example benefit from being able to form replacement material channel regions with such substantially planar interfaces can include at least a 30 percent improvement in current flow at a fixed voltage.
摘要翻译：公开了用于在具有不同通道材料的同一衬底上形成晶体管的技术。这些技术包括在基板中形成替换材料区域，用于形成多个翅片的区域，用于形成晶体管沟道区域的翅片。在一个示例性情况下，衬底可以包括Si，并且替换材料可以包括Ge，SiGe和/或至少一种III-V材料。替换材料区域可以具有足以确保替换材料和衬底材料之间的基本平坦的界面的宽度。因此，由更换材料区域形成的翅片也可以在替换材料和基底材料之间具有基本平坦的界面。能够形成具有这种基本上平面的界面的替换材料通道区域的一个示例益处可以包括在固定电压下的电流流动的至少30％的改善。

3. 发明申请

WO2016148926A1 COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) TRANSISTOR AND TUNNEL FIELD-EFFECT TRANSISTOR (TFET) ON A SINGLE SUBSTRATE 审中-公开
标题翻译：单个基板上的补充金属氧化物半导体（CMOS）晶体管和隧道场效应晶体管（TFET）
公开(公告)号：WO2016148926A1
公开(公告)日：2016-09-22
申请号：PCT/US2016/020622
申请日：2016-03-03
申请人： QUALCOMM INCORPORATED
发明人： YANG, Bin , LI, Xia , YUAN, Jun
IPC分类号： H01L21/8238 , H01L29/739 , H01L27/092
CPC分类号： H01L27/088 , H01L21/823418 , H01L21/823487 , H01L21/823814 , H01L27/092 , H01L29/0847 , H01L29/165 , H01L29/66356 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66666 , H01L29/7391 , H01L29/7827 , H01L29/7848 , H01L29/7851
摘要： An apparatus includes a structure that includes a single substrate, a planar complementary metal-oxide semiconductor (CMOS) transistor formed on the single substrate, a planar tunnel field-effect transistor (TFET) formed on the single substrate, and a mobility enhancement strength layer included in the planar CMOS transistor or included in the planar TFET.
摘要翻译：一种装置包括一种结构，其包括单个衬底，形成在单个衬底上的平面互补金属氧化物半导体（CMOS）晶体管，形成在单个衬底上的平面隧道场效应晶体管（TFET）和迁移率增强强度层包括在平面CMOS晶体管中或包括在平面TFET中。

4. 发明申请

WO2016048791A1 METHOD FOR SOURCE-DRAIN JUNCTION FORMATION IN SILICON-GERMANIUM FINFET AND CORRESPONDING FINFET APPARATUS 审中-公开
标题翻译：硅锗熔体中的源极 - 漏极结形成方法及相关器件
公开(公告)号：WO2016048791A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/050694
申请日：2015-09-17
申请人： QUALCOMM INCORPORATED
发明人： MACHKAOUTSAN, Vladimir , XU, Jeffrey Junhao , SONG, Stanley Seungchul , BADAROGLU, Mustafa , YEAP, Choh Fei
IPC分类号： H01L29/78 , H01L21/336 , H01L29/10
CPC分类号： H01L29/66803 , H01L21/2254 , H01L29/1054 , H01L29/165 , H01L29/66545 , H01L29/6681 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： A portion of a bulk silicon (Si) is formed into a fin, having a fin base and, on the fin base, an in-process fin. The fin base is doped Si and the in-process fin is silicon germanium (SiGe). The in-process SiGe fin has a source region and a drain region. Boron is in-situ doped into the drain region and into the source region. Optionally, boron is in-situ doped by forming an epi-layer, having boron, on the drain region and on the source region, and drive-in annealing to diffuse boron in the source region and the drain region.
摘要翻译：体硅（Si）的一部分形成为翅片，具有翅片基底，并且在翅片基底上形成有工艺前翅片。翅片基底是掺杂Si，而工艺中的鳍是硅锗（SiGe）。处理中的SiGe鳍具有源极区和漏极区。硼原位掺杂到漏极区域并进入源极区域。任选地，硼通过在漏极区域和源极区域上形成具有硼的外延层进行原位掺杂，以及驱动退火以在源极区域和漏极区域中扩散硼。

5. 发明申请

WO2015142357A1 TECHNIQUES FOR INTEGRATION OF GE-RICH P-MOS SOURCE/DRAIN CONTACTS 审中-公开
标题翻译：整合P-MOS源/漏联系的技术
公开(公告)号：WO2015142357A1
公开(公告)日：2015-09-24
申请号：PCT/US2014/031486
申请日：2014-03-21
申请人： INTEL CORPORATION , GLASS, Glenn A. , MURTHY, Anand S. , GHANI, Tahir , PANG, Ying , MISTKAWI, Nabil, G.
发明人： GLASS, Glenn A. , MURTHY, Anand S. , GHANI, Tahir , PANG, Ying , MISTKAWI, Nabil, G.
IPC分类号： H01L29/78 , H01L21/336 , H01L29/94 , H01L21/8238
CPC分类号： H01L29/7848 , B82Y10/00 , H01L21/02532 , H01L21/30604 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0924 , H01L29/0649 , H01L29/0673 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/167 , H01L29/41783 , H01L29/42392 , H01L29/45 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66795 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm -3 .
摘要翻译：公开了用于改善锗（Ge）富集的p-MOS源极/漏极触点的集成的技术，例如降低接触电阻。这些技术包括将p型富锗层直接沉积在接触沟槽位置的硅（Si）表面上，因为Si表面有利于沉积高质量的导电富Ge材料。在一个示例性方法中，在去除先前沉积在源极/漏极位置中的牺牲硅锗（SiGe）层之后，在源/漏接触沟槽位置中的富Si层沉积在Si衬底的表面上。在另一示例性方法中，富集层沉积在接触沟槽位置中的Si包覆层上，其中Si包覆层沉积在功能性p型SiGe层上。在一些情况下，富锗层包含至少50％的Ge（并且可以含有锡（Sn）和/或Si），并且是以高于1E20cm-3的掺杂的硼（B）。

6. 发明申请

WO2015127701A1 METHOD FOR FORMING FIN FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：形成Fin场效应晶体管的方法
公开(公告)号：WO2015127701A1
公开(公告)日：2015-09-03
申请号：PCT/CN2014/073838
申请日：2014-03-21
申请人： TSINGHUA UNIVERSITY
发明人： WANG, Jing , XIAO, Lei , ZHAO, Mei , LIANG, Renrong , XU, Jun
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795 , H01L29/7848
摘要： A method for forming a FinFET is provided, comprising: providing a substrate; forming a fin structure with a material Ge or GeSi on the substrate; forming a gate stack or a dummy gate on the substrate; defining a first region and a second region in the fin structure; and implanting atoms, molecules, ions or plasmas containing an element Sn into the first region and the second region in the fin structure with the material Ge to form a strained Ge Sn layer, or implanting atoms, molecules, ions or plasmas containing an element Sn into the first region and the second region in the fin structure with the material Ge Si to form a strained Ge Sn Si layer, or co-implanting atoms, molecules, ions or plasmas containing elements Sn and Si into the first region and the second region in the fin structure with the material Ge Si to form a strained Ge Sn Si layer.
摘要翻译：提供一种形成FinFET的方法，包括：提供衬底; 在基板上形成具有Ge或GeSi的材料的翅片结构; 在基板上形成栅叠层或虚栅; 限定所述翅片结构中的第一区域和第二区域; 以及使用材料Ge将含有元素Sn的原子，分子，离子或等离子体注入第一区域和鳍结构中的第二区域以形成应变Ge Sn层，或者注入含有元素Sn的原子，分子，离子或等离子体在第一区域和鳍状结构中的第二区域与材料Ge Si形成应变Ge Sn Si层，或将含有元素Sn和Si的原子，分子，离子或等离子体共注入第一区域和第二区域在翅片结构中用材料Ge Si形成应变Ge Sn Si层。

7. 发明申请

WO2015127697A1 METHOD FOR FORMING FIN FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：形成Fin场效应晶体管的方法
公开(公告)号：WO2015127697A1
公开(公告)日：2015-09-03
申请号：PCT/CN2014/073592
申请日：2014-03-18
申请人： TSINGHUA UNIVERSITY
发明人： WANG, Jing , XIAO, Lei , ZHAO, Mei , LIANG, Renrong , XU, Jun
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/165 , H01L21/2236 , H01L21/26506 , H01L29/1054 , H01L29/161 , H01L29/66545 , H01L29/66795 , H01L29/66803 , H01L29/7848
摘要： A method for forming a fin field effect transistor is provided. The method includes: providing a substrate; forming a fin structure with a material Ge or GeSi on the substrate; implanting atoms, molecules, ions or plasmas containing an element Sn into the fin structure with the material Ge or GeSi to form a Ge-based GeSn layer or a Ge-based GeSn Si layer; and forming a gate stack on the Ge-based GeSn layer or the Ge-based GeSn Si layer, the gate stack being oriented transversely to the fin structure.
摘要翻译：提供一种形成鳍式场效应晶体管的方法。该方法包括：提供衬底; 在基板上形成具有Ge或GeSi的材料的翅片结构; 用材料Ge或GeSi将含有元素Sn的原子，分子，离子或等离子体注入翅片结构中以形成Ge基GeSn层或Ge基GeSn Si层; 并且在Ge基GeSn层或Ge基GeSn Si层上形成栅极叠层，栅叠层横向于鳍结构。

8. 发明申请

WO2015127363A1 INTEGRATED CIRCUIT DEVICES INCLUDING CONTACTS AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：包括联系人的集成电路设备及其形成方法
公开(公告)号：WO2015127363A1
公开(公告)日：2015-08-27
申请号：PCT/US2015/017111
申请日：2015-02-23
申请人： SAMSUNG ELECTRONICS, CO., LTD. , KITTL, Jorge A. , PALLE, Dharmendar Reddy , RODDER, Mark S.
发明人： KITTL, Jorge A. , PALLE, Dharmendar Reddy , RODDER, Mark S.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/41791 , H01L21/76897 , H01L23/485 , H01L27/0886 , H01L27/1211 , H01L29/45 , H01L29/7848 , H01L29/7851 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuit devices including contacts and methods of forming the same are provided. The devices may include a fin on a substrate, a gate structure on the fin and a source/drain region in the fin at a side of the gate structure. The devices may further include a contact plug covering an uppermost surface of the source/drain region and a sidewall of the gate structure. The contact plug may include an inner portion including a first material and an outer portion including a second material different from the first material. The outer portion may at least partially cover a sidewall of the inner portion, and a portion of the outer portion may be disposed between the sidewall of the gate structure and the sidewall of the inner portion.
摘要翻译：提供了包括触点的集成电路装置及其形成方法。器件可以包括衬底上的翅片，翅片上的栅极结构和栅极结构侧的鳍中的源极/漏极区域。所述装置还可以包括覆盖源极/漏极区域的最上表面和栅极结构的侧壁的接触插塞。接触插塞可以包括包括第一材料的内部部分和包括不同于第一材料的第二材料的外部部分。外部部分可以至少部分地覆盖内部部分的侧壁，并且外部部分的一部分可以设置在门结构的侧壁和内部部分的侧壁之间。

9. 发明申请

WO2015123305A1 FINFET WITH BACKGATE, WITHOUT PUNCHTHROUGH, AND WITH REDUCED FIN HEIGHT VARIATION 审中-公开
标题翻译：带背光的FINFET，无爆炸声，并具有降低的高度变化
公开(公告)号：WO2015123305A1
公开(公告)日：2015-08-20
申请号：PCT/US2015/015426
申请日：2015-02-11
申请人： QUALCOMM INCORPORATED
发明人： YANG, Bin , LI, Xia , CHIDAMBARAM, Pr , YEAP, Choh Fei
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/7855 , H01L29/0607 , H01L29/267 , H01L29/66795 , H01L29/7842 , H01L29/7848 , H01L29/7851 , H03K17/687 , H03K2017/6878 , H03K2217/0018 , H03K2217/0054
摘要： A FinFET having a backgate and a barrier layer beneath the fin channel of the FinFET, where the barrier layer has a bandgap greater than that of the backgate. The barrier layer serves as an etch stop layer under the fin channel, resulting in reduced fin channel height variation. The backgate provides improved current control. There is less punchthrough due to the higher bandgap barrier layer. The FinFET may also include deeply embedded stressors adjacent to the source/drain diffusions through the high bandgap barrier layer.
摘要翻译：在FinFET的鳍通道下方具有背栅和阻挡层的FinFET，其中阻挡层的带隙大于背栅的带隙。阻挡层在翅片通道下面用作蚀刻停止层，从而减少了翅片通道高度变化。后门提供改进的电流控制。由于较高的带隙阻挡层，穿孔较少。 FinFET还可以包括通过高带隙势垒层与源极/漏极扩散相邻的深埋入的应力源。

10. 发明申请

WO2015099692A1 TENSILE SOURCE DRAIN III-V TRANSISTORS FOR MOBILITY IMPROVED N-MOS 审中-公开
标题翻译：用于移动性改进的N-MOS的拉伸源III-V晶体管
公开(公告)号：WO2015099692A1
公开(公告)日：2015-07-02
申请号：PCT/US2013/077627
申请日：2013-12-23
申请人： INTEL CORPORATION , GLASS, Glenn A. , MURTHY, Anand , MOHAPATRA, Chandra
发明人： GLASS, Glenn A. , MURTHY, Anand , MOHAPATRA, Chandra
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/1054 , H01L29/205 , H01L29/66522 , H01L29/66795 , H01L29/66818 , H01L29/785
摘要： An n-MOS transistor device and method for forming such a device are disclosed. The n- MOS transistor device comprises a semiconductor substrate with one or more replacement active regions formed above the substrate. The replacement active regions comprise a first III-V semiconductor material. A gate structure is formed above the replacement active regions. Source/Drain (S/D) recesses are formed in the replacement active region adjacent to the gate structure. Replacement S/D regions are formed in the S/D recesses and comprise a second III-V semiconductor material having a lattice constant that is smaller than the lattice constant of the first III-V semiconductor material. The smaller lattice constant of the second III-V material induces a uniaxial-strain on the channel formed from the first III-V material. The uniaxial strain in the channel improves carrier mobility in the n-MOS device.
摘要翻译：公开了一种用于形成这种器件的n-MOS晶体管器件和方法。 n-MOS晶体管器件包括在衬底上方形成有一个或多个替换有源区的半导体衬底。替代的有源区域包括第一III-V族半导体材料。在替换有源区上方形成栅极结构。源极/漏极（S / D）凹槽形成在与栅极结构相邻的替换有源区中。替换S / D区域形成在S / D凹槽中，并且包括具有小于第一III-V半导体材料的晶格常数的晶格常数的第二III-V半导体材料。第二III-V材料的较小晶格常数在由第一III-V材料形成的沟道上引起单轴应变。通道中的单轴应变改善了n-MOS器件中的载流子迁移率。

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