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1. 发明申请

WO2018236357A1 THIN FILM TRANSISTORS HAVING RELATIVELY INCREASED WIDTH 审中-公开
公开(公告)号：WO2018236357A1
公开(公告)日：2018-12-27
申请号：PCT/US2017/038383
申请日：2017-06-20
申请人： INTEL CORPORATION , MAJHI, Prashant , DOYLE, Brian S. , SHARMA, Abhishek A. , KARPOV, Elijah V. , OGUZ, Kaan , O'BRIEN, Kevin P. , AHMED, Khaled
发明人： MAJHI, Prashant , DOYLE, Brian S. , SHARMA, Abhishek A. , KARPOV, Elijah V. , OGUZ, Kaan , O'BRIEN, Kevin P. , AHMED, Khaled
IPC分类号： H01L29/786 , H01L29/78 , H01L21/768 , H01L29/423
摘要： Thin film transistors having relatively increased width are described. In an example, an integrated circuit structure includes an insulator structure above a substrate. The insulator structure has a topography that varies along a plane parallel with a global plane of the substrate. A semiconducting oxide material is on the insulator structure. The semiconducting oxide material is conformal with the topography of the insulator structure. A gate electrode is over a first portion of the semiconducting oxide material on the insulator structure. The gate electrode has a first side opposite a second side. A first conductive contact is adjacent the first side of the gate electrode. A second conductive contact is adjacent the second side of the gate electrode.

2. 发明申请

WO2017111929A1 P-CHANNEL OXIDE SEMICONDUCTOR THIN FILM TRANSISTOR 审中-公开
标题翻译： P沟道氧化物半导体薄膜晶体管
公开(公告)号：WO2017111929A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/067233
申请日：2015-12-22
申请人： INTEL CORPORATION , AHMED, Khaled , MAJHI, Prashant
发明人： AHMED, Khaled , MAJHI, Prashant
IPC分类号： H01L21/8238
CPC分类号： H01L29/7869 , H01L27/1218 , H01L27/124 , H01L29/66969 , H01L29/78603 , H01L29/78615 , H01L29/78618
摘要： Substrates, assemblies, and techniques for enabling a p-channel oxide semiconductor. For example, some embodiments can include an oxide semiconductor, where the oxide semiconductor includes an indium gallium zinc oxide (IGZO) sulfur alloy as a semiconducting material. The semiconducting material can be included in a thin-film-transistor that includes one or more p-channels.
摘要翻译：
用于实现p沟道氧化物半导体的衬底，组件和技术。例如，一些实施例可以包括氧化物半导体，其中氧化物半导体包括作为半导体材料的铟镓锌氧化物（IGZO）硫合金。半导体材料可以包含在包括一个或多个p沟道的薄膜晶体管中。

3. 发明申请

WO2017111827A1 NANOWIRE LED PIXEL 审中-公开
公开(公告)号：WO2017111827A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000385
申请日：2015-12-26
申请人： INTEL CORPORATION , AHMED, Khaled , MAJHI, Prashant
发明人： AHMED, Khaled , MAJHI, Prashant
IPC分类号： H01L33/02 , H01L33/12 , H01L33/32 , H05B37/00 , H05B33/14
CPC分类号： H01L27/156 , H01L33/007 , H01L33/08 , H01L33/18 , H01L33/32
摘要： Substrates, assemblies, and techniques for enabling a nanowire LED pixel are disclosed herein. For example, some embodiments include growing a buffer layer on a support substrate, growing an N-type GaN layer on the buffer layer, growing a core of N-type GaN rods from the N-type GaN layer, growing an active emitting region (AER) around a portion of the N-type GaN core nanorods to create a blue AER LED, growing a AER around a portion of the N-type GaN core nanorods to create a green AER LED, and growing a AER around a portion of the N-type GaN core nanorods to create a red AER LED. This allows for the fabrication of RGB pixels on wafers monolithically (i.e., on a single wafer). The RGB pixels may then be transferred all at once, from source wafers to TFT backplanes.
摘要翻译：本文公开了用于启用纳米线LED像素的基板，组件和技术。例如，一些实施例包括在支撑衬底上生长缓冲层，在缓冲层上生长N型GaN层，从N型GaN层生长N型GaN棒的核心，生长有源发射区域（ AER）围绕N型GaN核心纳米棒的一部分形成蓝色AER LED，在N型GaN核心纳米棒的一部分周围生长AER以形成绿色AER LED，并且围绕一部分N型GaN核心纳米棒生长AER N型GaN核心纳米棒创建一个红色的AER LED。这允许单片地（即，在单个晶片上）在晶片上制造RGB像素。 RGB像素可以一次全部传输，从源晶圆到TFT背板。

4. 发明申请

WO2019066964A1 1S-1C DRAM WITH A NON-VOLATILE CBRAM ELEMENT 审中-公开
公开(公告)号：WO2019066964A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054597
申请日：2017-09-29
申请人： INTEL CORPORATION , PILLARISETTY, Ravi , SHARMA, Abhishek A. , DOYLE, Brian S. , KARPOV, Elijah V. , MAJHI, Prashant
发明人： PILLARISETTY, Ravi , SHARMA, Abhishek A. , DOYLE, Brian S. , KARPOV, Elijah V. , MAJHI, Prashant
IPC分类号： H01L27/108 , H01L27/115
摘要： One embodiment of a memory device comprises a selector and a storage capacitor in series with the selector. A further embodiment comprises a conductive bridging RAM (CBRAM) in parallel with a storage capacitor coupled between the selector and zero volts. A plurality of memory devices form a 1S-1C or a 1S-1C-CBRAM cross-point DRAM array with 4F 2 or less density.

5. 发明申请

WO2019055003A1 SELECTOR ELEMENT WITH BALLAST FOR LOW VOLTAGE BIPOLAR MEMORY DEVICES 审中-公开
公开(公告)号：WO2019055003A1
公开(公告)日：2019-03-21
申请号：PCT/US2017/051367
申请日：2017-09-13
申请人： INTEL CORPORATION , MAJHI, Prashant , PILLARISETTY, Ravi , KARPOV, Elijah V. , DOYLE, Brian S. , SHARMA, Abhishek A.
发明人： MAJHI, Prashant , PILLARISETTY, Ravi , KARPOV, Elijah V. , DOYLE, Brian S. , SHARMA, Abhishek A.
IPC分类号： H01L45/00 , H01L43/02
CPC分类号： H01L27/2409 , H01L27/224 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/1675
摘要： Embedded non-volatile memory structures having selector elements with ballast are described. In an example, a memory device includes a word line. A selector element is above the word line. The selector element includes a selector material layer and a ballast material layer different than the selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the elector element and the bipolar memory element. A bit line is above the word line.

6. 发明申请

WO2017111831A1 STACKABLE SWITCHING DEVICE 审中-公开
标题翻译：可堆叠切换装置
公开(公告)号：WO2017111831A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000389
申请日：2015-12-26
申请人： INTEL CORPORATION , KARPOV, Elijah, V. , MAJHI, Prashant , SHAH, Uday , PILLARISETTY, Ravi
发明人： KARPOV, Elijah, V. , MAJHI, Prashant , SHAH, Uday , PILLARISETTY, Ravi
IPC分类号： H01L29/78 , H01L21/336 , H01L27/02
CPC分类号： H01L27/02 , H01L27/2463 , H01L27/2481 , H01L29/76 , H01L29/78 , H01L45/08 , H01L45/1206 , H01L45/1226 , H01L45/145 , H01L45/1675
摘要： Substrates, assemblies, and techniques for enabling a stackable switching device are disclosed herein. For example, in some embodiments, a device may include a source, a drain, and a reaction layer located between the source and the drain. The source, the drain, and the reaction layer can be on top of a support substrate such as a semiconductor substrate and a contact area can modulate the resistance of the reaction layer. In an example, the contact area is a Schottky contact area and the reaction layer is a resistive switching layer.
摘要翻译：本文公开了用于启用可堆叠开关装置的基板，组件和技术。例如，在一些实施例中，器件可以包括源极，漏极和位于源极和漏极之间的反应层。源极，漏极和反应层可以位于诸如半导体衬底之类的支撑衬底的顶部，并且接触区域可以调节反应层的电阻。在一个例子中，接触面积是肖特基接触面积，反应层是电阻切换层。

7. 发明申请

WO2016105407A1 RESISTIVE MEMORY CELLS AND PRECURSORS THEREOF, METHODS OF MAKING THE SAME, AND DEVICES INCLUDING THE SAME 审中-公开
标题翻译：电阻记忆体及其前体，其制备方法和包括其的装置
公开(公告)号：WO2016105407A1
公开(公告)日：2016-06-30
申请号：PCT/US2014/072330
申请日：2014-12-24
申请人： INTEL CORPORATION , MUKHERJEE, Niloy , PILLARISETTY, Ravi , MAJHI, Prashant , SHAH, Uday , ARCH, Ryan E. , KUHN, Markus , BROCKMAN, Justin S. , LIU, Huiying , KARPOV, Elijah V. , OGUZ, Kaan , DOYLE, Brian S. , CHAU, Robert S.
发明人： MUKHERJEE, Niloy , PILLARISETTY, Ravi , MAJHI, Prashant , SHAH, Uday , ARCH, Ryan E. , KUHN, Markus , BROCKMAN, Justin S. , LIU, Huiying , KARPOV, Elijah V. , OGUZ, Kaan , DOYLE, Brian S. , CHAU, Robert S.
IPC分类号： H01L43/08 , H01L43/12
CPC分类号： H01L45/1633 , H01L45/08 , H01L45/126 , H01L45/145 , H01L45/1608 , H01L45/1616
摘要： Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.
摘要翻译：描述了电阻记忆单元，其前体，以及制造电阻式存储单元的方法。在一些实施例中，电阻性存储器单元由电阻式存储器前体形成，该电阻存储器前体包括开关层前体，其包含存在于受控分布中的多个氧空位，任选地不使用氧交换层。在这些或其他实施例中，所描述的电阻式存储器前体可以包括形成在开关层前体上的第二电极，其中第二电极包括导电但基本上不与氧反应的第二电极材料。还描述了包括电阻式存储器单元的器件。

8. 发明申请

WO2010074964A2 GROUP III-V MOSFET HAVING METAL DIFFUSION REGIONS 审中-公开
标题翻译：具有金属扩散区域的III-V族MOSFET
公开(公告)号：WO2010074964A2
公开(公告)日：2010-07-01
申请号：PCT/US2009/067182
申请日：2009-12-08
申请人： INTEL CORPORATION , MAJHI, Prashant , GOEL, Niti , KOVESHNIKOV, Sergei , TSAI, Wilman , RADOSAVLJEVIC, Marko , PILLARESITTY, Ravi , GARGINI, Paolo
发明人： MAJHI, Prashant , GOEL, Niti , KOVESHNIKOV, Sergei , TSAI, Wilman , RADOSAVLJEVIC, Marko , PILLARESITTY, Ravi , GARGINI, Paolo
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7783 , H01L29/41766 , H01L29/452 , H01L29/517 , H01L29/66462
摘要： A group III-V MOSFET includes metal source and drain regions that are in direct contact with the quantum well region. Such an apparatus comprises a substrate, a III-V quantum well layer formed on the substrate, a III-V barrier layer formed on the quantum well layer, a gate dielectric layer formed on the barrier layer, a gate electrode formed on the gate dielectric layer, a first metal sidewall liner formed adjacent to both the quantum well layer and the barrier layer, a second metal sidewall liner formed adjacent to both the quantum well layer and the barrier layer, a metal source region adjacent to the first metal sidewall liner, and a metal drain region adjacent to the second metal sidewall liner.
摘要翻译： III-V族MOSFET包括与量子阱区域直接接触的金属源极和漏极区域。这种装置包括衬底，形成在衬底上的III-V量子阱层，形成在量子阱层上的III-V阻挡层，形成在阻挡层上的栅极介电层，形成在栅极介质上的栅极邻近量子阱层和阻挡层形成的第一金属侧壁衬垫，邻近量子阱层和阻挡层形成的第二金属侧壁衬垫，与第一金属侧壁衬垫相邻的金属源极区域，以及与第二金属侧壁衬垫相邻的金属漏极区域。</ p>

9. 发明申请

WO2008118825A1 FORMING A NON-PLANAR TRANSISTOR HAVING A QUANTUM WELL CHANNEL 审中-公开
标题翻译：形成具有量子阱通道的非平面晶体管
公开(公告)号：WO2008118825A1
公开(公告)日：2008-10-02
申请号：PCT/US2008/057951
申请日：2008-03-21
申请人： INTEL CORPORATION , CHUI, Chi On , MAJHI, Prashant , TSAI, Wilman , KAVALIEROS, Jack
发明人： CHUI, Chi On , MAJHI, Prashant , TSAI, Wilman , KAVALIEROS, Jack
IPC分类号： H01L29/778 , H01L29/768 , H01L21/336
CPC分类号： H01L29/66977 , H01L29/1054 , H01L29/165 , H01L29/66431 , H01L29/66795 , H01L29/778 , H01L29/7842 , H01L29/785
摘要： In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种具有衬底，形成在衬底上的掩埋氧化物层，形成在掩埋氧化物层上的绝缘体上硅（SOI）芯体，围绕着该衬底的压应变量子阱（QW）层） SOI芯，以及围绕QW层缠绕的拉伸应变硅层。描述和要求保护其他实施例。

10. 发明申请

WO2019066774A1 THIN FILM TRANSISTORS HAVING RELATIVELY INCREASED WIDTH AND SHARED BITLINES 审中-公开
公开(公告)号：WO2019066774A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/053424
申请日：2017-09-26
申请人： INTEL CORPORATION , DOYLE, Brian S. , SHARMA, Abhishek A. , PILLARISETTY, Ravi , MAJHI, Prashant , KARPOV, Elijah V.
发明人： DOYLE, Brian S. , SHARMA, Abhishek A. , PILLARISETTY, Ravi , MAJHI, Prashant , KARPOV, Elijah V.
IPC分类号： H01L29/786 , H01L29/49
摘要： Thin film transistors having relatively increased width and shared bitlines are described. In an example, an integrated circuit structure includes a plurality of transistors formed in an insulator structure above a substrate. The plurality of transistors arranged in a column such that the respective lateral arrangement of the source, the gate, and the drain of each of the transistors aligns with an adjacent thin film transistor, wherein the plurality transistors extend vertically through the insulator structure at least two interconnect levels to provide increased relative width. A first conductive contact is formed between one of sources and drains of at least two of the plurality of transistors in the column, and the conductive contact extends through the insulator structure at least two interconnect levels.

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