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1. 发明申请

WO2012054642A1 METHOD AND APPARATUS FOR USE IN IMPROVING LINEARITY OF MOSFETS USING AN ACCUMULATED CHARGE SINK - HARMONIC WRINKLE REDUCTION 审中-公开
标题翻译：用于改善MOSFET的线性度的方法和装置使用累积充电电荷 - 谐波皱缩减少
公开(公告)号：WO2012054642A1
公开(公告)日：2012-04-26
申请号：PCT/US2011/056942
申请日：2011-10-19
申请人： PEREGRINE SEMICONDUCTOR CORPORATION , BRINDLE, Christopher N. , DENG, Jie , YANG, Chieh-Kai , GENC, Alper
发明人： BRINDLE, Christopher N. , DENG, Jie , YANG, Chieh-Kai , GENC, Alper
IPC分类号： H01L21/84 , H01L21/86 , H01L29/786 , H01L27/12
CPC分类号： H01L21/84 , H01L21/86 , H01L27/1203 , H01L29/78615 , H03K2217/0018
摘要： A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
摘要翻译：公开了一种用于提高具有累积电荷吸收（ACS）的MOSFET器件的线性灵敏度的方法和装置。该方法和装置适于解决在采用累积电荷宿的装置中在期望的工作电压范围内的二阶和三阶互调谐波失真的劣化。

2. 发明申请

WO2007133306A2 METHOD OF FORMING A BODY-TIE 审中-公开
标题翻译：形成身体的方法
公开(公告)号：WO2007133306A2
公开(公告)日：2007-11-22
申请号：PCT/US2007/002774
申请日：2007-02-01
申请人： HONEYWELL INTERNATIONAL INC. , FECHNER, Paul, S. , SHAW, Gordon, A. , VOGT, Eric, E.
发明人： FECHNER, Paul, S. , SHAW, Gordon, A. , VOGT, Eric, E.
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78615 , H01L29/66772
摘要： A method of forming a body-tie. The method includes forming the body-tie during an STI scheme of an SOI process. During the STI scheme, a first trench is formed. The first trench stops before a buried oxide layer of the SOI substrate. The first trench may determine a height of body tie. that is shared between at least two FETs. A second trench niay also be formed within the first trench. The second trench stops in the SOI substrate. The second trench defines the location and shape of a body-tie. Once the location and shape of the body-tie are defined, an oxide is deposited above the body-tie. The deposited oxide prevents certain implants from entering the body tie. By preventing these implants, a source and a drain implant may be self-aligned to the source and drain areas without requiring the use of the photoresist mask to shield the body tie regions from the source and drain implant.
摘要翻译：一种形成身体的方法。该方法包括在SOI工艺的STI方案期间形成体系。在STI方案中，形成第一沟槽。第一沟槽在SOI衬底的掩埋氧化物层之前停止。第一个沟槽可以确定身体搭接的高度。在至少两个FET之间共享。第二沟槽niay也形成在第一沟槽内。第二沟槽在SOI衬底中停止。第二个沟槽定义了一个领带的位置和形状。一旦定义了身体领带的位置和形状，就会在身体绑带上方沉积氧化物。沉积的氧化物防止某些植入物进入身体束带。通过防止这些植入物，源极和漏极注入可以与源极和漏极区域自对准，而不需要使用光致抗蚀剂掩模来屏蔽源极和漏极植入物的主体连接区域。

3. 发明申请

WO2007098305A2 METHOD AND APPARATUS FOR FORMING A SEMICONDUCTOR-ON-INSULATOR (SOI) BODY-CONTACTED DEVICE 审中-公开
标题翻译：用于形成半导体绝缘体（SOI）身体接触装置的方法和装置
公开(公告)号：WO2007098305A2
公开(公告)日：2007-08-30
申请号：PCT/US2007/060843
申请日：2007-01-22
申请人： FREESCALE SEMICONDUCTOR INC. , MATHEW, Leo , GE, Lixin , VEERARAGHAVAN, Surya
发明人： MATHEW, Leo , GE, Lixin , VEERARAGHAVAN, Surya
IPC分类号： H01L27/12
CPC分类号： H01L29/78615 , H01L29/785
摘要： A method for making a semiconductor device includes patterning a semiconductor layer (14), overlying an insulator layer (12), to create a first active region (28) and a second active region (30), wherein the first active region is of a different height from the second active region, and wherein at least a portion of the first active region has a first conductivity type and at least a portion of the second active region has a second conductivity type different from the first conductivity type in at least a channel region of the semiconductor device. The method further includes forming a gate structure (26) over at least a portion of the first active region and the second active region. The method further includes removing a portion of the second active region on one side of the semiconductor device.
摘要翻译：制造半导体器件的方法包括图案化覆盖绝缘体层（12）的半导体层（14），以形成第一有源区（28）和第二有源区（30），其中第一有源区为与第二有源区不同的高度，并且其中第一有源区的至少一部分具有第一导电类型，并且第二有源区的至少一部分具有与至少一个沟道中的第一导电类型不同的第二导电类型半导体器件的区域。该方法还包括在第一有源区域和第二有源区域的至少一部分上形成栅极结构（26）。该方法还包括去除半导体器件一侧上的第二有源区的一部分。

4. 发明申请

WO2006113395A2 PARALLEL FIELD EFFECT TRANSISTOR STRUCTURE HAVING A BODY CONTACT 审中-公开
标题翻译：具有身体接触的平行场效应晶体管结构
公开(公告)号：WO2006113395A2
公开(公告)日：2006-10-26
申请号：PCT/US2006/013987
申请日：2006-04-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , WARNOCK, James, D. , SMITH, George, E., III
发明人： WARNOCK, James, D. , SMITH, George, E., III
IPC分类号： H01L27/01
CPC分类号： H01L27/1203 , H01L27/088 , H01L29/7833 , H01L29/78615
摘要： A first or primary field effect transistor ("FET") (620) is separated from a body contact thereto by one or more second FETs (632) that are placed electrically in parallel with the first FET (620). In this way, the body of the first FET (620) can be extended into the region occupied by the second FET (632) to allow contact to be made to the body of the first FET (620). In one embodiment, the gate conductor of the first FET (620) and a gate conductor of the second FET (632) are integral parts of a unitary conductive pattern. The unitary conductive pattern is made desirably small, and can be made as small as the smallest predetermined linewidth for gate conductors on an integrated circuit which includes the body-contacted FET. In this way, area and parasitic capacitance are kept small.
摘要翻译：第一或主要场效应晶体管（“FET”）（620）通过与第一FET（620）并联放置的一个或多个第二FET（632）与其体接触分离。以这种方式，第一FET（620）的主体可以延伸到由第二FET（632）占据的区域中，以允许与第一FET（620）的主体接触。在一个实施例中，第一FET（620）的栅极导体和第二FET（632）的栅极导体是整体导电图案的整体部分。整体式导电图案理想地小，并且可以制成与包括身体接触的FET的集成电路上的栅极导体的最小预定线宽一样小。以这种方式，面积和寄生电容保持较小。

5. 发明申请

WO2005015644A1 BODY-TIED SOI TRANSISTOR AND METHOD FOR FABRICATION THEREOF 审中-公开
标题翻译：体内SOI晶体管及其制造方法
公开(公告)号：WO2005015644A1
公开(公告)日：2005-02-17
申请号：PCT/US2004/000486
申请日：2004-01-09
申请人： ADVANCED MICRO DEVICES, INC. , WU, David, Donggang , QI, Wen-Jie
发明人： WU, David, Donggang , QI, Wen-Jie
IPC分类号： H01L29/786
CPC分类号： H01L29/66492 , H01L21/26586 , H01L29/4238 , H01L29/6659 , H01L29/66772 , H01L29/78615
摘要： A method for fabricating a body-tied SOI transistor with reduced body resistance is presented. During the wafer fabrication process, a semiconductor wafer is placed in an ion implantation device and oriented to a first position relative to a beam path (31-34) of the ion implantation device in order to obtain a substantially non-orthogonal twist orientation between the beam path and the transistor gate (29) edge. Following this orientation of the first position, an ion species is implanted into a first implantation region. The wafer is then rotated to a second substantially non-orthogonal twist orientation, where another ion implantation is conducted. This process continues in the same manner, such that further substantially non-orthogonal twists and ion implantations are conducted, until the desired number of implantation areas is created. Halo or pocket implants are an example of the type of implantations to which the technique may be applied.
摘要翻译：提出了一种制造具有降低的体电阻的体结的SOI晶体管的方法。在晶片制造过程中，将半导体晶片放置在离子注入装置中并且相对于离子注入装置的光束路径（31-34）定向到第一位置，以便获得基本上非正交的扭转取向光束路径和晶体管栅极（29）边缘。在第一位置的该取向之后，将离子物质注入到第一注入区域中。然后将晶片旋转到第二基本上非正交的扭转取向，其中进行另一个离子注入。该过程以相同的方式继续，使得进一步进行基本上非正交的扭转和离子注入，直到产生所需数量的注入区域。光晕或口袋植入物是可应用该技术的植入类型的实例。

6. 发明申请

WO2004053990A1 EMULSATION OF LONG DELAY CHAIN BY RING OSCILLATOR WITH FLOATING BODY-TIED BODY TRANSISTORS 审中-公开
标题翻译：通过振荡器与浮动体身体晶体管对长延时链进行模拟
公开(公告)号：WO2004053990A1
公开(公告)日：2004-06-24
申请号：PCT/US2003/034778
申请日：2003-10-30
申请人： ADVANCED MICRO DEVICES, INC.
发明人： KLEIN, Richard, K. , PELELLA, Mario, M.
IPC分类号： H01L27/092
CPC分类号： H01L29/78615 , H03K19/0027 , H03K2005/00071 , H03K2217/0018
摘要： A method and apparatus for reducing the number of stages for measuring first and second switching speeds for PD/SOI transistors uses an inverter circuit which includes: a p-channel body-tied transistor; an n-channel body-tied transistor, coupled at their drains and gates; and a first and a second group of components tied to the bodies of the transistors. The first group restores body potentials for the transistors if the inverter circuit belongs to an event numbered stage of a ring oscillator. The second group provides body potentials for the transistors if the inverter circuit belongs to an odd numbered stage. After each transition of a waveform, the body potentials for the PD/SOI transistors are restored to the original potentials as stored in the capacitors. In this manner, a much smaller ring oscillator with fewer number of stages may be used to accurately measure the first and second switching speeds.
摘要翻译：用于减少用于测量PD / SOI晶体管的第一和第二开关速度的级数的方法和装置使用的逆变器电路包括：p沟道体结晶体管; 在其下水道和门上耦合的n沟道体结晶体管; 以及连接到晶体管的主体的第一组和第二组元件。如果逆变器电路属于环形振荡器的事件编号阶段，则第一组恢复晶体管的体电位。如果逆变器电路属于奇数级，则第二组提供晶体管的体电位。在波形的每次转换之后，PD / SOI晶体管的体电位恢复到存储在电容器中的原始电位。以这种方式，可以使用具有较少级数的更小的环形振荡器来精确地测量第一和第二切换速度。

7. 发明申请

WO1996013861A1 HIGH RESOLUTION ACTIVE MATRIX LCD CELL DESIGN 审中-公开
标题翻译：高分辨率有源矩阵LCD单元设计
公开(公告)号：WO1996013861A1
公开(公告)日：1996-05-09
申请号：PCT/US1995013688
申请日：1995-10-16
申请人： HONEYWELL INC.
发明人： HONEYWELL INC. , LIU, Michael, S. , LO, Ka-Lun , KALLURI, Sarma, R.
IPC分类号： H01L27/12
CPC分类号： H01L27/124 , H01L27/1214 , H01L27/1255 , H01L29/78615
摘要： A transistor panel used for active matrix display devices includes islands of single crystal silicon formed on a transparent quartz substrate and arranged in rows and columns, with an NMOS transistor formed in each island. Each transistor includes source, drain and channel regions and an isolated pixel reference voltage region. A silicon body tie connects the channel region to the pixel reference voltage region and acts as a current sink for unwanted carriers thereby greatly increasing the snapback voltage. A metallization extends to each transistor and is in contact with each reference voltage region to form a body tie bus. The portion of the body tie that overlaps the pixel electrode may be sized to provide a storage capacitor for improved display performance. The unique body tie design obviates the need for a separate light shield layer, provides a dramatically increased aperture ratio and is compatible with normal high temperature silicon processes.
摘要翻译：用于有源矩阵显示装置的晶体管面板包括形成在透明石英衬底上的单晶硅岛，并以行和列排列，每个岛形成NMOS晶体管。每个晶体管包括源极，漏极和沟道区域以及孤立的像素参考电压区域。硅体接头将通道区域连接到像素参考电压区域，并且用作不需要的载流子的电流吸收器，从而大大增加了回跳电压。金属化延伸到每个晶体管并且与每个参考电压区域接触以形成主体连接母线。与像素电极重叠的身体束带的部分可以被设计成提供用于改善显示性能的存储电容器。独特的身体搭配设计避免了单独的遮光层的需要，提供了显着增加的开口率，并且与普通的高温硅工艺兼容。

8. 发明申请

WO2011084975A3 A BODY-TIED ASYMMETRIC N-TYPE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：体态非对称N型场效应晶体管
公开(公告)号：WO2011084975A3
公开(公告)日：2011-12-29
申请号：PCT/US2011020173
申请日：2011-01-05
申请人： IBM , CHANG JOSEPHINE B , CHANG LELAND , LIN CHUNG-HSUN , SLEIGHT JEFFREY W
发明人： CHANG JOSEPHINE B , CHANG LELAND , LIN CHUNG-HSUN , SLEIGHT JEFFREY W
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/1083 , H01L29/42384 , H01L29/66659 , H01L29/66772 , H01L29/78615
摘要： In one exemplary embodiment of the invention, an asymmetric N-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric N-type field effect transistor is operable to act as a symmetric N-type field effect transistor.
摘要翻译：在本发明的一个示例性实施例中，非对称N型场效应晶体管包括：源极区，经由沟道耦合到漏极区; 覆盖所述通道的至少一部分的栅极结构; 至少部分地设置在所述通道中的卤素植入物，其中所述晕轮植入物设置成比所述漏极区域更靠近所述源极区域; 以及耦合到该通道的机身连接。在另一示例性实施例中，非对称N型场效应晶体管可用作对称N型场效应晶体管。

9. 发明申请

WO2007035610A2 METHOD AND APPARATUS IMPROVING GATE OXIDE RELIABILITY BY CONTROLLING ACCUMULATED CHARGE 审中-公开
标题翻译：通过控制积累电荷改善栅极氧化可靠性的方法和装置
公开(公告)号：WO2007035610A2
公开(公告)日：2007-03-29
申请号：PCT/US2006036240
申请日：2006-09-15
申请人： PEREGRINE SEMICONDUCTOR CORP , STUBER MICHAEL S , BRINDLE CHRISTOPHER N , KELLY DYLAN J , KEMERLING CLINT L , IMTHURN GEORGE P , WELSTAND ROBERT B , BURGENER MARK L , KIM TAE YOUN , DRIBINSKY ALEXANDER
发明人： STUBER MICHAEL S , BRINDLE CHRISTOPHER N , KELLY DYLAN J , KEMERLING CLINT L , IMTHURN GEORGE P , WELSTAND ROBERT B , BURGENER MARK L , KIM TAE YOUN , DRIBINSKY ALEXANDER
IPC分类号： H01L27/12
CPC分类号： H01L29/78615 , H01L27/1203 , H01L29/4908 , H01L29/78651 , H01L29/78654 , H01L29/78657 , H03K17/162
摘要： A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to- breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.
摘要翻译：公开了一种用于使用累积电荷控制（ACC）技术来改善绝缘体上半导体（SOI）金属氧化物 - 硅场效应晶体管（MOSFET）器件的栅极氧化物可靠性的方法和装置。该方法和装置适于去除，减少或以其他方式控制SOI MOSFET中的累积电荷，从而产生FET性能特性的改进。在一个实施例中，电路包括以累积电荷状态运行的MOSFET，以及用于控制可操作地耦合到SOI MOSFET的累积电荷的装置。首先确定不受控制的累积电荷对SOI MOSFET的栅极氧化物的时间依赖介电击穿（TDDB）的影响。第二次确定SOI MOSFET的栅极氧化物的受控累积电荷对TDDB的影响。 SOI MOSFET适于具有响应于第一和第二确定的选择的平均时间分解，并且使用用于可操作地耦合到SOI MOSFET的累积电荷控制的技术来操作电路。在一个实施例中，累积的电荷控制技术包括使用可操作地耦合到SOI MOSFET体的累积电荷宿。

10. 发明申请

WO2006113395A3 PARALLEL FIELD EFFECT TRANSISTOR STRUCTURE HAVING A BODY CONTACT 审中-公开
标题翻译：具有身体接触的平行场效应晶体管结构
公开(公告)号：WO2006113395A3
公开(公告)日：2007-03-08
申请号：PCT/US2006013987
申请日：2006-04-13
申请人： IBM , WARNOCK JAMES D , SMITH GEORGE E III
发明人： WARNOCK JAMES D , SMITH GEORGE E III
IPC分类号： H01L27/01
CPC分类号： H01L27/1203 , H01L27/088 , H01L29/7833 , H01L29/78615
摘要： A first or primary field effect transistor ("FET") (620) is separated from a body contact thereto by one or more second FETs (632) that are placed electrically in parallel with the first FET (620). In this way, the body of the first FET (620) can be extended into the region occupied by the second FET (632) to allow contact to be made to the body of the first FET (620). In one embodiment, the gate conductor of the first FET (620) and a gate conductor of the second FET (632) are integral parts of a unitary conductive pattern. The unitary conductive pattern is made desirably small, and can be made as small as the smallest predetermined linewidth for gate conductors on an integrated circuit which includes the body-contacted FET. In this way, area and parasitic capacitance are kept small.
摘要翻译：第一或主要场效应晶体管（“FET”）（620）通过与第一FET（620）并联放置的一个或多个第二FET（632）与其体接触分离。以这种方式，第一FET（620）的主体可以延伸到由第二FET（632）占据的区域中，以允许与第一FET（620）的主体接触。在一个实施例中，第一FET（620）的栅极导体和第二FET（632）的栅极导体是整体导电图案的整体部分。整体式导电图案理想地小，并且可以制成与包括身体接触的FET的集成电路上的栅极导体的最小预定线宽一样小。以这种方式，面积和寄生电容保持较小。

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