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1. 发明申请

WO2009137578A3 SEMICONDUCTOR DEVICES WITH NON-PUNCH-THROUGH SEMICONDUCTOR CHANNELS HAVING ENHANCED CONDUCTION AND METHODS OF MAKING 审中-公开
标题翻译：具有增强导通的非穿通半导体通道的半导体器件及其制造方法
公开(公告)号：WO2009137578A3
公开(公告)日：2010-03-04
申请号：PCT/US2009042983
申请日：2009-05-06
申请人： SEMISOUTH LAB INC , SANKIN IGOR , SHERIDAN DAVID C , MERRETT JOSEPH NEIL
发明人： SANKIN IGOR , SHERIDAN DAVID C , MERRETT JOSEPH NEIL
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/8083 , H01L29/1058 , H01L29/1608 , H01L29/7392 , H01L29/7722
摘要： Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.
摘要翻译：描述了半导体器件，其中器件中的电流被限制在整流结（例如，p-n结或金属半导体结）之间。该器件提供非穿通行为和增强的电流传导能力。器件可以是功率半导体器件，例如结型场效应晶体管（VJFET），静态感应晶体管（SIT），结型场效应晶闸管或JFET限流器。器件可以用碳化硅（SiC）等宽带隙半导体制造。根据一些实施例，该器件可以是常闭SiC垂直结型场效应晶体管。还描述了制造包括器件的器件和电路的方法。

2. 发明申请

WO2006060337A2 NORMALLY-OFF INTEGRATED JFET POWER SWITCHES IN WIDE BANDGAP SEMICONDUCTORS AND METHODS OF MAKING 审中-公开
标题翻译：宽带隙半导体中的常关集成式JFET电源开关及其制造方法
公开(公告)号：WO2006060337A2
公开(公告)日：2006-06-08
申请号：PCT/US2005/042982
申请日：2005-11-30
申请人： SEMISOUTH LABORATORIES, INC. , SANKIN, Igor , MERRETT, Joseph, N.
发明人： SANKIN, Igor , MERRETT, Joseph, N.
IPC分类号： H01L29/76
CPC分类号： H03K17/567 , H01L27/098 , H01L29/1608 , H01L29/2003 , H01L29/808 , H01L29/8083 , H01L29/8086 , H01L29/861 , H01L29/868 , H01L29/872
摘要： Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described.
摘要翻译：描述了包括常关VJFET集成功率开关的宽带隙半导体器件。功率开关可以单片或混合实现，并且可以与内置在单芯片或多芯片宽带隙功率半导体模块中的控制电路集成。该器件可用于高功率，耐高温和抗辐射的电子元件。还描述了制造这些设备的方法。

3. 发明申请

WO2006060302A2 LATERAL TRENCH FIELD-EFFECT TRANSISTORS IN WIDE BANDGAP SEMICONDUCTOR MATERIALS, METHODS OF MAKING, AND INTEGRATED CIRCUITS INCORPORATING THE TRANSISTORS 审中-公开
标题翻译：宽带激光场效应晶体管在宽带半导体材料，制造方法和集成电路中并入晶体管
公开(公告)号：WO2006060302A2
公开(公告)日：2006-06-08
申请号：PCT/US2005042871
申请日：2005-11-30
申请人： SEMISOUTH LAB INC , SANKIN IGOR , CASADY JEFFREY B , MERRETT JOSPEH N
发明人： SANKIN IGOR , CASADY JEFFREY B , MERRETT JOSPEH N
IPC分类号： H01L31/111 , H01L21/332
CPC分类号： H01L29/2003 , H01L27/098 , H01L29/1608 , H01L29/47 , H01L29/808 , H01L29/8122
摘要： A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprise source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel, drift and drain layers can be epitaxially grown. The ohmic contacts to the source, gate, and drain regions can be formed on the same side of the wafer. The devices can have different threshold voltages depending on the vertical channel width and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used for digital, analog, and monolithic microwave integrated circuits. Methods for making the transistors and integrated circuits comprising the devices are also described.
摘要翻译：描述了结型场效应晶体管。晶体管由宽带隙半导体材料制成。该器件包括源极，沟道，漂移和漏极半导体层以及p型注入或肖特基栅极区。源极，沟道，漂移和漏极层可以外延生长。到源极，栅极和漏极区域的欧姆接触可以形成在晶片的同一侧上。器件可以具有取决于垂直沟道宽度的不同阈值电压，并且可以针对相同沟道掺杂的耗尽和增强的工作模式实现。该器件可用于数字，模拟和单片微波集成电路。还描述了制造包括这些器件的晶体管和集成电路的方法。

4. 发明申请

WO2009023502A1 VERTICAL JUNCTION FIELD EFFECT TRANSISTOR WITH MESA TERMINATION AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：具有MESA终止的垂直连接场效应晶体管及其制造方法
公开(公告)号：WO2009023502A1
公开(公告)日：2009-02-19
申请号：PCT/US2008/072413
申请日：2008-08-07
申请人： SEMISOUTH LABORATORIES, INC. , SANKIN, Igor , MERRETT, Joseph, Neil
发明人： SANKIN, Igor , MERRETT, Joseph, Neil
IPC分类号： H01L29/80 , H01L29/78
CPC分类号： H01L29/868 , H01L29/1608 , H01L29/872
摘要： A vertical junction field effect transistor (VJFET) having a mesa termination and a method of making the device are described. The device includes: an n-type mesa on an n- type substrate; a plurality of raised n-type regions on the mesa comprising an upper n-type layer on a lower n-type layer; p-type regions between and adjacent the raised n-type regions and along a lower sidewall portion of the raised regions; dielectric material on the sidewalls of the raised regions, on the p-type regions and on the sidewalls of the mesa; and electrical contacts to the substrate (drain), p-type regions (gate) and the upper n-type layer (source). The device can be made in a wide-bandgap semiconductor material such as SiC. The method includes selectively etching through an n-type layer using a mask to form the raised regions and implanting p-type dopants into exposed surfaces of an underlying n-type layer using the mask.
摘要翻译：描述具有台面终止的垂直结型场效应晶体管（VJFET）和制造该器件的方法。该装置包括：n型衬底上的n型台面; 在台面上的多个凸起的n型区域，包括在下n型层上的上n型层; 在凸起的n型区域之间和相邻的凸起区域的下侧壁部分之间的p型区域; 介电材料在凸起区域的侧壁上，在p型区域和台面的侧壁上; 和与基板（漏极），p型区域（gate）和上部n型层（源极）的电接触。该器件可以制成诸如SiC的宽带隙半导体材料。该方法包括使用掩模选择性地蚀刻n型层以形成凸起区域，并使用掩模将p型掺杂剂注入到下面的n型层的暴露表面中。

5. 发明申请

WO2007130505A2 SEMICONDUCTOR DEVICE WITH SURGE CURRENT PROTECTION AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：具有浪涌电流保护的半导体器件及其制造方法
公开(公告)号：WO2007130505A2
公开(公告)日：2007-11-15
申请号：PCT/US2007010712
申请日：2007-05-01
申请人： SEMISOUTH LAB INC , SANKIN IGOR , MERRETT JOSEPH NEIL
发明人： SANKIN IGOR , MERRETT JOSEPH NEIL
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/1608 , H01L29/868
摘要： A wide bandgap semiconductor device with surge current protection and a method of making the device are described. The device comprises a low doped n-type region formed by plasma etching through the first epitaxial layer grown on a heavily doped n-type substrate and a plurality of heavily doped p-type regions formed by plasma etching through the second epitaxial layer grown on the first epitaxial layer. Ohmic contacts are formed on p-type regions and on the backside of the n-type substrate. Schottky contacts are formed on the top surface of the n-type region. At normal operating conditions, the current in the device flows through the Schottky contacts. The device, however, is capable of withstanding extremely high current densities due to conductivity modulation caused by minority carrier injection from p-type regions.
摘要翻译：描述了具有浪涌电流保护的宽带隙半导体器件和制造该器件的方法。该器件包括通过等离子体蚀刻形成的低掺杂n型区域，其通过在重掺杂n型衬底上生长的第一外延层和通过等离子体蚀刻形成的多个重掺杂p型区域形成，该区域通过在第一外延层。欧姆接触形成在p型区域和n型衬底的背面上。在n型区域的顶表面上形成肖特基接触。在正常工作条件下，器件中的电流流过肖特基触点。然而，由于由p型区域的少数载流子注入引起的导电性调制，该器件能够承受极高的电流密度。

6. 发明申请

WO2005089303A3 SELF-ALIGNED SILICON CARBIDE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：自对准硅碳化硅半导体器件
公开(公告)号：WO2005089303A3
公开(公告)日：2007-04-05
申请号：PCT/US2005008526
申请日：2005-03-14
申请人： SEMISOUTH LAB INC , SANKIN IGOR , CASADY JANNA B , MERRETT JOSEPH N
发明人： SANKIN IGOR , CASADY JANNA B , MERRETT JOSEPH N
IPC分类号： H01L29/76 , H01L29/15 , H01L29/745 , H01L31/0312
CPC分类号： H01L29/66068 , H01L29/1608 , H01L29/2003 , H01L29/42316 , H01L29/45 , H01L29/66863 , H01L29/8128
摘要： A self-aligned silicon carbide power MESFET with improved current stability and a method of making the device are described. The device, which includes raised source and drain regions separated by a gate recess, has improved current stability as a result of reduced surface trapping effects even at low gate biases. The device can be made using a self-aligned process in which a substrate comprising an n + -doped SiC layer on an n-doped SiC channel layer is etched to define raised source and drain regions (e.g., raised fingers) using a metal etch mask. The metal etch mask is then annealed to form source and drain ohmic contacts. A single- or multilayer dielectric film is then grown or deposited and anisotropically etched. A Schottky contact layer and a final metal layer are subsequently deposited using evaporation or another anisotropic deposition technique followed by an optional isotropic etch of dielectric layer or layers.
摘要翻译：描述了具有改善的电流稳定性的自对准碳化硅功率MESFET和制造该器件的方法。该器件包括由栅极凹槽分隔开的升高的源极和漏极区域，由于甚至在低栅极偏置处降低的表面捕获效应，具有改善的电流稳定性。可以使用自对准工艺来制造器件，其中在n掺杂的SiC沟道层上包括掺杂有n + n个掺杂的SiC层的衬底被蚀刻以限定凸起的源极和漏极区域（例如，凸起的手指）使用金属蚀刻掩模。然后将金属蚀刻掩模退火以形成源极和漏极欧姆接触。然后生长或沉积单层或多层介电膜并进行各向异性蚀刻。随后使用蒸发或其他各向异性沉积技术沉积肖特基接触层和最后的金属层，然后进行介电层或层的任意各向同性蚀刻。

7. 发明申请

WO2009009380A2 NORMALLY-OFF INTEGRATED JFET POWER SWITCHES IN WIDE BANDGAP SEMICONDUCTORS AND METHODS OF MAKING 审中-公开
标题翻译：宽范围半导体中的正常集成JFET功率开关及其制造方法
公开(公告)号：WO2009009380A2
公开(公告)日：2009-01-15
申请号：PCT/US2008/069043
申请日：2008-07-02
申请人： SEMISOUTH LABORATORIES, INC. , SANKIN, Igor , MERRETT, Joseph, Neil
发明人： SANKIN, Igor , MERRETT, Joseph, Neil
IPC分类号： H01L27/098 , H01L29/808 , H01L29/812 , H01L21/04 , H01L21/8232
CPC分类号： H01L29/808 , H01L27/098 , H01L29/0619 , H01L29/1608 , H01L29/2003 , H01L29/8083 , H01L29/8122 , H01L29/8124 , H01L29/861 , H01L29/868 , H01L29/872 , H03K17/08142 , H03K17/08148 , H03K17/567 , H03K17/6871 , H03K2017/6875
摘要： Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature -tolerant and radiation-resistant electronics components. Methods of making the devices are also described.
摘要翻译：描述了包括常闭VJFET集成功率开关的宽带隙半导体器件。功率开关可以单片或混合地实现，并且可以与内置在单芯片或多芯片宽带隙功率半导体模块中的控制电路集成。该器件可用于大功率，耐温耐辐射电子元件。还描述了制造装置的方法。

8. 发明申请

WO2006060337A3 NORMALLY-OFF INTEGRATED JFET POWER SWITCHES IN WIDE BANDGAP SEMICONDUCTORS AND METHODS OF MAKING 审中-公开
标题翻译：宽范围半导体中的正常集成JFET功率开关及其制造方法
公开(公告)号：WO2006060337A3
公开(公告)日：2006-09-14
申请号：PCT/US2005042982
申请日：2005-11-30
申请人： SEMISOUTH LAB INC , SANKIN IGOR , MERRETT JOSEPH N
发明人： SANKIN IGOR , MERRETT JOSEPH N
IPC分类号： H01L29/76
CPC分类号： H03K17/567 , H01L27/098 , H01L29/1608 , H01L29/2003 , H01L29/808 , H01L29/8083 , H01L29/8086 , H01L29/861 , H01L29/868 , H01L29/872
摘要： Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described.
摘要翻译：描述了包括常闭VJFET集成功率开关的宽带隙半导体器件。功率开关可以单片或混合地实现，并且可以与内置在单芯片或多芯片宽带隙功率半导体模块中的控制电路集成。该器件可用于高功率，耐温和耐辐射电子元件。还描述了制造装置的方法。

9. 发明申请

WO2012016233A1 PHOTOLUMINESCENCE MEASUREMENT TOOL AND ASSOCIATED METHOD 审中-公开
标题翻译：光电测量工具及相关方法
公开(公告)号：WO2012016233A1
公开(公告)日：2012-02-02
申请号：PCT/US2011/046087
申请日：2011-08-01
申请人： FIRST SOLAR, INC. , ALLENIC, Arnold , BACON, Douglas , BULLER, Benyamin , CHRISTIANSEN, John , MILSHTEIN, Erel , REGEV, Avner , SANKIN, Igor
发明人： ALLENIC, Arnold , BACON, Douglas , BULLER, Benyamin , CHRISTIANSEN, John , MILSHTEIN, Erel , REGEV, Avner , SANKIN, Igor
IPC分类号： G01N21/64 , G01N21/88 , G01N21/89 , G01N21/95 , H01L21/66 , H01L31/18
CPC分类号： H01L22/12 , G01N21/6489 , G01N21/9501 , G01N2021/6419 , G01N2021/6421 , G01N2021/646 , G01N2021/8411 , G01N2021/845
摘要： The invention relates to a photoluminescence measurement tool, and an associated method and measurement system for probing the electronic structure of semiconductor materials. The tool or system may be integrated into a photovoltaic module manufacturing process.
摘要翻译：本发明涉及一种光致发光测量工具，以及用于探测半导体材料的电子结构的相关方法和测量系统。工具或系统可以集成到光伏模块制造过程中。

10. 发明申请

WO2010080282A1 PHOTOVOLTAIC DEVICES INCLUDING BACK METAL CONTACTS 审中-公开
标题翻译：包括背部金属接触的光电器件
公开(公告)号：WO2010080282A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/066995
申请日：2009-12-07
申请人： FIRST SOLAR, INC. , SANKIN, Igor
发明人： SANKIN, Igor
IPC分类号： H01L31/042
CPC分类号： H01L31/022425 , H01L29/22 , H01L29/45 , H01L31/073 , Y02E10/543 , Y02P70/521
摘要： A photovoltaic cell can include a substrate having a transparent conductive oxide layer, a CdS/CdTe layer, and a back metal contact. The back metal contact can be deposited by sputtering or by chemical vapor deposition.
摘要翻译：光伏电池可以包括具有透明导电氧化物层，CdS / CdTe层和背面金属触点的衬底。背金属接触可以通过溅射或化学气相沉积沉积。

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