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1. 发明申请

WO2009009380A3 NORMALLY-OFF INTEGRATED JFET POWER SWITCHES IN WIDE BANDGAP SEMICONDUCTORS AND METHODS OF MAKING 审中-公开
标题翻译：宽带隙半导体中的常关集成式JFET电源开关及其制造方法
公开(公告)号：WO2009009380A3
公开(公告)日：2009-03-05
申请号：PCT/US2008069043
申请日：2008-07-02
申请人： SEMISOUTH LAB INC , SANKIN IGOR , MERRETT JOSEPH NEIL
发明人： SANKIN IGOR , MERRETT JOSEPH NEIL
IPC分类号： H01L27/098 , H01L21/04 , H01L21/8232 , H01L29/808 , H01L29/812
CPC分类号： H01L29/808 , H01L27/098 , H01L29/0619 , H01L29/1608 , H01L29/2003 , H01L29/8083 , H01L29/8122 , H01L29/8124 , H01L29/861 , H01L29/868 , H01L29/872 , H03K17/08142 , H03K17/08148 , H03K17/567 , H03K17/6871 , H03K2017/6875
摘要： Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature -tolerant and radiation-resistant electronics components. Methods of making the devices are also described.
摘要翻译：描述了包括常关VJFET集成功率开关的宽带隙半导体器件。功率开关可以单片或混合实现，并且可以与内置在单芯片或多芯片宽带隙功率半导体模块中的控制电路集成。该器件可用于高功率，耐高温和抗辐射的电子元件。还描述了制造这些装置的方法。

2. 发明申请

WO2013036376A3 METHODS FOR THE EPITAXIAL GROWTH OF SILICON CARBIDE 审中-公开
标题翻译：碳化硅外延生长的方法
公开(公告)号：WO2013036376A3
公开(公告)日：2013-05-02
申请号：PCT/US2012051718
申请日：2012-08-21
申请人： SEMISOUTH LAB INC , DAS HRISHIKESH , SUNKARI SWAPNA , OLDHAM TIMOTHY , CASADY JANNA B
发明人： DAS HRISHIKESH , SUNKARI SWAPNA , OLDHAM TIMOTHY , CASADY JANNA B
IPC分类号： H01L21/20 , C30B23/02 , C30B29/36
CPC分类号： C30B25/02 , C30B25/20 , C30B29/36 , H01L21/02378 , H01L21/02433 , H01L21/02447 , H01L21/02529 , H01L21/02587 , H01L21/0262 , H01L21/02658
摘要： A method for the epitaxial growth of SiC is described which includes contacting a surface of a substrate with hydrogen and HC1, subsequently increasing the temperature of the substrate to at least 1550 °C and epitaxially growing SiC on the surface of the substrate. A method for the epitaxial growth of SiC is also described which includes heating a substrate to a temperature of at least 1550 °C, contacting a surface of the substrate with a C containing gas and a Si containing gas at a C/Si ratio of 0.5-0.8 to form a SiC buffer layer and subsequently contacting the surface with a C containing gas and a Si containing gas at a C/Si ratio > 0.8 to form a SiC epitaxial layer on the SiC buffer layer. The method results in silicon carbide epitaxial layers with improved surface morphology.
摘要翻译：描述了用于SiC的外延生长的方法，其包括将衬底的表面与氢气和HCl接触，随后将衬底的温度升高至至少1550℃，并在衬底的表面上外延生长SiC。还描述了用于SiC的外延生长的方法，其包括将衬底加热到至少1550℃的温度，使衬底的表面与C / Si比为0.5的含C气体和含Si气体接触 -0.8以形成SiC缓冲层，随后使C表面与含C气体和含Si气体以C / Si比> 0.8接触，以在SiC缓冲层上形成SiC外延层。该方法产生具有改善的表面形态的碳化硅外延层。

3. 发明申请

WO2010132460A3 GATE DRIVER FOR ENHANCEMENT-MODE AND DEPLETION-MODE WIDE BANDGAP SEMICONDUCTOR JFETS 审中-公开
标题翻译：增强型和分离型宽栅双极晶体管栅极驱动器
公开(公告)号：WO2010132460A3
公开(公告)日：2011-02-24
申请号：PCT/US2010034399
申请日：2010-05-11
申请人： SEMISOUTH LAB INC , KELLEY ROBIN LYNN , REES FENTON
发明人： KELLEY ROBIN LYNN , REES FENTON
IPC分类号： H03K17/687 , H03K7/08
CPC分类号： H03K17/04123 , H03K2017/6875
摘要： A DC-coupled two-stage gate driver circuit for driving a junction field effect transistor (JFET) is provided. The JFET can be a wide bandgap junction field effect transistor (JFET) such as a SiC JFET. The driver includes a first turn-on circuit, a second turn-on circuit and a pull-down circuit. The driver is configured to accept an input pulse-width modulation (PWM) control signal and generate an output driver signal for driving the gate of the JFET.
摘要翻译：提供了用于驱动结型场效应晶体管（JFET）的直流耦合二级栅极驱动器电路。 JFET可以是诸如SiC JFET的宽带隙结场效应晶体管（JFET）。驱动器包括第一导通电路，第二导通电路和下拉电路。驱动器被配置为接受输入脉宽调制（PWM）控制信号并产生用于驱动JFET的栅极的输出驱动器信号。

4. 发明申请

WO2010129837A3 HIGH TEMPERATURE GATE DRIVERS FOR WIDE BANDGAP SEMICONDUCTOR POWER JFETS AND INTEGRATED CIRCUITS INCLUDING THE SAME 审中-公开
标题翻译：宽带栅极半导体功率栅极的高温栅极驱动器和包括它们的集成电路
公开(公告)号：WO2010129837A3
公开(公告)日：2011-02-17
申请号：PCT/US2010033982
申请日：2010-05-07
申请人： SEMISOUTH LAB INC , ROBIN KELLEY
发明人： ROBIN KELLEY
IPC分类号： H03K17/14 , H03K17/687
CPC分类号： H03K17/145 , H03K17/687 , H03K2017/6875
摘要： Gate drivers for wide bandgap (e.g., >2eV) semiconductor junction field effect transistors (JFETs) capable of operating in high ambient temperature environments are described. The wide bandgap (WBG) semiconductor devices include silicon carbide (SiC) and gallium nitride (GaN) devices. The driver can be a non-inverting gate driver which has an input, an output, a first reference line for receiving a first supply voltage, a second reference line for receiving a second supply voltage, a ground terminal, and six Junction Field-Effect Transistors (JFETs) wherein the first JFET and the second JFET form a first inverting buffer, the third JFET and the fourth JFET form a second inverting buffer, and the fifth JFET and the sixth JFET form a totem pole which can be used to drive a high temperature power SiC JFET. An inverting gate driver is also described.
摘要翻译：描述了能够在高环境温度环境中工作的宽带隙（例如> 2eV）半导体结场效应晶体管（JFET）的栅极驱动器。宽带隙（WBG）半导体器件包括碳化硅（SiC）和氮化镓（GaN）器件。驱动器可以是非反相栅极驱动器，其具有输入，输出，用于接收第一电源电压的第一参考线，用于接收第二电源电压的第二参考线，接地端子以及六接点场效应晶体管（JFET），其中第一JFET和第二JFET形成第一反相缓冲器，第三JFET和第四JFET形成第二反相缓冲器，并且第五JFET和第六JFET形成图腾柱，其可用于驱动高温功率SiC JFET。还描述了反相栅极驱动器。

5. 发明申请

WO2010148266A2 VERTICAL JUNCTION FIELD EFFECT TRANSISTORS AND DIODES HAVING GRADED DOPED REGIONS AND METHODS OF MAKING 审中-公开
标题翻译：垂直连接场效应晶体管和具有分级掺杂区域的二极体及其制备方法
公开(公告)号：WO2010148266A2
公开(公告)日：2010-12-23
申请号：PCT/US2010039106
申请日：2010-06-18
申请人： SEMISOUTH LAB INC , CHENG LIN , MAZZOLA MICHAEL
发明人： CHENG LIN , MAZZOLA MICHAEL
IPC分类号： H01L29/80 , H01L21/337 , H01L29/808
CPC分类号： H01L29/8083 , H01L29/1066 , H01L29/1608 , H01L29/36 , H01L29/6606 , H01L29/66068 , H01L29/868 , H01L29/872
摘要： Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.
摘要翻译：对半导体装置及其制造方法进行说明。器件可以是结型场效应晶体管（JFET）或二极管，例如结型势垒肖特基（JBS）二极管或PiN二极管。器件具有通过外延生长形成的渐变p型半导体层和/或区域。该方法不需要离子注入。这些器件可以由诸如碳化硅（SiC）的宽带隙半导体材料制成，并且可以用于高温和高功率应用中。

6. 发明申请

WO2010006107A3 SEMICONDUCTOR DEVICES WITH NON-PUNCH-THROUGH SEMICONDUCTOR CHANNELS HAVING ENHANCED CONDUCTION AND METHODS OF MAKING 审中-公开
标题翻译：具有非穿孔半导体通道的半导体器件具有增强的导通和制造方法
公开(公告)号：WO2010006107A3
公开(公告)日：2010-03-18
申请号：PCT/US2009050021
申请日：2009-07-09
申请人： SEMISOUTH LAB INC , SHERIDAN DAVID C , RITENOUR ANDREW
发明人： SHERIDAN DAVID C , RITENOUR ANDREW
IPC分类号： H01L29/80 , H01L21/337
CPC分类号： H01L29/1058 , H01L29/1608 , H01L29/2003 , H01L29/42316 , H01L29/475 , H01L29/7832 , H01L29/8083 , H01L29/8122
摘要： Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.
摘要翻译：描述了半导体器件，其中器件中的电流被限制在整流结（例如p-n结或金属 - 半导体结）之间。该器件提供非穿通性能和增强的电流传导能力。器件可以是诸如接地场效应晶体管（VJFET），静态感应晶体管（SIT），结场效应晶闸管或JFET限流器的功率半导体器件。这些器件可以制成宽带隙半导体，如碳化硅（SiC）。根据一些实施例，该器件可以是常关的SiC垂直结型场效应晶体管。还描述了制造包括这些装置的装置和电路的方法。

7. 发明申请

WO2006060337A3 NORMALLY-OFF INTEGRATED JFET POWER SWITCHES IN WIDE BANDGAP SEMICONDUCTORS AND METHODS OF MAKING 审中-公开
标题翻译：宽范围半导体中的正常集成JFET功率开关及其制造方法
公开(公告)号：WO2006060337A3
公开(公告)日：2006-09-14
申请号：PCT/US2005042982
申请日：2005-11-30
申请人： SEMISOUTH LAB INC , SANKIN IGOR , MERRETT JOSEPH N
发明人： SANKIN IGOR , MERRETT JOSEPH N
IPC分类号： H01L29/76
CPC分类号： H03K17/567 , H01L27/098 , H01L29/1608 , H01L29/2003 , H01L29/808 , H01L29/8083 , H01L29/8086 , H01L29/861 , H01L29/868 , H01L29/872
摘要： Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described.
摘要翻译：描述了包括常闭VJFET集成功率开关的宽带隙半导体器件。功率开关可以单片或混合地实现，并且可以与内置在单芯片或多芯片宽带隙功率半导体模块中的控制电路集成。该器件可用于高功率，耐温和耐辐射电子元件。还描述了制造装置的方法。

8. 发明申请

WO2009129049A3 METHODS OF MAKING LATERAL JUNCTION FIELD EFFECT TRANSISTORS USING SELECTIVE EPITAXIAL GROWTH 审中-公开
标题翻译：使用选择性外延生长制造横截面场效应晶体管的方法
公开(公告)号：WO2009129049A3
公开(公告)日：2010-02-18
申请号：PCT/US2009039107
申请日：2009-04-01
申请人： SEMISOUTH LAB INC , MERRETT JOSEPH NEIL , SANKIN IGOR
发明人： MERRETT JOSEPH NEIL , SANKIN IGOR
IPC分类号： H01L21/336 , H01L21/20 , H01L29/78
CPC分类号： H01L29/808 , H01L29/1608 , H01L29/66068 , H01L29/66901
摘要： Methods of making a semiconductor device such as a lateral junction field effect transistor (JFET) are described. The methods are self-aligned and involve selective epitaxial growth using a regrowth mask material to form the gate or the source/drain regions of the device. The methods can eliminate the need for ion implantation. The device can be made from a wide band-gap semiconductor material such as SiC. The regrowth mask material can be TaC. The devices can be used in harsh environments including applications involving exposure to radiation and/or high temperatures.
摘要翻译：描述制造诸如横向结型场效应晶体管（JFET）的半导体器件的方法。这些方法是自对准的，并且涉及使用再生长掩模材料选择性地外延生长以形成器件的栅极或源极/漏极区域。该方法可以消除离子注入的需要。该器件可以由诸如SiC的宽带隙半导体材料制成。再生面膜材料可以是TaC。该设备可用于恶劣环境，包括涉及辐射和/或高温的应用。

9. 发明申请

WO2007001316A9 MONOLITHIC VERTICAL JUNCTION FIELD EFFECT TRANSISTOR AND SCHOTTKY BARRIER DIODE FABRICATED FROM SILICON CARBIDE AND METHOD FOR FABRICATING THE SAME 审中-公开
公开(公告)号：WO2007001316A9
公开(公告)日：2007-05-31
申请号：PCT/US2005024189
申请日：2005-07-08
申请人： SEMISOUTH LAB INC , UNIV MISSISSIPPI , MAZZOLA MICHAEL S , MERRETT JOSEPH N
发明人： MAZZOLA MICHAEL S , MERRETT JOSEPH N
IPC分类号： H01L29/15
CPC分类号： H01L29/872 , H01L27/0641 , H01L27/0814 , H01L27/098 , H01L29/0619 , H01L29/0661 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/8083
摘要： A switching element combining a self-aligned, vertical junction field effect transistor with etched-implanted gate and an integrated antiparallel Schottky barrier diode is described. The anode of the diode is connected to the source of the transistor at the device level in order to reduce losses due to stray inductances. The SiC surface in the SBD anode region is conditioned through dry etching to achieve a low Schottky barrier height so as to reduce power losses associated with the turn on voltage of the SBD.

10. 发明申请

WO2010054073A3 VERTICAL JUNCTION FIELD EFFECT TRANSISTORS HAVING SLOPED SIDEWALLS AND METHODS OF MAKING 审中-公开
标题翻译：具有斜面的垂直连接场效应晶体管及其制造方法
公开(公告)号：WO2010054073A3
公开(公告)日：2010-07-15
申请号：PCT/US2009063391
申请日：2009-11-05
申请人： SEMISOUTH LAB INC , SHERIDAN DAVID C , RITENOUR ANDREW P
发明人： SHERIDAN DAVID C , RITENOUR ANDREW P
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/8083 , H01L21/047 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/2003 , H01L29/66068
摘要： Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of
摘要翻译：对半导体装置及其制造方法进行说明。器件可以是结型场效应晶体管（JFET）。这些装置具有向内倾斜的具有倾斜侧壁的凸起区域。侧壁可以垂直于基板表面形成5°或更大的角度。这些装置可以具有双斜面侧壁，其中侧壁的下部形成垂直方向为5°或更大的角度，并且侧壁的上部部分与垂直方向形成<5°的角度。可以使用正常（即0°）或接近正常的入射离子注入来制造器件。这些器件具有相对均匀的侧壁掺杂，并且可以在没有成角度注入的情况下制造。

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