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1. 发明申请

WO2009009380A2 NORMALLY-OFF INTEGRATED JFET POWER SWITCHES IN WIDE BANDGAP SEMICONDUCTORS AND METHODS OF MAKING 审中-公开
标题翻译：宽范围半导体中的正常集成JFET功率开关及其制造方法
公开(公告)号：WO2009009380A2
公开(公告)日：2009-01-15
申请号：PCT/US2008/069043
申请日：2008-07-02
申请人： SEMISOUTH LABORATORIES, INC. , SANKIN, Igor , MERRETT, Joseph, Neil
发明人： SANKIN, Igor , MERRETT, Joseph, Neil
IPC分类号： H01L27/098 , H01L29/808 , H01L29/812 , H01L21/04 , H01L21/8232
CPC分类号： H01L29/808 , H01L27/098 , H01L29/0619 , H01L29/1608 , H01L29/2003 , H01L29/8083 , H01L29/8122 , H01L29/8124 , H01L29/861 , H01L29/868 , H01L29/872 , H03K17/08142 , H03K17/08148 , H03K17/567 , H03K17/6871 , H03K2017/6875
摘要： Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature -tolerant and radiation-resistant electronics components. Methods of making the devices are also described.
摘要翻译：描述了包括常闭VJFET集成功率开关的宽带隙半导体器件。功率开关可以单片或混合地实现，并且可以与内置在单芯片或多芯片宽带隙功率半导体模块中的控制电路集成。该器件可用于大功率，耐温耐辐射电子元件。还描述了制造装置的方法。

2. 发明申请

WO2009129049A3 METHODS OF MAKING LATERAL JUNCTION FIELD EFFECT TRANSISTORS USING SELECTIVE EPITAXIAL GROWTH 审中-公开
标题翻译：使用选择性外延生长制造横截面场效应晶体管的方法
公开(公告)号：WO2009129049A3
公开(公告)日：2010-02-18
申请号：PCT/US2009039107
申请日：2009-04-01
申请人： SEMISOUTH LAB INC , MERRETT JOSEPH NEIL , SANKIN IGOR
发明人： MERRETT JOSEPH NEIL , SANKIN IGOR
IPC分类号： H01L21/336 , H01L21/20 , H01L29/78
CPC分类号： H01L29/808 , H01L29/1608 , H01L29/66068 , H01L29/66901
摘要： Methods of making a semiconductor device such as a lateral junction field effect transistor (JFET) are described. The methods are self-aligned and involve selective epitaxial growth using a regrowth mask material to form the gate or the source/drain regions of the device. The methods can eliminate the need for ion implantation. The device can be made from a wide band-gap semiconductor material such as SiC. The regrowth mask material can be TaC. The devices can be used in harsh environments including applications involving exposure to radiation and/or high temperatures.
摘要翻译：描述制造诸如横向结型场效应晶体管（JFET）的半导体器件的方法。这些方法是自对准的，并且涉及使用再生长掩模材料选择性地外延生长以形成器件的栅极或源极/漏极区域。该方法可以消除离子注入的需要。该器件可以由诸如SiC的宽带隙半导体材料制成。再生面膜材料可以是TaC。该设备可用于恶劣环境，包括涉及辐射和/或高温的应用。

3. 发明申请

WO2009137578A2 SEMICONDUCTOR DEVICES WITH NON-PUNCH-THROUGH SEMICONDUCTOR CHANNELS HAVING ENHANCED CONDUCTION AND METHODS OF MAKING 审中-公开
标题翻译：具有非穿孔半导体通道的半导体器件具有增强导电性和制造方法
公开(公告)号：WO2009137578A2
公开(公告)日：2009-11-12
申请号：PCT/US2009/042983
申请日：2009-05-06
申请人： SEMISOUTH LABORATORIES, INC. , SANKIN, Igor , SHERIDAN, David, C. , MERRETT, Joseph, Neil
发明人： SANKIN, Igor , SHERIDAN, David, C. , MERRETT, Joseph, Neil
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/8083 , H01L29/1058 , H01L29/1608 , H01L29/7392 , H01L29/7722
摘要： Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.
摘要翻译：描述了半导体器件，其中器件中的电流限制在整流结（例如，p-n结或金属 - 半导体结）之间。该器件提供非穿通性能和增强的电流传导能力。这些器件可以是功率半导体器件，例如接地场效应晶体管（VJFET），静态感应晶体管（SIT），结场效应晶闸管或JFET限流器。这些器件可以制成宽带隙半导体，如碳化硅（SiC）。根据一些实施例，器件可以是常关的SiC垂直结场效应晶体管。还描述了制造包括装置的装置和电路的方法。

4. 发明申请

WO2009129049A2 METHODS OF MAKING LATERAL JUNCTION FIELD EFFECT TRANSISTORS USING SELECTIVE EPITAXIAL GROWTH 审中-公开
标题翻译：使用选择性外延生长制造横截面场效应晶体管的方法
公开(公告)号：WO2009129049A2
公开(公告)日：2009-10-22
申请号：PCT/US2009/039107
申请日：2009-04-01
申请人： SEMISOUTH LABORATORIES, INC. , MERRETT, Joseph, Neil , SANKIN, Igor
发明人： MERRETT, Joseph, Neil , SANKIN, Igor
IPC分类号： H01L21/336 , H01L29/78 , H01L21/20
CPC分类号： H01L29/808 , H01L29/1608 , H01L29/66068 , H01L29/66901
摘要： Methods of making a semiconductor device such as a lateral junction field effect transistor (JFET) are described. The methods are self-aligned and involve selective epitaxial growth using a regrowth mask material to form the gate or the source/drain regions of the device. The methods can eliminate the need for ion implantation. The device can be made from a wide band-gap semiconductor material such as SiC. The regrowth mask material can be TaC. The devices can be used in harsh environments including applications involving exposure to radiation and/or high temperatures.
摘要翻译：描述制造诸如横向结型场效应晶体管（JFET）的半导体器件的方法。这些方法是自对准的，并且涉及使用再生长掩模材料选择性地外延生长以形成器件的栅极或源极/漏极区域。该方法可以消除离子注入的需要。该器件可以由诸如SiC的宽带隙半导体材料制成。再生面膜材料可以是TaC。该设备可用于恶劣环境，包括涉及辐射和/或高温的应用。

5. 发明申请

WO2009137578A3 SEMICONDUCTOR DEVICES WITH NON-PUNCH-THROUGH SEMICONDUCTOR CHANNELS HAVING ENHANCED CONDUCTION AND METHODS OF MAKING 审中-公开
标题翻译：具有增强导通的非穿通半导体通道的半导体器件及其制造方法
公开(公告)号：WO2009137578A3
公开(公告)日：2010-03-04
申请号：PCT/US2009042983
申请日：2009-05-06
申请人： SEMISOUTH LAB INC , SANKIN IGOR , SHERIDAN DAVID C , MERRETT JOSEPH NEIL
发明人： SANKIN IGOR , SHERIDAN DAVID C , MERRETT JOSEPH NEIL
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/8083 , H01L29/1058 , H01L29/1608 , H01L29/7392 , H01L29/7722
摘要： Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.
摘要翻译：描述了半导体器件，其中器件中的电流被限制在整流结（例如，p-n结或金属半导体结）之间。该器件提供非穿通行为和增强的电流传导能力。器件可以是功率半导体器件，例如结型场效应晶体管（VJFET），静态感应晶体管（SIT），结型场效应晶闸管或JFET限流器。器件可以用碳化硅（SiC）等宽带隙半导体制造。根据一些实施例，该器件可以是常闭SiC垂直结型场效应晶体管。还描述了制造包括器件的器件和电路的方法。

6. 发明申请

WO2009023502A1 VERTICAL JUNCTION FIELD EFFECT TRANSISTOR WITH MESA TERMINATION AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：具有MESA终止的垂直连接场效应晶体管及其制造方法
公开(公告)号：WO2009023502A1
公开(公告)日：2009-02-19
申请号：PCT/US2008/072413
申请日：2008-08-07
申请人： SEMISOUTH LABORATORIES, INC. , SANKIN, Igor , MERRETT, Joseph, Neil
发明人： SANKIN, Igor , MERRETT, Joseph, Neil
IPC分类号： H01L29/80 , H01L29/78
CPC分类号： H01L29/868 , H01L29/1608 , H01L29/872
摘要： A vertical junction field effect transistor (VJFET) having a mesa termination and a method of making the device are described. The device includes: an n-type mesa on an n- type substrate; a plurality of raised n-type regions on the mesa comprising an upper n-type layer on a lower n-type layer; p-type regions between and adjacent the raised n-type regions and along a lower sidewall portion of the raised regions; dielectric material on the sidewalls of the raised regions, on the p-type regions and on the sidewalls of the mesa; and electrical contacts to the substrate (drain), p-type regions (gate) and the upper n-type layer (source). The device can be made in a wide-bandgap semiconductor material such as SiC. The method includes selectively etching through an n-type layer using a mask to form the raised regions and implanting p-type dopants into exposed surfaces of an underlying n-type layer using the mask.
摘要翻译：描述具有台面终止的垂直结型场效应晶体管（VJFET）和制造该器件的方法。该装置包括：n型衬底上的n型台面; 在台面上的多个凸起的n型区域，包括在下n型层上的上n型层; 在凸起的n型区域之间和相邻的凸起区域的下侧壁部分之间的p型区域; 介电材料在凸起区域的侧壁上，在p型区域和台面的侧壁上; 和与基板（漏极），p型区域（gate）和上部n型层（源极）的电接触。该器件可以制成诸如SiC的宽带隙半导体材料。该方法包括使用掩模选择性地蚀刻n型层以形成凸起区域，并使用掩模将p型掺杂剂注入到下面的n型层的暴露表面中。

7. 发明申请

WO2007130505A2 SEMICONDUCTOR DEVICE WITH SURGE CURRENT PROTECTION AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：具有浪涌电流保护的半导体器件及其制造方法
公开(公告)号：WO2007130505A2
公开(公告)日：2007-11-15
申请号：PCT/US2007010712
申请日：2007-05-01
申请人： SEMISOUTH LAB INC , SANKIN IGOR , MERRETT JOSEPH NEIL
发明人： SANKIN IGOR , MERRETT JOSEPH NEIL
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/1608 , H01L29/868
摘要： A wide bandgap semiconductor device with surge current protection and a method of making the device are described. The device comprises a low doped n-type region formed by plasma etching through the first epitaxial layer grown on a heavily doped n-type substrate and a plurality of heavily doped p-type regions formed by plasma etching through the second epitaxial layer grown on the first epitaxial layer. Ohmic contacts are formed on p-type regions and on the backside of the n-type substrate. Schottky contacts are formed on the top surface of the n-type region. At normal operating conditions, the current in the device flows through the Schottky contacts. The device, however, is capable of withstanding extremely high current densities due to conductivity modulation caused by minority carrier injection from p-type regions.
摘要翻译：描述了具有浪涌电流保护的宽带隙半导体器件和制造该器件的方法。该器件包括通过等离子体蚀刻形成的低掺杂n型区域，其通过在重掺杂n型衬底上生长的第一外延层和通过等离子体蚀刻形成的多个重掺杂p型区域形成，该区域通过在第一外延层。欧姆接触形成在p型区域和n型衬底的背面上。在n型区域的顶表面上形成肖特基接触。在正常工作条件下，器件中的电流流过肖特基触点。然而，由于由p型区域的少数载流子注入引起的导电性调制，该器件能够承受极高的电流密度。

8. 发明申请

WO2009009380A3 NORMALLY-OFF INTEGRATED JFET POWER SWITCHES IN WIDE BANDGAP SEMICONDUCTORS AND METHODS OF MAKING 审中-公开
标题翻译：宽带隙半导体中的常关集成式JFET电源开关及其制造方法
公开(公告)号：WO2009009380A3
公开(公告)日：2009-03-05
申请号：PCT/US2008069043
申请日：2008-07-02
申请人： SEMISOUTH LAB INC , SANKIN IGOR , MERRETT JOSEPH NEIL
发明人： SANKIN IGOR , MERRETT JOSEPH NEIL
IPC分类号： H01L27/098 , H01L21/04 , H01L21/8232 , H01L29/808 , H01L29/812
CPC分类号： H01L29/808 , H01L27/098 , H01L29/0619 , H01L29/1608 , H01L29/2003 , H01L29/8083 , H01L29/8122 , H01L29/8124 , H01L29/861 , H01L29/868 , H01L29/872 , H03K17/08142 , H03K17/08148 , H03K17/567 , H03K17/6871 , H03K2017/6875
摘要： Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature -tolerant and radiation-resistant electronics components. Methods of making the devices are also described.
摘要翻译：描述了包括常关VJFET集成功率开关的宽带隙半导体器件。功率开关可以单片或混合实现，并且可以与内置在单芯片或多芯片宽带隙功率半导体模块中的控制电路集成。该器件可用于高功率，耐高温和抗辐射的电子元件。还描述了制造这些装置的方法。

9. 发明申请

WO2007130505A3 SEMICONDUCTOR DEVICE WITH SURGE CURRENT PROTECTION AND METHOD OF MAKING THE SAME 审中-公开
公开(公告)号：WO2007130505A3
公开(公告)日：2007-11-15
申请号：PCT/US2007/010712
申请日：2007-05-01
申请人： SEMISOUTH LABORATORIES, INC. , SANKIN, Igor , MERRETT, Joseph, Neil
发明人： SANKIN, Igor , MERRETT, Joseph, Neil
IPC分类号： H01L29/872 , H01L29/868
摘要： A wide bandgap semiconductor device with surge current protection and a method of making the device are described. The device comprises a low doped n-type region formed by plasma etching through the first epitaxial layer grown on a heavily doped n-type substrate and a plurality of heavily doped p-type regions formed by plasma etching through the second epitaxial layer grown on the first epitaxial layer. Ohmic contacts are formed on p-type regions and on the backside of the n-type substrate. Schottky contacts are formed on the top surface of the n-type region. At normal operating conditions, the current in the device flows through the Schottky contacts. The device, however, is capable of withstanding extremely high current densities due to conductivity modulation caused by minority carrier injection from p-type regions.

10. 发明申请

WO2007067458A1 SELF-ALIGNED TRENCH FIELD EFFECT TRANSISTORS WITH REGROWN GATES AND BIPOLAR JUNCTION TRANSISTORS WITH REGROWN BASE CONTACT REGIONS AND METHODS OF MAKING 审中-公开
标题翻译：具有复位栅的自对准TRENCH场效应晶体管和带有基极接触区的双极晶体管晶体管和制造方法
公开(公告)号：WO2007067458A1
公开(公告)日：2007-06-14
申请号：PCT/US2006/046180
申请日：2006-12-04
申请人： SEMISOUTH LABORATORIES, INC. , MERRETT, Joseph, Neil , SANKIN, Igor
发明人： MERRETT, Joseph, Neil , SANKIN, Igor
IPC分类号： H01L21/04 , H01L29/737 , H01L29/808
CPC分类号： H01L29/66068 , H01L29/732 , H01L29/808
摘要： Junction field-effect transistors with vertical channels and self-aligned regrown gates and methods of making these devices are described. The methods use techniques to selectively grow and/or selectively remove semiconductor material to form a p-n junction gate along the sides of the channel and on the bottom of trenches separating source fingers. Methods of making bipolar junction transistors with self- aligned regrown base contact regions and methods of making these devices are also described. The semiconductor devices can be made in silicon carbide.
摘要翻译：描述了具有垂直沟道和自对准再生栅的结型场效应晶体管和制造这些器件的方法。所述方法使用技术来选择性地生长和/或选择性地去除半导体材料，以沿着沟道的侧面和分离源极指的沟槽的底部形成p-n结栅极。还描述了制造具有自对准重新生长的基极接触区域的双极结型晶体管的方法和制造这些器件的方法。半导体器件可以制成碳化硅。

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