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1. 发明申请

WO2011146579A8 ELECTRICAL CONNECTOR BETWEEN DIE PAD AND Z-INTERCONNECT FOR STACKED DIE ASSEMBLIES 审中-公开
标题翻译：堆叠式模具组件的模垫和Z型互连之间的电连接器
公开(公告)号：WO2011146579A8
公开(公告)日：2012-12-20
申请号：PCT/US2011036941
申请日：2011-05-18
申请人： INVENSAS CORP , CO REYNALDO , LEAL JEFFREY S , PANGRLE SUZETTE K , MCGRATH SCOTT , MELCHER DEANN EILEEN , BARRIE KEITH L , VILLAVICENCIO GRANT , DEL ROSARIO ELMER M , BRAY JOHN R
发明人： CO REYNALDO , LEAL JEFFREY S , PANGRLE SUZETTE K , MCGRATH SCOTT , MELCHER DEANN EILEEN , BARRIE KEITH L , VILLAVICENCIO GRANT , DEL ROSARIO ELMER M , BRAY JOHN R
IPC分类号： H01L23/12 , H01L23/48
CPC分类号： H01L25/0657 , H01L21/6836 , H01L21/78 , H01L23/3171 , H01L23/3185 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/18 , H01L24/24 , H01L24/82 , H01L25/50 , H01L2221/68327 , H01L2221/68336 , H01L2224/02371 , H01L2224/03002 , H01L2224/03318 , H01L2224/0332 , H01L2224/03632 , H01L2224/03848 , H01L2224/05016 , H01L2224/05017 , H01L2224/0529 , H01L2224/05553 , H01L2224/24051 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/76155 , H01L2224/82102 , H01L2224/94 , H01L2225/06551 , H01L2225/06562 , H01L2225/06568 , H01L2924/01327 , H01L2924/14 , H01L2924/00 , H01L2224/03
摘要： Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.
摘要翻译：用于在晶片级处理中在管芯焊盘上形成连接器的方法包括在管芯焊盘上方形成可固化导电材料的斑点并且延伸至互连芯片边缘或在互连芯片边缘之上延伸; 固化导电材料; 并在此后的晶圆切割过程中切断斑点。而且，管芯焊盘用于z互连由这些方法形成的连接器，并且相应地被成形和确定尺寸。而且，根据所述方法制备的堆叠的管芯组件和堆叠的管芯封装包含管芯，并且具有管芯焊盘以z互连由所述方法形成的连接器，并且相应地成形和确定尺寸。

2. 发明申请

WO2011146579A3 ELECTRICAL CONNECTOR BETWEEN DIE PAD AND Z-INTERCONNECT FOR STACKED DIE ASSEMBLIES 审中-公开
标题翻译：用于堆叠式电池组件的电路板和Z型互连器之间的电连接器
公开(公告)号：WO2011146579A3
公开(公告)日：2012-02-23
申请号：PCT/US2011036941
申请日：2011-05-18
申请人： VERTICAL CIRCUITS INC , CO REYNALDO , LEAL JEFFREY S , PANGRLE SUZETTE K , MCGRATH SCOTT , MELCHER DEANN EILEEN , BARRIE KEITH L , VILLLAVICENCIO GRANT , DEL ROSARIO ELMER M , BRAY JOHN R
发明人： CO REYNALDO , LEAL JEFFREY S , PANGRLE SUZETTE K , MCGRATH SCOTT , MELCHER DEANN EILEEN , BARRIE KEITH L , VILLLAVICENCIO GRANT , DEL ROSARIO ELMER M , BRAY JOHN R
IPC分类号： H01L23/12 , H01L23/48
CPC分类号： H01L25/0657 , H01L21/6836 , H01L21/78 , H01L23/3171 , H01L23/3185 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/18 , H01L24/24 , H01L24/82 , H01L25/50 , H01L2221/68327 , H01L2221/68336 , H01L2224/02371 , H01L2224/03002 , H01L2224/03318 , H01L2224/0332 , H01L2224/03632 , H01L2224/03848 , H01L2224/05016 , H01L2224/05017 , H01L2224/0529 , H01L2224/05553 , H01L2224/24051 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/76155 , H01L2224/82102 , H01L2224/94 , H01L2225/06551 , H01L2225/06562 , H01L2225/06568 , H01L2924/01327 , H01L2924/14 , H01L2924/00 , H01L2224/03
摘要： Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.
摘要翻译：在晶片级处理中在芯片焊盘上形成连接器的方法包括在芯片焊盘上形成可固化的导电材料的点并且延伸到互连芯片边缘上或之上; 固化导电材料; 并且在切割步骤之后切断斑点。而且，通过这些方法形成的管芯焊盘到z-互连连接器，并相应地成形和尺寸。而且，堆叠的模具组件和包含根据方法制备的模具的堆叠模具组件，并且具有通过所述方法形成并且形状和尺寸的模具垫到z互连连接器。

3. 发明申请

WO2008157722A1 WAFER LEVEL SURFACE PASSIVATION OF STACKABLE INTEGRATED CIRCUIT CHIPS 审中-公开
标题翻译：可堆叠集成电路板的水平面钝化
公开(公告)号：WO2008157722A1
公开(公告)日：2008-12-24
申请号：PCT/US2008/067541
申请日：2008-06-19
申请人： VERTICAL CIRCUITS, INC. , MCELREA, Simon, J.s. , CASKEY, Terrence , MCGRATH, Scott , MELCHER, Deann, Eileen , CO, Reynaldo , ANDREWS, Lawrence, Douglas , PAN, Weiping , VILLAVICENCIO, Grant , DU, Yong , CRANE, Scott, Jay , LIU, Zongrong
发明人： MCELREA, Simon, J.s. , CASKEY, Terrence , MCGRATH, Scott , MELCHER, Deann, Eileen , CO, Reynaldo , ANDREWS, Lawrence, Douglas , PAN, Weiping , VILLAVICENCIO, Grant , DU, Yong , CRANE, Scott, Jay , LIU, Zongrong
IPC分类号： H01L21/76 , H01L21/78 , H01L23/02
CPC分类号： H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/3185 , H01L24/81 , H01L24/83 , H01L2221/68327 , H01L2221/6834 , H01L2221/68359 , H01L2221/68377 , H01L2224/2919 , H01L2224/81801 , H01L2224/83851 , H01L2924/14 , H01L2924/1461 , H01L2924/0665 , H01L2924/00014 , H01L2924/00
摘要： An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).
摘要翻译：在晶片处理期间，电绝缘保形涂层至少施加到管芯的活性（前）侧和一个或多个侧壁。此外，模具具有至少施加到活性（前）侧和侧壁的电绝缘保形涂层。此外，组件包括这样的模具的堆叠，电互连的模 - 芯; 并且组件包括这样的管芯或这种管芯的堆叠，电连接到下面的电路（例如在衬底或电路板中）。

4. 发明申请

WO2009155247A2 SEMICONDUCTOR DIE SEPARATION METHOD 审中-公开
标题翻译：半导体分离方法
公开(公告)号：WO2009155247A2
公开(公告)日：2009-12-23
申请号：PCT/US2009/047389
申请日：2009-06-15
申请人： VERTICAL CIRCUITS, INC. , CO, Reynaldo , MELCHER, DeAnn, Eileen , PAN, Weiping , VILLAVICENCIO, Grant
发明人： CO, Reynaldo , MELCHER, DeAnn, Eileen , PAN, Weiping , VILLAVICENCIO, Grant
IPC分类号： H01L21/78
CPC分类号： H01L21/78 , H01L21/6835 , H01L21/6836 , H01L24/27 , H01L24/83 , H01L2221/68327 , H01L2221/6834 , H01L2221/68359 , H01L2224/274 , H01L2224/83191 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets. Subsequent to the first cutting procedure, and prior to the second cutting procedure, additional die preparation procedures that are sensitive to die shift may be carried out.
摘要翻译：根据本发明，通过两个阶段切割晶片来减小或基本消除晶片位移。在一些实施例中，在将晶片减薄到规定的模具厚度之前执行第一晶片切割程序; 并且在其他实施例中，在执行第一晶片切割程序之前将晶片减薄到规定的模具厚度。第一晶片切割程序包括沿着第一组街道切割到大于规定模具厚度的深度，并且可选地沿着第二组街道切割至小于模具厚度的深度。第一切割过程的结果是一组带状或模具块，每个包括多个连接的模具，其比单独的单个模具更少受到偏移。在第二晶片切割过程中，通过沿着第二组街道切割来切割模具。在第一切割过程之后，并且在第二切割过程之前，可以进行对模移的敏感的附加的模具制备程序。

5. 发明申请

WO2011146579A2 ELECTRICAL CONNECTOR BETWEEN DIE PAD AND Z-INTERCONNECT FOR STACKED DIE ASSEMBLIES 审中-公开
标题翻译：用于堆叠式电池组件的电路板和Z型互连器之间的电连接器
公开(公告)号：WO2011146579A2
公开(公告)日：2011-11-24
申请号：PCT/US2011/036941
申请日：2011-05-18
申请人： VERTICAL CIRCUITS, INC. , CO, Reynaldo , LEAL, Jeffrey, S. , PANGRLE, Suzette, K. , MCGRATH, Scott , MELCHER, DeAnn, Eileen , BARRIE, Keith, L. , VILLLAVICENCIO, Grant , DEL ROSARIO, Elmer, M. , BRAY, John, R.
发明人： CO, Reynaldo , LEAL, Jeffrey, S. , PANGRLE, Suzette, K. , MCGRATH, Scott , MELCHER, DeAnn, Eileen , BARRIE, Keith, L. , VILLLAVICENCIO, Grant , DEL ROSARIO, Elmer, M. , BRAY, John, R.
CPC分类号： H01L25/0657 , H01L21/6836 , H01L21/78 , H01L23/3171 , H01L23/3185 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/18 , H01L24/24 , H01L24/82 , H01L25/50 , H01L2221/68327 , H01L2221/68336 , H01L2224/0235 , H01L2224/02371 , H01L2224/03002 , H01L2224/03318 , H01L2224/0332 , H01L2224/03632 , H01L2224/03848 , H01L2224/05016 , H01L2224/05017 , H01L2224/0529 , H01L2224/05553 , H01L2224/24051 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/76155 , H01L2224/82102 , H01L2224/94 , H01L2225/06551 , H01L2225/06562 , H01L2225/06568 , H01L2924/01327 , H01L2924/14 , H01L2924/00 , H01L2224/03
摘要： Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.
摘要翻译：在晶片级处理中在芯片焊盘上形成连接器的方法包括在芯片焊盘上形成可固化的导电材料的点并且延伸到互连芯片边缘上或之上; 固化导电材料; 并且在切割步骤之后切断斑点。而且，通过这些方法形成的管芯焊盘到z-互连连接器，并相应地成形和尺寸。而且，堆叠的模具组件和包含根据方法制备的模具的堆叠模具组件，并且具有通过所述方法形成并且形状和尺寸的模具垫到z互连连接器。

6. 发明申请

WO2009155247A3 SEMICONDUCTOR DIE SEPARATION METHOD 审中-公开
标题翻译：半导体分离方法
公开(公告)号：WO2009155247A3
公开(公告)日：2010-03-11
申请号：PCT/US2009047389
申请日：2009-06-15
申请人： VERTICAL CIRCUITS INC , CO REYNALDO , MELCHER DEANN EILEEN , PAN WEIPING , VILLAVICENCIO GRANT
发明人： CO REYNALDO , MELCHER DEANN EILEEN , PAN WEIPING , VILLAVICENCIO GRANT
IPC分类号： H01L21/78
CPC分类号： H01L21/78 , H01L21/6835 , H01L21/6836 , H01L24/27 , H01L24/83 , H01L2221/68327 , H01L2221/6834 , H01L2221/68359 , H01L2224/274 , H01L2224/83191 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets. Subsequent to the first cutting procedure, and prior to the second cutting procedure, additional die preparation procedures that are sensitive to die shift may be carried out.
摘要翻译：根据本发明，通过两个阶段切割晶片来减小或基本消除晶片位移。在一些实施例中，在将晶片减薄到规定的模具厚度之前执行第一晶片切割程序; 并且在其他实施例中，在执行第一晶片切割程序之前将晶片减薄到规定的模具厚度。第一晶片切割程序包括沿着第一组街道切割到大于规定模具厚度的深度，并且可选地沿着第二组街道切割至小于模具厚度的深度。第一切割过程的结果是一组带状或模具块，每个包括多个连接的模具，其比单独的单个模具更少受到偏移。在第二晶片切割过程中，通过沿着第二组街道切割来切割模具。在第一切割过程之后，并且在第二切割过程之前，可以进行对模移的敏感的附加的模具制备程序。

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