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1. 发明申请

WO2004109803A1 PLANAR POLYMER MEMORY DEVICE 审中-公开
标题翻译：平面聚合物存储器件
公开(公告)号：WO2004109803A1
公开(公告)日：2004-12-16
申请号：PCT/US2004/014696
申请日：2004-05-11
申请人： ADVANCED MICRO DEVICES, INC. , TRIPSAS, Nicholas, H. , BUYNOSKI, Matthew , OKOROANYANWU, Uzodinma , PANGRLE, Suzette, K.
发明人： TRIPSAS, Nicholas, H. , BUYNOSKI, Matthew , OKOROANYANWU, Uzodinma , PANGRLE, Suzette, K.
IPC分类号： H01L27/00
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/5664 , G11C13/0016 , H01L27/28 , H01L51/0575
摘要： The present invention provides a planar polymer memory device (100) that can operate as a non-volatile memory device. A planar polymer memory device (100) can be formed with two or more electrodes and an electrode extension associated with one electrode, wherein a selectively conductive medium and dielectric separate the electrodes. The method for forming a planar polymer memory device (100) comprises at least one of forming a first electrode (125) with an associated plug, forming a second electrode (140), forming a passive layer (130) over the extension, depositing an organic polymer and patterning the organic polymer (115). The method affords integration of a planar polymer memory device into a semiconductor fabrication process. A thin film diode (TFD) can further be employed with a planar polymer memory device (100) to facilitate programming. The TFD can be formed between the first electrode (125) and the selectively conductive medium or the second electrode (140) and the selectively conductive medium.
摘要翻译：本发明提供可作为非易失性存储器件操作的平面聚合物存储器件（100）。平面聚合物存储器件（100）可以形成有两个或更多个电极和与一个电极相关联的电极延伸部分，其中选择性导电介质和电介质分离电极。用于形成平面聚合物存储器件（100）的方法包括形成具有相关插塞的第一电极（125），形成第二电极（140），在延伸部分上形成钝化层（130），沉积有机聚合物和图案化有机聚合物（115）。该方法将平面聚合物存储器件集成到半导体制造工艺中。还可以与平面聚合物存储器件（100）一起使用薄膜二极管（TFD），以便于编程。 TFD可以形成在第一电极（125）和选择性导电介质或第二电极（140）和选择性导电介质之间。

2. 发明申请

WO2005010892A1 POLYMER MEMORY DEVICE FORMED IN VIA OPENING 审中-公开
标题翻译：聚合物存储器件通过开放形成
公开(公告)号：WO2005010892A1
公开(公告)日：2005-02-03
申请号：PCT/US2004/014797
申请日：2004-05-11
申请人： ADVANCED MICRO DEVICES, INC. , TRIPSAS, Nicholas, H. , BUYNOSKI, Matthew , PANGRLE, Suzette, K. , OKOROANYANWU, Uzodinma , HUI, Angela, T. , LYONS, Christopher, F. , SUBRAMANIAN, Ramkumar , LOPATIN, Sergey, D. , NGO, Minh, Van , KHATHURIA, Ashok, M. , CHANG, Mark, S. , CHEUNG, Patrick, K. , OGLESBY, Jane, V.
发明人： TRIPSAS, Nicholas, H. , BUYNOSKI, Matthew , PANGRLE, Suzette, K. , OKOROANYANWU, Uzodinma , HUI, Angela, T. , LYONS, Christopher, F. , SUBRAMANIAN, Ramkumar , LOPATIN, Sergey, D. , NGO, Minh, Van , KHATHURIA, Ashok, M. , CHANG, Mark, S. , CHEUNG, Patrick, K. , OGLESBY, Jane, V.
IPC分类号： G11C13/02
CPC分类号： H01L27/285 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.
摘要翻译：本发明的一个方面涉及在通孔中制造聚合物存储器件的方法。该方法包括提供其上具有至少一个含金属层的半导体衬底，在含金属层中形成至少一个铜触点，在铜触点上形成至少一个电介质层，在电介质层中形成至少一个通孔露出铜触点的至少一部分，在通孔的下部形成聚合物材料，并在通孔的上部形成顶部电极材料层。

3. 发明申请

WO2006055482A1 DIODE ARRAY ARCHITECTURE FOR ADDRESSING NANOSCALE RESISTIVE MEMORY ARRAYS 审中-公开
标题翻译：用于解决纳米电阻记忆阵列的二极体阵列
公开(公告)号：WO2006055482A1
公开(公告)日：2006-05-26
申请号：PCT/US2005/041173
申请日：2005-11-10
申请人： SPANSION LLC , TRIPSAS, Nicholas, H. , BILL, Colin, S. , VANBUSKIRK, Michael, A. , BUYNOSKI, Matthew , FANG, Tzu-Ning , CAI, Wei, Daisy , PANGRLE, Suzette, K. , AVANZINO, Steven
发明人： TRIPSAS, Nicholas, H. , BILL, Colin, S. , VANBUSKIRK, Michael, A. , BUYNOSKI, Matthew , FANG, Tzu-Ning , CAI, Wei, Daisy , PANGRLE, Suzette, K. , AVANZINO, Steven
IPC分类号： H01L27/10 , H01L27/102
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0007 , G11C2213/56 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/101 , H01L27/1021
摘要： The present memory structure includes thereof a first conductor (BL), a second conductor (WL), a resistive memory cell (130) connected to the second conductor (WL), a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL), and oriented in the forward direction from the resistive memory cell (130) to the first conductor (BL), and a second diode (132) connected to the resistive memory cell (130) and the first conductor (BL), in parallel with the first diode (134), and oriented in the reverse direction from the resistive memory cell (130) to the first conductor (BL). The first and second diodes (134, 132) have different threshold voltages.
摘要翻译：本存储器结构包括第一导体（BL），第二导体（WL），连接到第二导体（WL）的电阻性存储单元（130），连接到电阻式存储单元（130）的第一二极管）和第一导体（BL），并且从正向方向从电阻性存储单元（130）定向到第一导体（BL）;以及第二二极管（132），连接到电阻性存储单元（130）和第一导体（BL），与第一二极管（134）并联，并且从电阻式存储单元（130）到第一导体（BL）的反向定向。第一和第二二极管（134,132）具有不同的阈值电压。

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