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1. 发明申请

WO2008060772A1 METHOD OF PACKAGING A DEVICE HAVING A MULTI-CONTACT ELASTOMER CONNECTOR CONTACT AREA AND DEVICE THEREOF 审中-公开
标题翻译：包装多接触弹性体连接器接触区域的装置的方法及其装置
公开(公告)号：WO2008060772A1
公开(公告)日：2008-05-22
申请号：PCT/US2007/080241
申请日：2007-10-03
申请人： FREESCALE SEMICONDUCTOR INC. , MANGRUM, Marc A. , BURCH, Kenneth R.
发明人： MANGRUM, Marc A. , BURCH, Kenneth R.
IPC分类号： H01L23/34
CPC分类号： H01L23/5389 , H01L23/49811 , H01L24/19 , H01L24/72 , H01L24/82 , H01L2224/04105 , H01L2224/131 , H01L2224/16145 , H01L2224/16227 , H01L2224/24137 , H01L2224/73209 , H01L2224/81815 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/12044 , H01L2924/15153 , H01L2924/181 , H01L2924/00
摘要： Forming a packaged device (10) having a semiconductor device (14) having a first major surface and a second major surface includes forming an encapsulating layer (18) over the second major surface of the semiconductor device (14) and around sides of the semiconductor device (14) and leaving the first major surface of the first semiconductor device exposed. A first insulating layer (46) is formed over the first major surface. A plurality of vias (48-56) are formed in the first insulating layer (46). A plurality of contacts (58-66) are formed to the semiconductor device (14) through the first plurality of vias (48-56), wherein each of the plurality of contacts (58-66) has a surface above the first insulating layer (46). A supporting layer (72) is formed over the first insulating layer (46) leaving an opening (70) over the first plurality of contacts (58-66) wherein the opening (70) has a sidewall surrounding the plurality of contacts (58-66).
摘要翻译：形成具有具有第一主表面和第二主表面的半导体器件（14）的封装器件（10）包括在半导体器件（14）的第二主表面上并在半导体器件的侧面周围形成封装层（18）器件（14）并且使第一半导体器件的第一主表面露出。第一绝缘层（46）形成在第一主表面上。多个通孔（48-56）形成在第一绝缘层（46）中。多个触点（58-66）通过第一多个通孔（48-56）形成到半导体器件（14），其中多个触点（58-66）中的每一个具有在第一绝缘层之上的表面（46）。支撑层（72）形成在第一绝缘层（46）之上，在第一多个触头（58-66）上留下开口（70），其中开口（70）具有围绕多个触点（58-66）的侧壁， 66）。

2. 发明申请

WO2007120282A2 STACKABLE MOLDED PACKAGES AND METHODS OF MAKING THE SAME 审中-公开
标题翻译：可堆叠成型的包装及其制造方法
公开(公告)号：WO2007120282A2
公开(公告)日：2007-10-25
申请号：PCT/US2006/061127
申请日：2006-11-21
申请人： FREESCALE SEMICONDUCTOR INC. , MISTRY, Addi B. , MANGRUM, Marc A. , PATTEN, David T. , PHOU, Jesse , TRAN, Ziep
发明人： MISTRY, Addi B. , MANGRUM, Marc A. , PATTEN, David T. , PHOU, Jesse , TRAN, Ziep
IPC分类号： H01L21/00
CPC分类号： H01L23/552 , H01L21/561 , H01L23/24 , H01L23/3128 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/105 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/3025 , H01L2924/3511 , H01L2224/85 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A first packaged integrated circuit (IC) includes a package substrate (80), at least one IC die (82) attached to a first surface of the package substrate, a plurality of conductive members (84) on the first surface at least partially surrounding the at least one IC die (82) and electrically connected to the at least one IC die (82), an encapsulant (86) over the first surface surrounding the at least one IC die (82) and the plurality of conductive members (84), wherein at least a portion of each of the plurality of conductive members (84) is exposed by the encapsulant (86). A second packaged IC (90) may be stacked onto the first packaged IC. The second packaged IC (90) includes at least one IC die (92) and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC (90) is in contact with a corresponding conductive member of the plurality conductive members (84) of the first packaged IC.
摘要翻译：第一封装集成电路（IC）包括封装基板（80），附接到封装基板的第一表面的至少一个IC管芯（82），在第一表面上的至少部分环绕的多个导电构件（84）所述至少一个IC管芯（82）并且电连接到所述至少一个IC管芯（82）;在所述第一表面上围绕所述至少一个IC管芯（82）和所述多个导电构件（84）的密封剂（86）），其中所述多个导电构件（84）中的每一个的至少一部分被所述密封剂（86）暴露。第二封装IC（90）可以堆叠在第一封装IC上。第二封装IC（90）包括至少一个IC管芯（92）和多个导电构件，第二封装IC（90）的多个导电构件中的每个导电构件与相应的导电构件第一封装IC的多个导电构件（84）。

3. 发明申请

WO2008063744A1 METHOD OF PACKAGING A DEVICE HAVING A KEYPAD SWITCH POINT 审中-公开
标题翻译：封装具有键盘开关点的装置的方法
公开(公告)号：WO2008063744A1
公开(公告)日：2008-05-29
申请号：PCT/US2007/079722
申请日：2007-09-27
申请人： FREESCALE SEMICONDUCTOR INC. , BURCH, Kenneth R. , MANGRUM, Marc A.
发明人： BURCH, Kenneth R. , MANGRUM, Marc A.
IPC分类号： H01L21/00
CPC分类号： H01L21/568 , H01L21/561 , H01L23/3128 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/24137 , H01L2224/97 , H01L2924/01029 , H01L2924/01078 , H01L2924/15311 , H01L2924/19043
摘要： A packaged device (10) has a semiconductor device (14) that has a first major surface and a second major surface. An encapsulating layer (18) is formed over the second major surface and around sides of the semiconductor device (14). The first major surface of the semiconductor device (14) is left exposed. The semiconductor device (14) has the ability to perform a keypad function and has a first contact (13) that has a surface that is external to the semiconductor device. The first contact (13) is used in performing the keypad function. A first dielectric layer (20) is formed over the first major surface. A second dielectric layer (42) is formed over the second major surface. A second contact (50) that has a surface that is external to the packaged device (10) is connected to the first contact (13). A keypad (65) can be connected to the second contact (50). The number of such first and second contacts is variable based on the keypad (65).
摘要翻译：封装装置（10）具有半导体装置（14），其具有第一主表面和第二主表面。在半导体器件（14）的第二主表面和侧面上形成封装层（18）。半导体器件（14）的第一主表面被暴露。半导体器件（14）具有执行小键盘功能的能力，并且具有第一触点（13），该第一触点具有在半导体器件外部的表面。第一个触点（13）用于执行键盘功能。第一介电层（20）形成在第一主表面上。第二介电层（42）形成在第二主表面上。具有在封装装置（10）外部的表面的第二触点（50）连接到第一触点（13）。键盘（65）可以连接到第二触点（50）。这样的第一和第二触点的数量可以基于键盘（65）而变化。

4. 发明申请

WO2007120282A3 STACKABLE MOLDED PACKAGES AND METHODS OF MAKING THE SAME 审中-公开
标题翻译：可堆叠成型的包装及其制造方法
公开(公告)号：WO2007120282A3
公开(公告)日：2008-04-10
申请号：PCT/US2006061127
申请日：2006-11-21
申请人： FREESCALE SEMICONDUCTOR INC , MISTRY ADDI B , MANGRUM MARC A , PATTEN DAVID T , PHOU JESSE , TRAN ZIEP
发明人： MISTRY ADDI B , MANGRUM MARC A , PATTEN DAVID T , PHOU JESSE , TRAN ZIEP
IPC分类号： H01L21/00
CPC分类号： H01L23/552 , H01L21/561 , H01L23/24 , H01L23/3128 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/105 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/3025 , H01L2924/3511 , H01L2224/85 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A first packaged integrated circuit (IC) includes a package substrate (80), at least one IC die (82) attached to a first surface of the package substrate, a plurality of conductive members (84) on the first surface at least partially surrounding the at least one IC die (82) and electrically connected to the at least one IC die (82), an encapsulant (86) over the first surface surrounding the at least one IC die (82) and the plurality of conductive members (84), wherein at least a portion of each of the plurality of conductive members (84) is exposed by the encapsulant (86). A second packaged IC (90) may be stacked onto the first packaged IC. The second packaged IC (90) includes at least one IC die (92) and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC (90) is in contact with a corresponding conductive member of the plurality conductive members (84) of the first packaged IC.
摘要翻译：第一封装集成电路（IC）包括封装基板（80），附接到封装基板的第一表面的至少一个IC管芯（82），在第一表面上的至少部分环绕的多个导电构件（84）所述至少一个IC管芯（82）并且电连接到所述至少一个IC管芯（82）;在所述第一表面上围绕所述至少一个IC管芯（82）和所述多个导电构件（84）的密封剂（86）），其中所述多个导电构件（84）中的每一个的至少一部分被所述密封剂（86）暴露。第二封装IC（90）可以堆叠在第一封装IC上。第二封装IC（90）包括至少一个IC管芯（92）和多个导电构件，第二封装IC（90）的多个导电构件中的每个导电构件与相应的导电构件第一封装IC的多个导电构件（84）。

5. 发明申请

WO2006112949A3 STRUCTURE FOR STACKING AN INTEGRATED CIRCUIT ON ANOTHER INTEGRATED CIRCUIT 审中-公开
标题翻译：在其他集成电路上堆叠集成电路的结构
公开(公告)号：WO2006112949A3
公开(公告)日：2007-03-22
申请号：PCT/US2006006426
申请日：2006-02-23
申请人： FREESCALE SEMICONDUCTOR INC , MANGRUM MARC A
发明人： MANGRUM MARC A
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L25/105 , H01L23/367 , H01L23/49805 , H01L23/49811 , H01L23/49816 , H01L23/5389 , H01L23/552 , H01L23/573 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/0002 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H01L2924/00
摘要： Two or more semiconductor packages (14, 12) are stacked with an intervening element (16, 43) that is positioned between within an area surrounded by conductive bumps (28) of a bottom surface of the overlying package. Different shapes of the intervening element (16, 43) are used depending upon how many sides of the bottom surface have conductive bumps. In one form (Fig. 7) the intervening element extends laterally from the stack and is bent downward to contact or extend through an underlying substrate (30). Contact to the intervening element at the backside of the substrate may be made. In another form (Fig. 13) the intervening element is bent upward for enhancing thermal properties. The intervening element (16, 43) is adhesive to prevent non-destructive removal of the packages thereby adding increased security for information contained within the packages. Selective electrical shielding between packages is also provided.
摘要翻译：两个或多个半导体封装（14,12）被堆叠，中间元件（16,43）位于由覆盖封装的底表面的导电凸块（28）围绕的区域之间。取决于底面的多少边具有导电凸块，使用中间元件（16,43）的不同形状。在一种形式（图7）中，中间元件从堆叠横向延伸并向下弯曲以接触或延伸通过下面的基底（30）。可以在衬底的背面接触介入元件。在另一种形式（图13）中，中间元件向上弯曲以增强热性能。中间元件（16,43）是粘合剂，以防止包装件的非破坏性去除，从而增加包装中包含的信息的增加的安全性。还提供了包装之间的选择性电屏蔽。

6. 发明申请

WO2009035962A2 ELECTROMAGNETIC SHIELD FORMATION FOR INTEGRATED CIRCUIT DIE PACKAGE 审中-公开
标题翻译：用于集成电路电路封装的电磁屏蔽形成
公开(公告)号：WO2009035962A2
公开(公告)日：2009-03-19
申请号：PCT/US2008/075688
申请日：2008-09-09
申请人： FREESCALE SEMICONDUCTOR INC. , TANG, Jinbang , FREAR, Darrel , LIN, Jong-Kai , MANGRUM, Marc A. , BOOTH, Robert E. , HERR, Lawrence N. , BURCH, Kenneth R.
发明人： TANG, Jinbang , FREAR, Darrel , LIN, Jong-Kai , MANGRUM, Marc A. , BOOTH, Robert E. , HERR, Lawrence N. , BURCH, Kenneth R.
IPC分类号： H01L23/02
CPC分类号： H01L23/3121 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/552 , H01L24/19 , H01L24/96 , H01L24/97 , H01L25/0655 , H01L2221/68345 , H01L2223/6677 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/92 , H01L2224/97 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2224/96 , H01L2224/82 , H01L2924/00
摘要： Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings (401, 403) in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die (169). A layered redistribution structure is formed on one side of the encapsulated structure.
摘要翻译：集成电路封装器件的电磁屏蔽。该方法包括通过在封装结构中形成开口（401,403）来形成屏蔽结构。开口填充有围绕至少一个管芯的导电材料。封装结构可以包括多个集成电路管芯（169）。在封装结构的一侧上形成分层再分布结构。

7. 发明申请

WO2008063742A3 METHOD OF PACKAGING A SEMICONDUCTOR DEVICE AND A PREFABRICATED CONNECTOR 审中-公开
标题翻译：封装半导体器件和预制连接器的方法
公开(公告)号：WO2008063742A3
公开(公告)日：2008-07-17
申请号：PCT/US2007079714
申请日：2007-09-27
申请人： FREESCALE SEMICONDUCTOR INC , MANGRUM MARC A , BURCH KENNETH R
发明人： MANGRUM MARC A , BURCH KENNETH R
IPC分类号： H01L23/28 , H01L23/48
CPC分类号： H01L24/19 , H01L23/522 , H01L23/5389 , H01L24/72 , H01L24/82 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/18 , H01L2224/8192 , H01L2224/9202 , H01L2224/97 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/81 , H01L2224/82
摘要： A method of packaging a first device (12, 102) having a first major surface and a second major surface includes forming a first layer (14, 104) over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer (52, 152, 170) over the first major surface of the first device, forming a via (30, 32, 128) in the first dielectric layer, forming a seed layer (38, 40, 136) within the via and over a portion of the first dielectric layer, physically coupling a connector (82, 116) to the seed layer, and plating a conductive material over the seed layer to form a first interconnect (90, 92, 144, 164) in the first via and over a portion of the first dielectric layer.
摘要翻译：包装具有第一主表面和第二主表面的第一装置（12,102）的方法包括在第一装置的第二主表面上并且围绕第一装置的侧面形成第一层（14,104）并且离开所述第一器件的第一主表面暴露，其中所述第一层选自密封剂和聚合物; 在所述第一器件的所述第一主表面上形成第一电介质层（52,152,170），在所述第一电介质层中形成通孔（30,32，128），形成在所述第一电介质层内的晶种层（38,40,136）所述通孔和所述第一介电层的一部分上，将连接器（82,116）物理耦合到所述种子层，以及在所述籽晶层上镀覆导电材料以形成第一互连（90,92,144,164），以形成第一互连第一通孔和第一介电层的一部分。

8. 发明申请

WO2006112949A2 STRUCTURE FOR STACKING AN INTEGRATED CIRCUIT ON ANOTHER INTEGRATED CIRCUIT 审中-公开
标题翻译：在其他集成电路上堆叠集成电路的结构
公开(公告)号：WO2006112949A2
公开(公告)日：2006-10-26
申请号：PCT/US2006/006426
申请日：2006-02-23
申请人： FREESCALE SEMICONDUCTOR , MANGRUM, Marc A.
发明人： MANGRUM, Marc A.
IPC分类号： H01L23/48
CPC分类号： H01L25/105 , H01L23/367 , H01L23/49805 , H01L23/49811 , H01L23/49816 , H01L23/5389 , H01L23/552 , H01L23/573 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/0002 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H01L2924/00
摘要： Two or more semiconductor packages (14, 12) are stacked with an intervening element (16, 43) that is positioned between within an area surrounded by conductive bumps (28) of a bottom surface of the overlying package. Different shapes of the intervening element (16, 43) are used depending upon how many sides of the bottom surface have conductive bumps. In one form (Fig. 7) the intervening element extends laterally from the stack and is bent downward to contact or extend through an underlying substrate (30). Contact to the intervening element at the backside of the substrate may be made. In another form (Fig. 13) the intervening element is bent upward for enhancing thermal properties. The intervening element (16, 43) is adhesive to prevent non-destructive removal of the packages thereby adding increased security for information contained within the packages. Selective electrical shielding between packages is also provided.
摘要翻译：两个或多个半导体封装（14,12）被堆叠，中间元件（16,43）位于由覆盖封装的底表面的导电凸块（28）围绕的区域之间。取决于底面的多少边具有导电凸块，使用中间元件（16,43）的不同形状。在一种形式（图7）中，中间元件从堆叠横向延伸并向下弯曲以接触或延伸通过下面的基底（30）。可以在衬底的背面接触介入元件。在另一种形式（图13）中，中间元件向上弯曲以增强热性能。中间元件（16,43）是粘合剂，以防止包装件的非破坏性去除，从而增加包装中包含的信息的增加的安全性。还提供了包装之间的选择性电屏蔽。

9. 发明申请

WO2009035962A3 ELECTROMAGNETIC SHIELD FORMATION FOR INTEGRATED CIRCUIT DIE PACKAGE 审中-公开
标题翻译：用于集成电路电路封装的电磁屏蔽形成
公开(公告)号：WO2009035962A3
公开(公告)日：2010-07-22
申请号：PCT/US2008075688
申请日：2008-09-09
申请人： FREESCALE SEMICONDUCTOR INC , TANG JINBANG , FREAR DARREL , LIN JONG-KAI , MANGRUM MARC A , BOOTH ROBERT E , HERR LAWRENCE N , BURCH KENNETH R
发明人： TANG JINBANG , FREAR DARREL , LIN JONG-KAI , MANGRUM MARC A , BOOTH ROBERT E , HERR LAWRENCE N , BURCH KENNETH R
IPC分类号： H01L23/02
CPC分类号： H01L23/3121 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/552 , H01L24/19 , H01L24/96 , H01L24/97 , H01L25/0655 , H01L2221/68345 , H01L2223/6677 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/92 , H01L2224/97 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2224/96 , H01L2224/82 , H01L2924/00
摘要： Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings (401, 403) in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die (169). A layered redistribution structure is formed on one side of the encapsulated structure.
摘要翻译：集成电路封装器件的电磁屏蔽。该方法包括通过在封装结构中形成开口（401,403）来形成屏蔽结构。开口填充有围绕至少一个管芯的导电材料。封装结构可以包括多个集成电路管芯（169）。在封装结构的一侧上形成分层再分布结构。

10. 发明申请

WO2009158057A1 TEST INTERPOSER HAVING ACTIVE CIRCUIT COMPONENT AND METHOD THEREFOR 审中-公开
标题翻译：具有有效电路组件的测试插座及其方法
公开(公告)号：WO2009158057A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/039635
申请日：2009-04-06
申请人： FREESCALE SEMICONDUCTOR INC. , MANGRUM, Marc, A. , PATTEN, David, T. , BURCH, Kenneth, R.
发明人： MANGRUM, Marc, A. , PATTEN, David, T. , BURCH, Kenneth, R.
IPC分类号： G01R31/3183 , G01R31/26 , H01L21/66
CPC分类号： G01R31/2889 , G01R1/0408
摘要： A device under test (DUT) (140) is tested via a test interposer (130). The test interposer (130) includes a first set of contacts (232, 332, 832) at a first surface (131) to interface with the contacts of a load board (120) or other interface of an automated test equipment (ATE) (110) and a second set of contacts (234, 334, 834) at an opposing second surface (132) to interface with the contacts of the DUT (140). The second set of contacts (234, 334, 834) can have a smaller contact pitch (338, 838) than the contact pitch (336, 836) of the first set of contacts (232, 332, 832) to facilitate connection to the smaller pitch (338, 838) of the contacts of the DUT (140). The test interposer (130) further includes one or more active circuit components (340, 342) or passive circuit components (340, 342) to facilitate testing of the DUT (140). The test interposer (130) can be implemented as an integrated circuit (IC) package (301) that encapsulates the circuit components (340, 342).
摘要翻译：被测设备（DUT）（140）通过测试插件（130）进行测试。测试插入器（130）包括在第一表面（131）处的第一组触点（232,332,832），以与负载板（120）的触点或自动测试设备（ATE）的其他接口 110）和在相对的第二表面（132）处的第二组触点（234,334,834）以与DUT（140）的触点相接合。第二组触点（234,334,834）可以具有比第一组触点（232,332,832）的接触间距（336,836）更小的接触间距（338,838），以便于连接到 DUT（140）的触点的较小间距（338,838）。测试插入器（130）还包括一个或多个有源电路部件（340,342）或无源电路部件（340,342），以便于DUT（140）的测试。测试插入器（130）可以被实现为封装电路组件（340,342）的集成电路（IC）封装（301）。

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