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1. 发明申请

WO2009035962A3 ELECTROMAGNETIC SHIELD FORMATION FOR INTEGRATED CIRCUIT DIE PACKAGE 审中-公开
标题翻译：用于集成电路电路封装的电磁屏蔽形成
公开(公告)号：WO2009035962A3
公开(公告)日：2010-07-22
申请号：PCT/US2008075688
申请日：2008-09-09
申请人： FREESCALE SEMICONDUCTOR INC , TANG JINBANG , FREAR DARREL , LIN JONG-KAI , MANGRUM MARC A , BOOTH ROBERT E , HERR LAWRENCE N , BURCH KENNETH R
发明人： TANG JINBANG , FREAR DARREL , LIN JONG-KAI , MANGRUM MARC A , BOOTH ROBERT E , HERR LAWRENCE N , BURCH KENNETH R
IPC分类号： H01L23/02
CPC分类号： H01L23/3121 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/552 , H01L24/19 , H01L24/96 , H01L24/97 , H01L25/0655 , H01L2221/68345 , H01L2223/6677 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/92 , H01L2224/97 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2224/96 , H01L2224/82 , H01L2924/00
摘要： Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings (401, 403) in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die (169). A layered redistribution structure is formed on one side of the encapsulated structure.
摘要翻译：集成电路封装器件的电磁屏蔽。该方法包括通过在封装结构中形成开口（401,403）来形成屏蔽结构。开口填充有围绕至少一个管芯的导电材料。封装结构可以包括多个集成电路管芯（169）。在封装结构的一侧上形成分层再分布结构。

2. 发明申请

WO2008063742A3 METHOD OF PACKAGING A SEMICONDUCTOR DEVICE AND A PREFABRICATED CONNECTOR 审中-公开
标题翻译：封装半导体器件和预制连接器的方法
公开(公告)号：WO2008063742A3
公开(公告)日：2008-07-17
申请号：PCT/US2007079714
申请日：2007-09-27
申请人： FREESCALE SEMICONDUCTOR INC , MANGRUM MARC A , BURCH KENNETH R
发明人： MANGRUM MARC A , BURCH KENNETH R
IPC分类号： H01L23/28 , H01L23/48
CPC分类号： H01L24/19 , H01L23/522 , H01L23/5389 , H01L24/72 , H01L24/82 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/18 , H01L2224/8192 , H01L2224/9202 , H01L2224/97 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/81 , H01L2224/82
摘要： A method of packaging a first device (12, 102) having a first major surface and a second major surface includes forming a first layer (14, 104) over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer (52, 152, 170) over the first major surface of the first device, forming a via (30, 32, 128) in the first dielectric layer, forming a seed layer (38, 40, 136) within the via and over a portion of the first dielectric layer, physically coupling a connector (82, 116) to the seed layer, and plating a conductive material over the seed layer to form a first interconnect (90, 92, 144, 164) in the first via and over a portion of the first dielectric layer.
摘要翻译：包装具有第一主表面和第二主表面的第一装置（12,102）的方法包括在第一装置的第二主表面上并且围绕第一装置的侧面形成第一层（14,104）并且离开所述第一器件的第一主表面暴露，其中所述第一层选自密封剂和聚合物; 在所述第一器件的所述第一主表面上形成第一电介质层（52,152,170），在所述第一电介质层中形成通孔（30,32，128），形成在所述第一电介质层内的晶种层（38,40,136）所述通孔和所述第一介电层的一部分上，将连接器（82,116）物理耦合到所述种子层，以及在所述籽晶层上镀覆导电材料以形成第一互连（90,92,144,164），以形成第一互连第一通孔和第一介电层的一部分。

3. 发明申请

WO2008063761A2 METHOD OF PACKAGING A DEVICE USING A DIELECTRIC LAYER 审中-公开
标题翻译：使用介质层封装器件的方法
公开(公告)号：WO2008063761A2
公开(公告)日：2008-05-29
申请号：PCT/US2007080523
申请日：2007-10-05
申请人： FREESCALE SEMICONDUCTOR INC , MANGRUM MARC A , BURCH KENNETH R
发明人： MANGRUM MARC A , BURCH KENNETH R
IPC分类号： H01L21/77
CPC分类号： H01L23/5389 , H01L21/568 , H01L21/6835 , H01L24/24 , H01L24/82 , H01L24/96 , H01L24/97 , H01L25/16 , H01L28/20 , H01L2224/04105 , H01L2224/12105 , H01L2224/24011 , H01L2224/24195 , H01L2224/82001 , H01L2224/97 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01077 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/15192 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3011 , H05K1/185 , H05K3/4644 , H05K2201/0919 , H01L2224/82
摘要： A method is for packaging a first device (14, 46) having a first major surface and a second major surface. An encapsulant (18) is formed over a second major surface of the first device (14, 46) and around sides of the first device. This leaves the first major surface of the first device exposed. A first dielectric layer (20) is formed over the first major surface of the first device (14). a side contact interface (36, 16; 48, 56, 46; 48, 56, 70, 72) is formed having at least a portion over the first dielectric layer (20). The encapsulant (18) is cut to form a plurality of sides of encapsulant (62, 64). A portion of the encapsulant (18) is removed along a first side (64) of the plurality of sides to expose a portion of the side contact interface (72, 46, 16) along the first side of the plurality of sides.
摘要翻译：一种用于包装具有第一主表面和第二主表面的第一装置（14,46）的方法。密封剂（18）形成在第一装置（14,46）的第二主表面上并且围绕第一装置的侧面。这使第一个器件的第一个主表面露出来。在第一装置（14）的第一主表面上形成第一电介质层（20）。形成具有在第一介电层（20）上方的至少一部分的侧面接触界面（36,16; 48,56,46; 48,56,70,72）。密封剂（18）被切割以形成密封剂（62,64）的多个侧面。密封剂（18）的一部分沿着多个侧面的第一侧（64）移除，以沿着多个侧面的第一侧暴露侧接触界面（72,46,16）的一部分。

4. 发明申请

WO2011126614A3 APPARATUS AND METHOD TO COMPENSATE FOR INJECTION LOCKING 审中-公开
标题翻译：补充注射锁定的装置和方法
公开(公告)号：WO2011126614A3
公开(公告)日：2011-12-01
申请号：PCT/US2011025872
申请日：2011-02-23
申请人： FREESCALE SEMICONDUCTOR INC , STEPHENS SAMUEL G , BURCH KENNETH R
发明人： STEPHENS SAMUEL G , BURCH KENNETH R
IPC分类号： H03L7/081 , H03L7/087
CPC分类号： H03L7/07
摘要： A circuit (10, 90, 100) and method (70) has a processing unit (28), a master clock generator (12) for providing a master clock and a plurality of phase-locked loops (14, 16, 18), each providing a respective clock signal. A plurality of dynamically variable delay circuits (30, 32, 34) each has a plurality of predetermined delay amounts. Clocked circuits (20, 22, 24) are coupled to respective clock signals provided by respective phase-locked loops. A performance detector (102) is coupled to receive the clock signals for determining a center of a quiet zone for at least one of the plurality of phase-locked loops (82). The phase-locked loops are turned off and on (86) and a respective one of the plurality of dynamically variable delay circuits is set to have a new predetermined value of delay which adjusts an edge of the master clock to a location that permits the data processing system to operate near substantially the center of the quiet zone (82, 84).
摘要翻译：电路（10,90,100）和方法（70）具有处理单元（28），用于提供主时钟和多个锁相环（14,16,18）的主时钟发生器（12）每个提供相应的时钟信号。多个动态可变延迟电路（30,32,34）各自具有多个预定延迟量。时钟电路（20,22,24）被耦合到由相应的锁相环提供的各个时钟信号。性能检测器（102）被耦合以接收用于确定多个锁相环（82）中的至少一个的安静区域的中心的时钟信号。锁相环被断开并导通（86），并且多个动态可变延迟电路中的相应一个延迟电路被设置为具有新的预定延迟值，该延迟调整将主时钟的边沿调整到允许数据的位置处理系统在大致安静区域（82,84）的中心附近操作。

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