专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2009129283A1 MANUFACTURING METHOD OF A MAGNETIC TUNNEL JUNCTION ELEMENT USING TWO MASKS 审中-公开
标题翻译：使用两个掩模的磁性隧道结构元件的制造方法
公开(公告)号：WO2009129283A1
公开(公告)日：2009-10-22
申请号：PCT/US2009/040612
申请日：2009-04-15
申请人： QUALCOMM INCORPORATED , KANG, Seung, H. , LI, Xia , GU, Shiqun , NOWAK, Matthew, M.
发明人： KANG, Seung, H. , LI, Xia , GU, Shiqun , NOWAK, Matthew, M.
IPC分类号： H01L43/08 , H01L43/12
CPC分类号： H01L43/08 , G11C11/161 , H01L43/12
摘要： A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer (36) containing an exposed first interconnect metallization, (37) a first electrode, (30) a fixed magnetization layer, (32) a tunneling barrier layer, (12) a free magnetization layer (11) and a second electrode (6). An MTJ structure including the tunnel barrier layer, free layer and second electrode is defined above the first interconnect metallization by a first mask. A first passivation layer (40) encapsulates the MTJ structure, leaving the second electrode exposed. A third electrode (15) is deposited in contact with the second electrode. A second mask is used to pattern a larger structure including the third electrode, the first passivation layer, the fixed magnetization layer and the first electrode. A second dielectric passivation layer (8) covers the etched plurality of layers, the first interlevel dielectric layer and the first interconnect metallization.
摘要翻译：用于使用两个掩模形成用于磁性随机存取存储器（MRAM）的磁性隧道结（MTJ）的方法包括在包含暴露的第一互连金属化的层间介质层（36）上沉积（37）第一电极，（30）固定磁化层，（32）隧道势垒层，（12）自由磁化层（11）和第二电极（6）。包括隧道势垒层，自由层和第二电极的MTJ结构通过第一掩模限定在第一互连金属化之上。第一钝化层（40）封装MTJ结构，留下第二电极。沉积与第二电极接触的第三电极（15）。使用第二掩模来图案化包括第三电极，第一钝化层，固定磁化层和第一电极的较大结构。第二介电钝化层（8）覆盖被蚀刻的多个层，第一层间介质层和第一互连金属化层。

2. 发明申请

WO2011075491A1 VIA STRUCTURE INTEGRATED IN ELECTRONIC SUBSTRATE 审中-公开
标题翻译：通过集成在电子基板中的结构
公开(公告)号：WO2011075491A1
公开(公告)日：2011-06-23
申请号：PCT/US2010/060362
申请日：2010-12-14
申请人： QUALCOMM Incorporated , LI, Xia , ZHAO, Wei , CAO, Yu , GU, Shiqun , KANG, Seung H. , KING, Ming-Chu
发明人： LI, Xia , ZHAO, Wei , CAO, Yu , GU, Shiqun , KANG, Seung H. , KING, Ming-Chu
IPC分类号： H01L23/552 , H01L23/66 , H01L23/498 , H01L23/48 , H01L23/64 , H05K1/02
CPC分类号： H01L23/552 , H01L23/14 , H01L23/49827 , H01L23/645 , H01L23/66 , H01L2223/6616 , H01L2223/6622 , H01L2223/6638 , H01L2924/0002 , H01L2924/3011 , H05K1/0222 , H05K1/0245 , H05K3/4602 , H05K3/4644 , H05K2201/09809 , Y10T29/49117 , H01L2924/00
摘要： A system of via structures disposed in a substrate. The system includes a first via structure that comprises an outer conductive layer, an inner insulating layer, and an inner conductive layer disposed in the substrate. The outer conductive layer separates the inner insulating layer and the substrate and the inner insulating layer separates the inner conductive layer and the outer conductive layer. A first signal of a first complementary pair passes through the inner conductive layer and a second signal of the first complementary pair passes through the outer conductive layer. In different embodiments, a method of forming a via structure in an electronic substrate is provided.
摘要翻译：设置在基板中的通孔结构的系统。该系统包括第一通孔结构，其包括外导电层，内绝缘层和设置在基板中的内导电层。外部导电层分离内部绝缘层和基板，内部绝缘层分离内部导电层和外部导电层。第一互补对的第一信号通过内导电层，第一互补对的第二信号通过外导电层。在不同的实施例中，提供了一种在电子衬底中形成通孔结构的方法。

3. 发明申请

WO2009079662A1 MAGNETIC TUNNEL JUNCTION DEVICE WITH SEPARATE READ AND WRITE PATHS 审中-公开
标题翻译：具有单独读取和写入功能的磁性隧道连接装置
公开(公告)号：WO2009079662A1
公开(公告)日：2009-06-25
申请号：PCT/US2008/087748
申请日：2008-12-19
申请人： QUALCOMM Incorporated , ZHU, Xiaochun , GU, Shiqun , LI, Xia , KANG, Seung H.
发明人： ZHU, Xiaochun , GU, Shiqun , LI, Xia , KANG, Seung H.
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , Y10S977/933 , Y10S977/935
摘要： In an embodiment, a device is disclosed that includes a magnetic tunnel junction (MTJ) structure. The device also includes a read path (102) coupled to the MTJ structure and a write path (104) coupled to the MTJ structure. The write path (104) is separate from the read path (102). The device in substance comprises a pair of serially coupled MTJ structures (106, 108), whereby the read path (102) comprises only one of the MTJ structure (108). This provides for combined improved read margin and improved write margin.
摘要翻译：在一个实施例中，公开了一种包括磁隧道结（MTJ）结构的装置。该设备还包括耦合到MTJ结构的读取路径（102）和耦合到MTJ结构的写入路径（104）。写入路径（104）与读取路径（102）分离。实质的装置包括一对串联耦合的MTJ结构（106,108），由此读路径（102）仅包括MTJ结构（108）中的一个。这提供了组合改进的读取余量和改进的写入余量。

4. 发明申请

WO2010011448A2 PREDICTIVE MODELING OF INTERCONNECT MODULES FOR ADVANCED ON-CHIP INTERCONNECT TECHNOLOGY 审中-公开
标题翻译：用于高级片上互连技术的互连模块的预测建模
公开(公告)号：WO2010011448A2
公开(公告)日：2010-01-28
申请号：PCT/US2009/047668
申请日：2009-06-17
申请人： QUALCOMM INCORPORATED , LI, Xia , ZHAO, Wei , CAO, Yu , GU, Shiqun , KANG, Seung, H. , NOWAK, Matthew
发明人： LI, Xia , ZHAO, Wei , CAO, Yu , GU, Shiqun , KANG, Seung, H. , NOWAK, Matthew
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A computer program product estimates performance of an interconnect structure of a semiconductor integrated circuit (IC). The program product includes code executing on a computer to calculate at least one electrical characteristic of the interconnect structure based on input data accounting for multiple layers of the interconnect structure. The electrical characteristics can be capacitance, resistance, and/or inductance. The capacitance may be based upon multiple components, including a fringe capacitance component, a terminal capacitance component, and a coupling capacitance component.
摘要翻译：计算机程序产品估计半导体集成电路（IC）的互连结构的性能。程序产品包括在计算机上执行的代码，用于基于考虑到互连结构的多层的输入数据来计算互连结构的至少一个电特性。电气特性可以是电容，电阻和/或电感。电容可以基于多个分量，包括边缘电容分量，端子电容分量和耦合电容分量。

5. 发明申请

WO2009131944A1 STT MRAM MAGNETIC TUNNEL JUNCTION ARCHITECTURE AND INTEGRATION 审中-公开
标题翻译： STT MRAM磁铁隧道结构和集成
公开(公告)号：WO2009131944A1
公开(公告)日：2009-10-29
申请号：PCT/US2009/041132
申请日：2009-04-20
申请人： QUALCOMM INCORPORATED , KANG, Seung, H. , LI, Xia , GU, Shiqun , LEE, Kangho , ZHU, Xiaochun
发明人： KANG, Seung, H. , LI, Xia , GU, Shiqun , LEE, Kangho , ZHU, Xiaochun
IPC分类号： H01L43/08 , H01L27/22 , H01L43/12
CPC分类号： H01L27/222 , H01L43/08 , H01L43/12
摘要： A magnetic tunnel junction (MTJ) device (400) for a magnetic random access memory (MRAM) in a semiconductor back-end-of-line (BEOL) process flow includes a first metal interconnect (401) for communicating with at least one control device and a first electrode (406) for coupling to the first metal interconnect through a via formed in a dielectric passivation barrier (404) using a first mask. The device also includes an MTJ stack (407, 408, 409) for storing data coupled to the first electrode, a portion of the MTJ stack having lateral dimensions based upon a second mask. The portion defined by the second mask is over the contact via. A second electrode (410) is coupled to the MTJ stack and also has a same lateral dimension as defined by the second mask. The first electrode (406) and a portion (407) of the MTJ stack. are defined by a third mask. A second metal interconnect (415) is coupled to the second electrode and at least one other control device.
摘要翻译：用于半导体后端（BEOL）处理流程中的磁随机存取存储器（MRAM）的磁性隧道结（MTJ）装置（400）包括用于与至少一个控制器器件和第一电极（406），用于通过使用第一掩模在介电钝化屏障（404）中形成的通孔耦合到第一金属互连。该装置还包括用于存储耦合到第一电极的数据的MTJ堆叠（407,408,409），MTJ堆叠的一部分具有基于第二掩模的侧向尺寸。由第二掩模限定的部分在接触通孔之上。第二电极（410）耦合到MTJ堆叠并且还具有与第二掩模所限定的相同的横向尺寸。第一电极（406）和MTJ叠层的一部分（407）。由第三个掩码定义。第二金属互连（415）耦合到第二电极和至少一个其他控制装置。

6. 发明申请

WO2012027423A2 WIDE INPUT OUTPUT MEMORY WITH LOW DENSITY, LOW LATENCY AND HIGH DENSITY, HIGH LATENCY BLOCKS 审中-公开
标题翻译：宽输入输出存储器，低密度，低密度和高密度，高延迟块
公开(公告)号：WO2012027423A2
公开(公告)日：2012-03-01
申请号：PCT/US2011/048885
申请日：2011-08-24
申请人： QUALCOMM INCORPORATED , GU, Shiqun , NOWAK, Matthew, M. , SRINIVASAN, Anand
发明人： GU, Shiqun , NOWAK, Matthew, M. , SRINIVASAN, Anand
IPC分类号： H01L23/48 , G11C11/4076
CPC分类号： G11C11/4076 , H01L23/481 , H01L24/73 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/00012 , H01L2924/00
摘要： External memory having a high density, high latency memory block; and a low density, low latency memory block. The two memory blocks may be separately accessed by one or more processing functional units. The access may be a direct memory access, or by way of a bus or fabric switch. Through-die vias may connect the external memory to a die comprising the one or more processing functional units.
摘要翻译：具有高密度，高延迟的存储器块的外部存储器; 和低密度，低延迟的存储器块。两个存储器块可以被一个或多个处理功能单元单独访问。访问可以是直接存储器访问，或者通过总线或结构交换机。通孔通孔可以将外部存储器连接到包括一个或多个处理功能单元的管芯。

7. 发明申请

WO2009137286A1 3-D INTEGRATED CIRCUIT LATERAL HEAT DISSIPATION 审中-公开
标题翻译： 3-D集成电路横向散热
公开(公告)号：WO2009137286A1
公开(公告)日：2009-11-12
申请号：PCT/US2009/041780
申请日：2009-04-27
申请人： QUALCOMM INCORPORATED , KASKOUN, Kenneth , GU, Shiqun , NOWAK, Matthew, M.
发明人： KASKOUN, Kenneth , GU, Shiqun , NOWAK, Matthew, M.
IPC分类号： H01L25/065 , H01L23/367 , H01L23/373
CPC分类号： H01L25/0657 , H01L23/3677 , H01L23/3732 , H01L23/3735 , H01L2224/16145 , H01L2225/06513 , H01L2225/06589 , H01L2924/01019
摘要： By filling an air gap between tiers (31,32) of a stacked IC device with a thermally conductive material (320) heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the thermal materia can be electrically insulating. Through silicon-vias (331) can be constructe at certain locations to assist in heat dissipation away from thermally troubled locations (310).
摘要翻译：通过在层叠的IC器件的层（31,32）之间填充导热材料（320），在层之一内的一个或多个位置处产生的热可以横向移位。热的横向位移可以沿着层的整个长度，并且热材料可以是电绝缘的。通过硅通孔（331）可以在某些位置处构造以帮助远离热故障位置（310）的散热。

8. 发明申请

WO2010088669A1 MAGNETIC TUNNEL JUNCTION COMPRISING A TUNNEL BARRIER, PINNED LAYER AND TOP ELECTRODE FORMED IN A DAMASCENE-TYPE PROCESS 审中-公开
标题翻译：包含隧道式障碍物，密封层和形成大型过程的顶部电极的磁隧道结
公开(公告)号：WO2010088669A1
公开(公告)日：2010-08-05
申请号：PCT/US2010/022887
申请日：2010-02-02
申请人： QUALCOMM INCORPORATED , GU, Shiqun , KANG, Seung, H. , ZHU, Xiaochun
发明人： GU, Shiqun , KANG, Seung, H. , ZHU, Xiaochun
IPC分类号： H01L27/22 , H01L43/08 , H01L43/12
CPC分类号： H01L43/12 , H01L27/222 , H01L27/228 , H01L27/24 , H01L29/82 , H01L43/08
摘要： A magnetic tunnel junction storage element for a spin transfer torque magnetoresistive random access memory (STT-MRAM) bit cell includes a bottom electrode layer, (150) a pinned layer (160) adjacent to the bottom electrode layer, a dielectric layer (70) encapsulating a portion of the bottom electrode layer and the pinned layer, the dielectric layer including sidewalls that define a hole adjacent to a portion of the pinned layer, a tunneling barrier (190) adjacent to the pinned layer, a free layer (200) adjacent to the tunneling barrier, and a top electrode (210) adjacent to the free layer, wherein a width of the bottom electrode layer and/or the pinned barrier in a first direction is greater than a width of a contact area between the pinned layer and the tunneling barrier in the first direction. Also a method of forming an STT-MRAM bit cell is disclosed.
摘要翻译：用于自旋转移磁阻随机存取存储器（STT-MRAM）位单元的磁性隧道结存储元件包括底部电极层，（150）邻近底部电极层的钉扎层（160），介电层（70）封装底部电极层和钉扎层的一部分，电介质层包括限定与被钉扎层的一部分相邻的孔的侧壁，邻近被钉扎层的隧道势垒（190），邻近的自由层（200）和与所述自由层相邻的顶部电极（210），其中所述底部电极层和/或所述被钉扎的屏障在第一方向上的宽度大于所述被钉扎层和所述被钉扎层之间的接触面积的宽度隧道屏障在第一个方向。还公开了一种形成STT-MRAM位单元的方法。

9. 发明申请

WO2009089360A1 MEMORY CELL AND METHOD OF FORMING A MAGNETIC TUNNEL JUNCTION (MTJ) OF A MEMORY CELL 审中-公开
标题翻译：存储单元和形成记忆体的磁性隧道结（MTJ）的方法
公开(公告)号：WO2009089360A1
公开(公告)日：2009-07-16
申请号：PCT/US2009/030451
申请日：2009-01-08
申请人： QUALCOMM Incorporated , GU, Shiqun , KANG, Seung, H. , NORWAK, Matthew, M.
发明人： GU, Shiqun , KANG, Seung, H. , NORWAK, Matthew, M.
IPC分类号： H01L43/08
CPC分类号： H01L43/08 , G11C11/161 , H01L27/228 , H01L43/12
摘要： A memory including a memory cell and method for producing the memory cell are disclosed. The memory includes a substrate in a first plane. A first metal connection extending in a second plane is provided. The second plane is substantially perpendicular to the first plane. A magnetic tunnel junction (MTJ) is provided having a first layer coupled to the metal connection such that the first layer of the MTJ is oriented along the second plane.
摘要翻译：公开了一种包括存储单元的存储器及其制造方法。存储器包括在第一平面中的衬底。提供了在第二平面中延伸的第一金属连接。第二平面基本上垂直于第一平面。提供磁性隧道结（MTJ），其具有耦合到金属连接的第一层，使得MTJ的第一层沿着第二平面定向。

10. 发明申请

WO2011116325A1 THROUGH GLASS VIA MANUFACTURING PROCESS 审中-公开
标题翻译：通过制造过程的玻璃
公开(公告)号：WO2011116325A1
公开(公告)日：2011-09-22
申请号：PCT/US2011/029057
申请日：2011-03-18
申请人： QUALCOMM Incorporated , GU, Shiqun , LI, Xia , LI, Yiming
发明人： GU, Shiqun , LI, Xia , LI, Yiming
IPC分类号： H01L21/48 , H01L23/15 , H01L23/498
CPC分类号： H01L23/15 , H01L21/486 , H01L23/49827 , H01L2924/0002 , H05K3/0041 , Y10T428/24273 , H01L2924/00
摘要： Fabrication of a through glass via in a relatively thick glass substrate includes patterning a through glass via hard mask on a surface of the glass substrate. The fabrication also includes wet etching a portion of the glass substrate, through the hard mask, to create a partial through glass via. The wet etching may involve applying a vapor of an oxide etch chemical, such as HF and XeF6, or applying a wet oxide etch chemical, such as HF and XeF6. The fabrication further includes passivating the etched partial through glass via, removing bottom passivation from the partial through glass via, and repeating the etching, passivating and removing to create the through glass via. The resulting through glass via has a scalloped side wall, a vertical profile and a high aspect ratio.
摘要翻译：在相对厚的玻璃基板中制造直通玻璃通孔包括在玻璃基板的表面上通过硬掩模图案化通孔玻璃。该制造还包括通过硬掩模湿法蚀刻玻璃基底的一部分，以产生部分透过玻璃通孔。湿蚀刻可以包括施加氧化物蚀刻化学品的蒸气，例如HF和XeF 6，或者施加湿氧化物蚀刻化学品，例如HF和XeF 6。该制造还包括钝化蚀刻的部分通过玻璃通孔，从部分通过玻璃通孔去除底部钝化，并重复蚀刻，钝化和去除以产生通孔玻璃通孔。所产生的通过玻璃通孔具有扇形侧壁，垂直轮廓和高纵横比。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式