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1. 发明申请

WO2006071683A1 METHOD OF PROGRAMMING, READING AND ERASING MEMORY-DIODE IN A MEMORY-DIODE ARRAY 审中-公开
标题翻译：存储二极管阵列中编程，读取和擦除存储器二极管的方法
公开(公告)号：WO2006071683A1
公开(公告)日：2006-07-06
申请号：PCT/US2005/046406
申请日：2005-12-20
申请人： SPANSION LLC , BILL, Colin, S. , KAZA, Swaroop , FANG, Tzu-Ning , SPITZER, Stuart
发明人： BILL, Colin, S. , KAZA, Swaroop , FANG, Tzu-Ning , SPITZER, Stuart
IPC分类号： G11C16/10
CPC分类号： G11C11/36
摘要： A memory array (140) includes first and second sets of conductors (142), (144) and a plurality of memory-diodes (130), each connecting in a forward direction a conductor (BL) of the first set (142) with a conductor (WL) of the second set (144). An electrical potential is applied across a selected memory-diode (130), from higher to lower potential in the forward direction, intended to program the selected memory-diode (130). During this intended programming, each other memory-diode (130) in the array (140) has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode (130) can be established by applying an electrical potential across that memory-diode (130) from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array (140), problems related to current leakage and disturb are avoided.
摘要翻译：存储器阵列（140）包括第一和第二组导体（142），（144）和多个存储器二极管（130），每个存储器二极管（130）在前向方向上与第一组（142）的导体（BL）第二组（144）的导体（WL）。在所选择的存储器二极管（130）上施加电势，从正向上的较高电位到较低的电位，用于对所选择的存储器二极管（130）进行编程。在该期望的编程期间，阵列（140）中的每个其它存储器二极管（130）在其正向方向上提供了低于其阈值电压的电位。每个存储二极管（130）的阈值电压可以通过在该存储二极管（130）上施加从相反方向的较高电位到较低电位的电位来建立。通过这样建立足够的阈值电压，并且通过选择施加到阵列（140）的导体的适当电势，避免了与电流泄漏和干扰有关的问题。

2. 发明申请

WO2008054572A1 METHOD OF SELECTING OPERATING CHARACTERISTICS OF A RESISTIVE MEMORY DEVICE 审中-公开
标题翻译：选择电阻式存储器件操作特性的方法
公开(公告)号：WO2008054572A1
公开(公告)日：2008-05-08
申请号：PCT/US2007/018730
申请日：2007-08-23
申请人： SPANSION LLC , FANG, Tzu-Ning , KAZA, Swaroop , CHEN, An , HADDAD, Sameer
发明人： FANG, Tzu-Ning , KAZA, Swaroop , CHEN, An , HADDAD, Sameer
IPC分类号： G11C13/00 , H01L45/00
CPC分类号： G11C13/0007 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/52 , H01L27/2409 , H01L27/2436 , H01L45/10 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： In a method of providing an operating characteristic of a resistive memory device (38, 138), material of an electrode thereof is selected to in turn provide a selected operating characteristic of the device. The material of the electrode may be reacted with material of an insulating layer (134) of the resistive memory device to form a reaction layer (137), the selected operating characteristic being dependent on the presence of the reaction layer (137).
摘要翻译：在提供电阻式存储器件（38,138）的工作特性的方法中，选择其电极的材料，从而提供器件的选定工作特性。电极的材料可以与电阻式存储器件的绝缘层（134）的材料反应以形成反应层（137），所选择的操作特性取决于反应层（137）的存在。

3. 发明申请

WO2006055482A1 DIODE ARRAY ARCHITECTURE FOR ADDRESSING NANOSCALE RESISTIVE MEMORY ARRAYS 审中-公开
标题翻译：用于解决纳米电阻记忆阵列的二极体阵列
公开(公告)号：WO2006055482A1
公开(公告)日：2006-05-26
申请号：PCT/US2005/041173
申请日：2005-11-10
申请人： SPANSION LLC , TRIPSAS, Nicholas, H. , BILL, Colin, S. , VANBUSKIRK, Michael, A. , BUYNOSKI, Matthew , FANG, Tzu-Ning , CAI, Wei, Daisy , PANGRLE, Suzette, K. , AVANZINO, Steven
发明人： TRIPSAS, Nicholas, H. , BILL, Colin, S. , VANBUSKIRK, Michael, A. , BUYNOSKI, Matthew , FANG, Tzu-Ning , CAI, Wei, Daisy , PANGRLE, Suzette, K. , AVANZINO, Steven
IPC分类号： H01L27/10 , H01L27/102
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0007 , G11C2213/56 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/101 , H01L27/1021
摘要： The present memory structure includes thereof a first conductor (BL), a second conductor (WL), a resistive memory cell (130) connected to the second conductor (WL), a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL), and oriented in the forward direction from the resistive memory cell (130) to the first conductor (BL), and a second diode (132) connected to the resistive memory cell (130) and the first conductor (BL), in parallel with the first diode (134), and oriented in the reverse direction from the resistive memory cell (130) to the first conductor (BL). The first and second diodes (134, 132) have different threshold voltages.
摘要翻译：本存储器结构包括第一导体（BL），第二导体（WL），连接到第二导体（WL）的电阻性存储单元（130），连接到电阻式存储单元（130）的第一二极管）和第一导体（BL），并且从正向方向从电阻性存储单元（130）定向到第一导体（BL）;以及第二二极管（132），连接到电阻性存储单元（130）和第一导体（BL），与第一二极管（134）并联，并且从电阻式存储单元（130）到第一导体（BL）的反向定向。第一和第二二极管（134,132）具有不同的阈值电压。

4. 发明申请

WO2006104858A1 WRITE-ONCE READ-MANY TIMES MEMORY 审中-公开
标题翻译：一次写入多个时间记忆
公开(公告)号：WO2006104858A1
公开(公告)日：2006-10-05
申请号：PCT/US2006/010651
申请日：2006-03-24
申请人： SPANSION LLC , VANBUSKIRK, Michael, A. , BILL, Colin, S. , LAN, Zhida , FANG, Tzu-Ning
发明人： VANBUSKIRK, Michael, A. , BILL, Colin, S. , LAN, Zhida , FANG, Tzu-Ning
IPC分类号： G11C13/02
CPC分类号： G11C13/0014 , B82Y10/00
摘要： A write-once read-many times memory device (130) is made up of first and second electrodes (132, 138), a passive layer (134) between the first and second electrodes (132, 138), and an active layer (136) between the first and second electrodes. The memory device (130) is programmed by providing a charged species from the passive layer (134) into the active layer (136). The memory device (130) may be programmed to have for the programmed memory device (130) a first erase activation energy. The present method provides for the programmed memory device (130) a second erase activation energy greater than the first erase activation energy.
摘要翻译：一次写入许多次的存储器件（130）由第一和第二电极（132,138），第一和第二电极（132,138）之间的无源层（134）和有源层（ 136）在第一和第二电极之间。存储器件（130）通过将带电物质从无源层（134）提供到有源层（136）来编程。可以将存储器件（130）编程为使编程的存储器件（130）具有第一擦除激活能量。本方法为编程存储器件（130）提供大于第一擦除激活能量的第二擦除激活能量。

5. 发明申请

WO2007064334A1 POLYMER-BASED TRANSISTOR DEVICES, METHODS, AND SYSTEMS 审中-公开
标题翻译：基于聚合物的晶体管器件，方法和系统
公开(公告)号：WO2007064334A1
公开(公告)日：2007-06-07
申请号：PCT/US2005/043788
申请日：2005-12-02
申请人： ADVANCED MICRO DEVICES, INC. , BILL, Colin, S. , VANBUSKIRK, Michael, A. , LAN, Zhida , ENNALS, John, S. , FANG, Tzu-Ning
发明人： BILL, Colin, S. , VANBUSKIRK, Michael, A. , LAN, Zhida , ENNALS, John, S. , FANG, Tzu-Ning
IPC分类号： H01L51/05 , H01L29/786
CPC分类号： H01L51/0512 , H01L51/0508
摘要： Disclosed is a semiconductor transistor device (100) with an annular gate (118) surrounding, at least in part, a channel (110) that conducts current between a first (104) and second (114) source/drain. Also disclosed is a semiconductor transistor device (100) having an annular gate (118) and containing a channel (110) composed of a polymer material. Yet also disclosed is the fabrication of a device utilizing a polymer channel (110) surrounded, at least in part, by an annular gate (118). Further disclosed is a system with a means to control (and/or amplify) current via an annular gate (118) surrounding a channel (110) which conducts current between a first (104) and second (114) source/drain.
摘要翻译：公开了具有环形栅极（118）的半导体晶体管器件（100），该环形栅极至少部分地围绕在第一（104）和第二（114）源极/漏极之间传导电流的沟道（110）。还公开了具有环形栅极（118）并且包含由聚合物材料构成的沟道（110）的半导体晶体管器件（100）。还公开了使用至少部分由环形栅极（118）包围的聚合物通道（110）的装置的制造。还公开了一种具有通过围绕在第一（104）和第二（114）源极/漏极之间传导电流的沟道（110）的环形栅极（118）来控制（和/或扩大）电流的装置的系统。

6. 发明申请

WO2006036622A1 CONTROL OF MEMORY DEVICES POSSESSING VARIABLE RESISTANCE CHARACTERISTICS 审中-公开
标题翻译：控制可变电阻特性的存储器件
公开(公告)号：WO2006036622A1
公开(公告)日：2006-04-06
申请号：PCT/US2005/033379
申请日：2005-09-19
申请人： ADVANCED MICRO DEVICES, INC. , FANG, Tzu-Ning , VANBUSKIRK, Michael, A. , BILL, Colin, S.
发明人： FANG, Tzu-Ning , VANBUSKIRK, Michael, A. , BILL, Colin, S.
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C11/5664 , B82Y10/00 , G11C13/0014 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0078 , G11C2213/15 , G11C2213/79
摘要： Systems and methods employing at least one constant current source (114, 404) to facilitate programming of an organic memory cell (102, 302, 402, 904, 1102, 1206) and/or employing at least one constant voltage source (112, 304) to facilitate erasing of a memory device (200, 300, 400, 900, 1100). The present invention is utilized in single memory cell devices and memory cell arrays (100). Employing a constant current source (114, 404) prevents current spikes during programming and allows accurate control of a memory cell's (102, 302, 402, 904, 1102, 1206) state during write cycles, independent of the cell's resistance. Employing a constant voltage source (112, 304) provides a stable load for memory cells (102, 302, 402, 904, 1102, 1206) during erase cycles and allows for accurate voltage control across the memory cell (102, 302, 402, 904, 1102, 1206) despite large dynamic changes in cell resistance during the process.
摘要翻译：使用至少一个恒流源（114,404）的系统和方法来促进对有机存储器单元（102,302,402,904,1102,1206）的编程

7. 发明申请

WO2006124235A1 RESISTIVE MEMORY DEVICE WITH IMPROVED DATA RETENTION AND REDUCED POWER 审中-公开
标题翻译：具有改进的数据保持和降低功率的电阻式存储器件
公开(公告)号：WO2006124235A1
公开(公告)日：2006-11-23
申请号：PCT/US2006/016185
申请日：2006-04-26
申请人： SPANSION LLC , CHEN, An , HADDAD, Sameer , FANG, Tzu-Ning
发明人： CHEN, An , HADDAD, Sameer , FANG, Tzu-Ning
IPC分类号： G11C13/02
CPC分类号： G11C13/0009 , G11C13/0069 , G11C2013/009 , G11C2213/12 , G11C2213/15 , G11C2213/34 , G11C2213/56 , G11C2213/79
摘要： Provided herein is method of programming a resistive memory device (130, 230), the resistive memory device (130, 230) including a first electrode (132, 232), a second electrode (138, 236), and an active layer (136, 234) between the first and second electrodes (132, 138 or 232, 236). In the programming method, an electrical potential is applied across the first and second electrodes (132, 138 or 232, 236) so that electronic charge carriers enter the active layer (136, 234) and are held by traps therein. In erasing the memory device (130, 230), an electrical potential is applied across the first and second electrodes (132, 138 or 232, 236) so that electronic charge carriers are moved from the active layer (136, 234).
摘要翻译：本文提供了对电阻式存储器件（130,230）进行编程的方法，所述电阻式存储器件（130,230）包括第一电极（132,232），第二电极（138,236）和有源层（136），234）在第一和第二电极（132,138或232,236）之间。在编程方法中，跨越第一和第二电极（132,138或232,236）施加电势，使得电子载流子进入有源层（136,234）并由其中的陷阱保持。在擦除存储器件（130,230）时，跨越第一和第二电极（132,138或232,236）施加电势，使得电子载流子从有源层（136,234）移动。

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