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1. 发明申请

WO2006130438A1 PAGE BUFFER ARCHITECTURE FOR PROGRAMMING, ERASING AND READING NANOSCALE RESISTIVE MEMORY DEVICES 审中-公开
标题翻译：用于编程，擦除和读取纳米电阻存储器件的页面缓冲器架构
公开(公告)号：WO2006130438A1
公开(公告)日：2006-12-07
申请号：PCT/US2006/020326
申请日：2006-05-26
申请人： SPANSION LLC , BILL, Colin, S. , CAI, Wei, Daisy
发明人： BILL, Colin, S. , CAI, Wei, Daisy
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： G11C7/1051 , G11C7/106 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2013/0076 , G11C2013/0085 , G11C2207/2245
摘要： In the present method of programming and erasing the resistive memory devices (30) of an array thereof, upon a single command, high current is provided in both the program and erase functions to program and erase only those memory devices (30) whose state is to be changed from the previous state thereof.
摘要翻译：在目前的编程和擦除其阵列的电阻式存储器件（30）的方法中，通过单个命令，在编程和擦除功能中都提供高电流，以仅对那些状态为从之前的状态改变。

2. 发明申请

WO2006102391A2 TEMPERATURE COMPENSATION OF THIN FILM DIODE VOLTAGE THRESHOLD IN MEMORY SENSING CIRCUIT 审中-公开
标题翻译：记忆感应电路中薄膜二极管电压阈值的温度补偿
公开(公告)号：WO2006102391A2
公开(公告)日：2006-09-28
申请号：PCT/US2006010364
申请日：2006-03-22
申请人： SPANSION LLC , BILL COLIN S , CAI WEI DAISY
发明人： BILL COLIN S , CAI WEI DAISY
IPC分类号： G11C7/04 , G11C13/02
CPC分类号： G11C13/0016 , B82Y10/00 , G11C7/04 , G11C11/5664 , G11C13/00 , G11C13/0014 , G11C2213/72 , Y10S977/943
摘要： Systems and methodologies are provided for temperature compensation of thin film diode voltage levels in memory sensing circuits. The subject invention includes a temperature sensitive bias circuit (408) and an array core (500) with a temperature variable select device (430). The array core (500) can consist of a thin film diode (430) in series with a nanoscale resistive memory cell (440). The temperature sensitive bias circuit (600) can include a thin film diode (630) in series with two resistors (610, 620) and provides a temperature compensating bias voltage (640) to the array core. The thin film diode (630) of the temperature sensitive bias circuit (600) tracks the diode (430) of the array core (500), while the two resistors (610, 620) create a resistive ratio to mimic the effect of temperature and/or process variation(s) on the array core (500). The compensating bias reference voltage (640) is generated by the temperature sensitive bias circuit (600), duplicated by a differential amplifier (450), and utilized to maintain a constant operation voltage level on the nanoscale resistive memory cell (440).
摘要翻译：提供了用于存储器感测电路中的薄膜二极管电压电平的温度补偿的系统和方法。本发明包括具有温度可变选择装置（430）的温度敏感偏置电路（408）和阵列芯（500）。阵列芯（500）可以由与纳米级电阻式存储单元（440）串联的薄膜二极管（430）组成。温度敏感偏置电路（600）可以包括与两个电阻（610,620）串联的薄膜二极管（630），并向阵列芯提供温度补偿偏置电压（640）。温度敏感偏置电路（600）的薄膜二极管（630）跟踪阵列芯（500）的二极管（430），而两个电阻（610,620）产生电阻比以模拟温度的影响， /或阵列核心（500）上的过程变化。补偿偏置参考电压（640）由温度敏感偏置电路（600）产生，由差分放大器（450）复制，并用于在纳米级电阻存储单元（440）上维持恒定的工作电压电平。

3. 发明申请

WO2007015864A2 PROGRAM/ERASE WAVESHAPING CONTROL TO INCREASE DATA RETENTION OF A MEMORY CELL 审中-公开
标题翻译：程序/擦除波形控制以增加记忆体的数据保留
公开(公告)号：WO2007015864A2
公开(公告)日：2007-02-08
申请号：PCT/US2006027853
申请日：2006-07-17
申请人： SPANSION LLC , FANG TZU-NING , BILL COLIN S , CAI WEI DAISY , GAUN DAVID , GERSHON EUGENE
发明人： FANG TZU-NING , BILL COLIN S , CAI WEI DAISY , GAUN DAVID , GERSHON EUGENE
IPC分类号： G11C13/02
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0007 , G11C13/0016 , G11C13/004 , G11C13/0069 , G11C2013/0078 , G11C2013/0092 , G11C2213/32 , G11C2213/71 , G11C2213/77
摘要： System(s) and method(s) of improving and controlling memory cell data retention are disclosed. A particular pulse width and magnitude is generated and applied to a memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes. The current across the memory cell is detected and a lower input pulse is sent to the memory cell. Application of the lower pulse controls the data retention of the memory cell without disturbing the final programming state of the memory cell.
摘要翻译：公开了改进和控制存储单元数据保持的系统和方法。产生特定的脉冲宽度和幅度并将其施加到由至少两个电极制成的存储器单元，该至少两个电极在至少两个电极之间具有可控导电的介质。检测存储器单元中的电流，并将较低的输入脉冲发送到存储单元。下部脉冲的应用控制存储器单元的数据保持，而不会干扰存储单元的最终编程状态。

4. 发明申请

WO2007015864A3 PROGRAM/ERASE WAVESHAPING CONTROL TO INCREASE DATA RETENTION OF A MEMORY CELL 审中-公开
公开(公告)号：WO2007015864A3
公开(公告)日：2007-02-08
申请号：PCT/US2006/027853
申请日：2006-07-17
申请人： SPANSION LLC , FANG, Tzu-ning , BILL, Colin, S. , CAI, Wei, Daisy , GAUN, David , GERSHON, Eugene
发明人： FANG, Tzu-ning , BILL, Colin, S. , CAI, Wei, Daisy , GAUN, David , GERSHON, Eugene
IPC分类号： G11C13/02
摘要： System(s) and method(s) of improving and controlling memory cell data retention are disclosed. A particular pulse width and magnitude is generated and applied to a memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes. The current across the memory cell is detected and a lower input pulse is sent to the memory cell. Application of the lower pulse controls the data retention of the memory cell without disturbing the final programming state of the memory cell.

5. 发明申请

WO2006102391A3 TEMPERATURE COMPENSATION OF THIN FILM DIODE VOLTAGE THRESHOLD IN MEMORY SENSING CIRCUIT 审中-公开
公开(公告)号：WO2006102391A3
公开(公告)日：2006-09-28
申请号：PCT/US2006/010364
申请日：2006-03-22
申请人： SPANSION LLC , BILL, Colin, S. , CAI, Wei, Daisy
发明人： BILL, Colin, S. , CAI, Wei, Daisy
IPC分类号： G11C7/04 , G11C13/02
摘要： Systems and methodologies are provided for temperature compensation of thin film diode voltage levels in memory sensing circuits. The subject invention includes a temperature sensitive bias circuit (408) and an array core (500) with a temperature variable select device (430). The array core (500) can consist of a thin film diode (430) in series with a nanoscale resistive memory cell (440). The temperature sensitive bias circuit (600) can include a thin film diode (630) in series with two resistors (610, 620) and provides a temperature compensating bias voltage (640) to the array core. The thin film diode (630) of the temperature sensitive bias circuit (600) tracks the diode (430) of the array core (500), while the two resistors (610, 620) create a resistive ratio to mimic the effect of temperature and/or process variation(s) on the array core (500). The compensating bias reference voltage (640) is generated by the temperature sensitive bias circuit (600), duplicated by a differential amplifier (450), and utilized to maintain a constant operation voltage level on the nanoscale resistive memory cell (440).

6. 发明申请

WO2006055482A1 DIODE ARRAY ARCHITECTURE FOR ADDRESSING NANOSCALE RESISTIVE MEMORY ARRAYS 审中-公开
标题翻译：用于解决纳米电阻记忆阵列的二极体阵列
公开(公告)号：WO2006055482A1
公开(公告)日：2006-05-26
申请号：PCT/US2005/041173
申请日：2005-11-10
申请人： SPANSION LLC , TRIPSAS, Nicholas, H. , BILL, Colin, S. , VANBUSKIRK, Michael, A. , BUYNOSKI, Matthew , FANG, Tzu-Ning , CAI, Wei, Daisy , PANGRLE, Suzette, K. , AVANZINO, Steven
发明人： TRIPSAS, Nicholas, H. , BILL, Colin, S. , VANBUSKIRK, Michael, A. , BUYNOSKI, Matthew , FANG, Tzu-Ning , CAI, Wei, Daisy , PANGRLE, Suzette, K. , AVANZINO, Steven
IPC分类号： H01L27/10 , H01L27/102
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0007 , G11C2213/56 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/101 , H01L27/1021
摘要： The present memory structure includes thereof a first conductor (BL), a second conductor (WL), a resistive memory cell (130) connected to the second conductor (WL), a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL), and oriented in the forward direction from the resistive memory cell (130) to the first conductor (BL), and a second diode (132) connected to the resistive memory cell (130) and the first conductor (BL), in parallel with the first diode (134), and oriented in the reverse direction from the resistive memory cell (130) to the first conductor (BL). The first and second diodes (134, 132) have different threshold voltages.
摘要翻译：本存储器结构包括第一导体（BL），第二导体（WL），连接到第二导体（WL）的电阻性存储单元（130），连接到电阻式存储单元（130）的第一二极管）和第一导体（BL），并且从正向方向从电阻性存储单元（130）定向到第一导体（BL）;以及第二二极管（132），连接到电阻性存储单元（130）和第一导体（BL），与第一二极管（134）并联，并且从电阻式存储单元（130）到第一导体（BL）的反向定向。第一和第二二极管（134,132）具有不同的阈值电压。

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