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11. 发明申请

WO98041990A1 INTEGRATED CIRCUIT WITH A MEMORY AND A CONTROL CIRCUIT 审中-公开
标题翻译：具有存储器和测试电路的集成电路
公开(公告)号：WO98041990A1
公开(公告)日：1998-09-24
申请号：PCT/DE1998/000479
申请日：1998-02-17
IPC分类号： G11C29/12 , G11C29/48 , G11C29/00
CPC分类号： G11C29/48
摘要： According to the invention, the memory (2) can be controlled by a control circuit (3) and connected thereto via data lines (D1, D2), address lines (ADR) and control lines (RAS, CAS, OE), at least one of which travels through a switching device. Said switching device (L, G) can be controlled via an external connection (6, 7) of the integrated circuit (1), whereby the signal traveling through the corresponding line and the appropriate control time can be influenced. The invention is particularly suitable for carrying out self-testing on integrated memory cores.
摘要翻译：存储器（2）能够由所述检查电路（3）进行检查，并通过数据线（D1，D2），地址线ADR和控制线（RAS，CAS，OE）与其连接被连接时，其中一个通过开关至少表示执行。开关装置（L，G）通过外部连接而连接（6,7）（1）控制，使得在相应的线的波形，因此在测试的时序由外部影响集成电路的。本发明特别适合于实现集成存储器内核自检。

12. 发明申请

WO1998012707A1 METHOD AND APPARATUS FOR PROVIDING EXTERNAL ACCESS TO INTERNAL INTEGRATED CIRCUIT TEST CIRCUITS 审中-公开
标题翻译：提供外部接入内部集成电路测试电路的方法和装置
公开(公告)号：WO1998012707A1
公开(公告)日：1998-03-26
申请号：PCT/US1997016724
申请日：1997-09-18
申请人： MICRON TECHNOLOGY, INC.
发明人： MICRON TECHNOLOGY, INC. , ROBERTS, Gordon , MILER, James, E., Jr.
IPC分类号： G11C29/00
CPC分类号： G06F11/2733 , G06F11/2273 , G11C29/48
摘要： An integrated circuit includes an integrated circuit die mounted in a package having a plurality of externally accessible contacts. A functional circuit, such as a memory circuit, is formed on the integrated circuit die and is coupled through bonding pads to the external contacts of the integrated circuit. A test circuit is also formed on the integrated circuit die to allow performance parameters to be determined by performing tests on the test circuit when the test circuit is in wafer form before packaging. To allow tests to be performed on the test circuit after packaging, a switch circuit formed on the integrated circuit die selectively couples input/output terminals of the test circuit to respective bonding pads that are connected to the externally accessible contacts. The switch circuit is operated by a switch controller, which may be a decoder that responds to a pattern of signals or a sequence of signals applied to the externally accessible contacts or an overvoltage detector that responds to a voltage outside a range of operating voltages for the functional circuit.
摘要翻译：集成电路包括安装在具有多个外部可访问触点的封装中的集成电路管芯。诸如存储器电路的功能电路形成在集成电路管芯上，并且通过焊盘耦合到集成电路的外部触点。在集成电路管芯上还形成一个测试电路，以便在封装前测试电路处于晶圆形式时，通过对测试电路进行测试来确定性能参数。为了允许在封装之后在测试电路上执行测试，形成在集成电路管芯上的开关电路将测试电路的输入/输出端子选择性地耦合到连接到外部可访问触点的相应焊盘。开关电路由开关控制器操作，开关控制器可以是响应于施加到外部可触摸触点的信号模式或信号序列的解码器，或过电压检测器，其响应于工作电压范围外的电压，功能电路。

13. 发明申请

WO2015174594A1 테스트 기능을 구비한 반도체 회로 审中-公开
标题翻译：具有测试功能的半导体电路
公开(公告)号：WO2015174594A1
公开(公告)日：2015-11-19
申请号：PCT/KR2014/010781
申请日：2014-11-11
申请人： 주식회사 씨자인
发明人： 이수형
IPC分类号： G11C29/00 , G11C29/12
CPC分类号： G01R31/2644 , G11C29/00 , G11C29/12 , G11C29/1201 , G11C29/48
摘要： 테스트 기능을 구비한 반도체 회로는, 제 1 패드와 제 2 패드 사이에 전원을 인가하는 것에 의해 동작하고, 상기 반도체 회로의 주요 기능(Main Function)을 수행하는 회로를 포함하는 제 1 회로 블록; 상기 반도체 회로의 테스트 기능을 수행하는 회로를 포함하는 제 2 회로 블록; 및 상기 제 2 회로 블록과 직렬로 연결된 다이오드;를 포함한다. 테스트 기능을 구비한 반도체 회로에 따르면, 별도의 제어 패드 및 제어 신호를 필요로 하지 않아 패드 수를 감소시키는 것에 의해 반도체 칩 면적이 패드에 의해 증가하는 현상을 억제할 수 있다.
摘要翻译：具有测试功能的半导体电路包括：通过在第一焊盘和第二焊盘之间施加电力来操作的第一电路块，并且包括用于执行半导体电路的主要功能的电路; 第二电路块，包括用于执行半导体电路的测试功能的电路; 以及与第二电路块串联连接的二极管。根据具有测试功能的半导体电路，不需要单独的控制焊盘和控制信号，因此可以通过减少焊盘的数量来限制由于焊盘引起的半导体芯片面积的增加。

14. 发明申请

WO2012127177A1 CONFIGURATION MEMORY CELL 审中-公开
标题翻译：配置存储单元
公开(公告)号：WO2012127177A1
公开(公告)日：2012-09-27
申请号：PCT/GB2011/050543
申请日：2011-03-18
申请人： PANASONIC CORPORATION , STANSFIELD, Anthony
发明人： STANSFIELD, Anthony
IPC分类号： G11C29/12 , G11C29/48 , G11C8/16 , H03K19/177
CPC分类号： G11C29/12 , G11C8/16 , G11C11/41 , G11C29/1201 , G11C29/48 , G11C2029/0401 , H03K19/1776
摘要： A configuration memory for a programmable logic device (PLD) is described comprising a plurality of memory cells for a configuration memory of a programmable logic device (PLD) each memory cell comprising a storage element and first input means and second input means each being independently operable to provide access to the storage element. The second input means of at least one of the plurality of memory cells is arranged to receive control signals from a test interface for providing test signals to the PLD.
摘要翻译：描述了可编程逻辑器件（PLD）的配置存储器，其包括用于可编程逻辑器件（PLD）的配置存储器的多个存储器单元，每个存储器单元包括存储元件和第一输入装置，以及第二输入装置，每个存储器单元可独立操作以提供对存储元件的访问。多个存储器单元中的至少一个的第二输入装置被布置成从测试接口接收控制信号，以向PLD提供测试信号。

15. 发明申请

WO2008051932A2 HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE 审中-公开
标题翻译：高速双数据速率JTAG接口
公开(公告)号：WO2008051932A2
公开(公告)日：2008-05-02
申请号：PCT/US2007/082143
申请日：2007-10-22
申请人： TEXAS INSTRUMENTS INCORPORATED , WHETSEL, Lee, D.
发明人： WHETSEL, Lee, D.
IPC分类号： H03K19/0175
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/318544 , G01R31/318547 , G11C29/48
摘要： A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
摘要翻译：过程和装置使用减少的引脚数，高速DDR接口（202）提供JTAG TAP控制器（302）以访问设备的JTAG TAP域（106）。通过将来自TAP控制器的单独TDI和TMS信号组合成单个信号，并在驱动DDR接口的TCK的上升沿和下降沿传送单个信号的TDI和TMS信号，实现访问。 TAP域可以以点对点方式或以可寻址的总线方式耦合到TAP控制器。对TAP域的访问可以用于基于JTAG的设备测试，调试，编程或其他类型的基于JTAG的操作。

16. 发明申请

WO2007044286A3 MEMORY SCAN TESTING 审中-公开
标题翻译：内存扫描测试
公开(公告)号：WO2007044286A3
公开(公告)日：2007-08-30
申请号：PCT/US2006038354
申请日：2006-10-03
申请人： TEXAS INSTRUMENTS INC , GROSE WILLIAM E , LAMBERT LONNIE L , PITZ JEANNE KRAYER , TANAKA TORU
发明人： GROSE WILLIAM E , LAMBERT LONNIE L , PITZ JEANNE KRAYER , TANAKA TORU
IPC分类号： G01R31/28
CPC分类号： G11C29/12 , G11C16/04 , G11C29/48 , G11C2029/3202
摘要： A method is provided for testing a semiconductor device that includes both a digital (310) and analog (320) portion. The digital portion may include a plurality of latch devices (361-364), and the analog portion may include a plurality of memory cells (321) and a plurality of selector devices (325). Each of the plurality of selector devices is electrically coupled to a respective one of the memory cells, is at least indirectly coupled to one of the plurality of latch devices, and is controlled by a selector input (215). A load clock (372) is applied to load a pattern into the plurality of latch devices. The selector input is asserted such that a derivative of the pattern is received by the plurality of selectors and returned to the plurality of latch devices. A system clock (371) is applied to the plurality of latch devices such that the derivative of the pattern is loaded into the plurality of latch devices.
摘要翻译：提供了一种用于测试包括数字（310）和模拟（320）部分的半导体器件的方法。数字部分可以包括多个锁存装置（361-364），并且模拟部分可以包括多个存储器单元（321）和多个选择器装置（325）。多个选择器装置中的每一个电耦合到相应的一个存储单元，至少间接耦合到多个锁存装置中的一个，并由选择器输入端（215）控制。施加负载时钟（372）以将图案加载到多个闩锁装置中。选择器输入被断言，使得图案的导数被多个选择器接收并返回到多个锁存装置。系统时钟（371）被施加到多个锁存装置，使得图案的导数被加载到多个锁存装置中。

17. 发明申请

WO2007050608A2 TESTING AND RECOVERY IN A MULTILAYER DEVICE 审中-公开
标题翻译：多层设备中的测试和恢复
公开(公告)号：WO2007050608A2
公开(公告)日：2007-05-03
申请号：PCT/US2006041481
申请日：2006-10-23
申请人： INAPAC TECHNOLOGY INC , ONG ADRIAN , EGAN RICHARD
发明人： ONG ADRIAN , EGAN RICHARD
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/72
摘要： Disclosed are systems and methods of producing electronic devices including an auxiliary circuit mounted on another, underlying, circuit at the wafer level. The auxiliary circuit is electrically connected to the underlying circuit via micro-scale interconnects. The systems are capable of testing the auxiliary circuit and/or interconnects using an interface within the underlying circuit. For example, the auxiliary circuit may be tested although it is mounted such that the interconnects are hidden, i.e., inaccessible for testing purposes after assembly using conventional testing systems and methods. The systems and methods further allow for including excess circuits and/or excess interconnects that can be reconfigured to replace parts of the auxiliary circuit and/or micro-scale interconnects found defective during testing.
摘要翻译：公开了制造电子器件的系统和方法，其包括安装在晶片级的另一个下层电路上的辅助电路。辅助电路通过微尺度互连电连接到底层电路。该系统能够使用底层电路内的接口来测试辅助电路和/或互连。例如，可以对辅助电路进行测试，尽管它被安装成使得互连是隐藏的，即在使用常规测试系统和方法组装之后不能进行测试。这些系统和方法还允许包括可以被重新配置的多余电路和/或多余的互连以替代在测试期间发现有缺陷的辅助电路和/或微尺度互连的部分。

18. 发明申请

WO2005043276A3 SYSTEM-IN-PACKAGE AND METHOD OF TESTING THEREOF 审中-公开
标题翻译：系统级封装及其测试方法
公开(公告)号：WO2005043276A3
公开(公告)日：2006-06-01
申请号：PCT/IL2004000941
申请日：2004-10-13
申请人： MILSYS LTD , AVRAHAM MEIR
发明人： AVRAHAM MEIR
IPC分类号： G08C25/02 , G01R31/3185 , G06F20060101 , G11C29/00 , G11C29/48 , H04L1/18
CPC分类号： G11C29/48 , G01R31/318513 , G11C29/1201 , G11C2029/0401 , G11C2029/1208
摘要： A method of testing a SIP that has a CPU, a nonvolatile memory and a volatile memory. First, the CPU is used to test the memories. Then the CPU is tested separately. Preferably, the programs for testing the memories are pre-stored in and loaded from the nonvolatile memory into the volatile memory and are executed by the CPU in the volatile memory. Preferably, the test results are stored in the nonvolatile memory.
摘要翻译：一种测试具有CPU，非易失性存储器和易失性存储器的SIP的方法。首先，CPU用于测试记忆。然后分别测试CPU。优选地，用于测试存储器的程序预先存储在非易失性存储器中并从非易失性存储器加载到易失性存储器中，并且由易失性存储器中的CPU执行。优选地，将测试结果存储在非易失性存储器中。

19. 发明申请

WO2005017959A3 INTEGRATED CIRCUIT WITH TEST PAD STRUCTURE AND METHOD OF TESTING 审中-公开
标题翻译：具有测试垫结构的集成电路和测试方法
公开(公告)号：WO2005017959A3
公开(公告)日：2005-09-09
申请号：PCT/US2004022509
申请日：2004-07-15
申请人： FREESCALE SEMICONDUCTOR INC , TRAN TU-ANH , EGUCHI RICHARD K , HARPER PETER R , LEE CHU-CHUNG , WILLIAMS WILLIAM M , YONG LOIS
发明人： TRAN TU-ANH , EGUCHI RICHARD K , HARPER PETER R , LEE CHU-CHUNG , WILLIAMS WILLIAM M , YONG LOIS
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3187 , G11C29/48 , G01R31/02
CPC分类号： G11C29/1201 , G01R31/2884 , G01R31/31715 , G01R31/3187 , G11C29/48 , H01L2224/05554
摘要： A semiconductor device (10) has a large number of bond pads (24) on the periphery for wirebonding. The semiconductor device (10) has a module (12) as well as other circuitry, but the module (12) takes significantly longer to test than the other circuitry. A relatively small number of the bond pads (20), the module bond pads (20), are required for the module testing due, at least in part, to the semiconductor device having a built-in self-test (BIST) (16) circuitry. The functionality of these module bond pads (22) is duplicated on the top surface of and in the interior of the semiconductor device (10) with module test pads (22) that are significantly larger than the bond pads (24) on the periphery. Having large pads (22) for testing allows longer probe needles, thus increasing parallel testing capability. Duplicating the functionality is achieved through a test pad interface so that the module bond pads (20) and the module test pads (22) do not have to be shorted together.
摘要翻译：半导体器件（10）在外围具有大量的接合焊盘（24）用于引线接合。半导体器件（10）具有模块（12）以及其它电路，但是模块（12）需要比其他电路更长的测试时间。由于至少部分地由具有内置自检（BIST）的半导体器件（BIST）（16），模块测试所需的相对较少数量的接合焊盘（20），模块接合焊盘（20））电路。这些模块接合焊盘（22）的功能性被复制在半导体器件（10）的内表面上和在半导体器件（10）的内部，其中模块测试焊盘（22）明显大于外围的接合焊盘（24）。具有大的用于测试的焊盘（22）允许更长的探针，因此增加了并行测试能力。通过测试垫接口实现复制功能，使得模块接合焊盘（20）和模块测试焊盘（22）不必一起短路。

20. 发明申请

WO2004072660A3 COMPRESSING TEST RESPONSES USING A COMPACTOR 审中-公开
标题翻译：使用压缩机压缩测试响应
公开(公告)号：WO2004072660A3
公开(公告)日：2005-04-28
申请号：PCT/US2004004271
申请日：2004-02-13
申请人： MENTOR GRAPHICS CORP , RAJSKI JANUSZ , TYSZER JERZY , WANG CHEN , MRUGALSKI GRZEGORZ , POGIEL ARTUR
发明人： RAJSKI JANUSZ , TYSZER JERZY , WANG CHEN , MRUGALSKI GRZEGORZ , POGIEL ARTUR
IPC分类号： G01R31/3185 , G01R31/319 , G11C29/40 , G11C29/48 , G06F11/00 , G01R31/28
CPC分类号： G01R31/318566 , G01R31/31703 , G01R31/318536 , G01R31/318583 , G01R31/31921 , G11C29/40 , G11C29/48 , G11C2029/3202
摘要： The present disclosure describes embodiments of a compactor (706) for compressing test results in an integrated circuit (704) and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation ("EDA") software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.
摘要翻译：本公开描述了用于压缩集成电路（704）中的测试结果的压实器（706）的实施例以及用于使用和设计这些实施例的方法。所公开的压实机可以例如用作任何基于扫描的设计的一部分。此外，任何公开的压实机可以在诸如电子设计自动化（“EDA”）软件工具的计算机执行的应用中被设计，模拟和/或验证。还描述了在公开的压实机实施例中用于诊断故障的方法的实施例。

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