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1. 发明申请

WO2005111796A2 DEFECT LOCATION IDENTIFICATION FOR MICRODEVICE MANUFACTURING AND TEST 审中-公开
标题翻译：用于MICRODEVICE制造和测试的缺陷位置识别
公开(公告)号：WO2005111796A2
公开(公告)日：2005-11-24
申请号：PCT/US2005/016054
申请日：2005-05-09
申请人： MENTOR GRAPHICS CORPORATION , SAWICKI, Joseph, D. , FERGUSON, John, G. , DHAR, Sanjay , ROBLES, Juan, Andres, Torres , RAJSKI, Janusz, E.
发明人： SAWICKI, Joseph, D. , FERGUSON, John, G. , DHAR, Sanjay , ROBLES, Juan, Andres, Torres , RAJSKI, Janusz, E.
IPC分类号： G06F9/455
CPC分类号： G06F17/50 , G01R31/318357 , G06F11/263 , G06F2217/14 , G06F2217/74
摘要： A defect identification tool is disclosed that predicts locations at which defects in a microdevice are most likely to occur. The tool may identify both a type of defect and the particular netlists in which that defect is likely to occur. A test circuit generation tool can then subsequently use this defect information to generate a test circuit that tests for the defect in the identified portions of the microcircuit. Similarly, an automatic test pattern generation tool may use the defect location information to generate test data custom-tailored to check for faults corresponding to the identified defect in the specified portions of the microcircuit. Various implementations of the tool may be used both to identify the locations at which defects caused by systematic errors, such as manufacturing process deficiencies or flaws, are most likely to occur and the locations at which randomly-created defects are most likely to occur.
摘要翻译：公开了一种缺陷识别工具，其预测微型设备中最有可能发生缺陷的位置。该工具可以识别缺陷的类型和可能发生缺陷的特定网表。然后，测试电路生成工具随后可以使用该缺陷信息来生成测试电路，该测试电路测试微电路的识别部分中的缺陷。类似地，自动测试图形生成工具可以使用缺陷位置信息来生成定制的测试数据，以检查与微电路的指定部分中的所识别的缺陷相对应的故障。工具的各种实现可以用于识别由系统错误（诸如制造过程缺陷或缺陷）最可能发生的缺陷以及随机创建的缺陷最可能发生的位置的位置。

2. 发明申请

WO2004072660A2 COMPRESSING TEST RESPONSES USING A COMPACTOR 审中-公开
标题翻译：使用压缩机压缩测试响应
公开(公告)号：WO2004072660A2
公开(公告)日：2004-08-26
申请号：PCT/US2004/004271
申请日：2004-02-13
申请人： MENTOR GRAPHICS CORPORATION , RAJSKI, Janusz , TYSZER, Jerzy , WANG, Chen , MRUGALSKI, Grzegorz , POGIEL, Artur
发明人： RAJSKI, Janusz , TYSZER, Jerzy , WANG, Chen , MRUGALSKI, Grzegorz , POGIEL, Artur
IPC分类号： G01R
CPC分类号： G01R31/318566 , G01R31/31703 , G01R31/318536 , G01R31/318583 , G01R31/31921 , G11C29/40 , G11C29/48 , G11C2029/3202
摘要： The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation ("EDA") software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.
摘要翻译：本公开描述了用于压缩集成电路中的测试结果的压实机的实施例以及用于使用和设计这些实施例的方法。所公开的压实机可以用作例如任何基于扫描的设计的一部分。此外，任何公开的压实机可以在诸如电子设计自动化（“EDA”）软件工具的计算机执行的应用中被设计，模拟和/或验证。还描述了在公开的压实机实施例中用于诊断故障的方法的实施例。

3. 发明申请

WO2011116145A1 TEST SCHEDULING AND TEST ACCESS IN TEST COMPRESSION ENVIRONMENT 审中-公开
标题翻译：测试压缩环境中的测试调度和测试访问
公开(公告)号：WO2011116145A1
公开(公告)日：2011-09-22
申请号：PCT/US2011/028741
申请日：2011-03-16
申请人： MENTOR GRAPHICS CORPORATION , KASSAB, Mark, A. , GRZEGORZ, Mrugalski , MUKHERJEE, Nilanjan , RAJSKI, Janusz , JAKUB, Janicki , JERZY, Tyszer
发明人： KASSAB, Mark, A. , GRZEGORZ, Mrugalski , MUKHERJEE, Nilanjan , RAJSKI, Janusz , JAKUB, Janicki , JERZY, Tyszer
IPC分类号： G01R31/319
CPC分类号： G01R31/2834 , G01R31/2851 , G01R31/318335 , G01R31/318547 , G01R31/31921
摘要： Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.
摘要翻译：公开了测试压缩环境中用于测试调度和测试访问的方法，装置和系统的代表性实施例。基于包括压缩测试数据，对应的测试仪通道要求和相关核心的测试信息形成用于测试电路中的多个核心的测试模式的集群。测试模式集群的形成之后是测试者信道分配。可以采用最佳拟合方案或平衡拟合方案来产生信道分配信息。可以基于信道分配信息来设计用于动态信道分配的测试接入电路。

4. 发明申请

WO2005101222A3 COMPACTOR INDEPENDENT FAULT DIAGNOSIS 审中-公开
标题翻译：压力计独立故障诊断
公开(公告)号：WO2005101222A3
公开(公告)日：2006-07-20
申请号：PCT/US2005009579
申请日：2005-03-21
申请人： MENTOR GRAPHICS CORP , CHENG WU-TUNG , TSAI KUN-HAN , HUANG YU , TAMARAPALLI NAGESH , RAJSKI JANUSZ
发明人： CHENG WU-TUNG , TSAI KUN-HAN , HUANG YU , TAMARAPALLI NAGESH , RAJSKI JANUSZ
IPC分类号： G06F11/30 , G06F15/00
CPC分类号： G01R31/318547 , G06F11/267
摘要： Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In certain disclosed embodiments, methods for diagnosing faults from compressed test responses are provided. For example, in one exemplary embodiment, a circuit description of an at least partially scan-based circuit-under-test and a compactor for compacting test responses captured in the circuit-under-test is received. A transformation function performed by the compactor to the test responses captured in the circuit-under-test is determined. A diagnostic procedure for evaluating uncompressed test responses is modified into a modified diagnostic procedure that incorporates the transformation function therein. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computerreadable media comprising lists of fault candidates identified by any of the disclosed methods or circuit descriptions created or modified by the disclosed methods are provided.
摘要翻译：本文公开了用于执行故障诊断的方法，装置和系统。在某些公开的实施例中，提供了用于从压缩测试响应诊断故障的方法。例如，在一个示例性实施例中，接收至少部分基于扫描的测试电路和压实器的电路描述，用于压缩在待测电路中捕获的测试响应。确定由压实机对被测电路中捕获的测试响应执行的变换功能。用于评估未压缩测试响应的诊断程序被修改为并入其中的变换功能的修改的诊断过程。还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的计算机可读介质。同样地，提供了包括通过由公开的方法创建或修改的任何公开的方法或电路描述所识别的故障候选列表的计算机可读介质。

5. 发明申请

WO2006029284A2 INTEGRATED CIRCUIT YIELD AND QUALITY ANALYSIS METHODS AND SYSTEMS 审中-公开
标题翻译：集成电路和质量分析方法和系统
公开(公告)号：WO2006029284A2
公开(公告)日：2006-03-16
申请号：PCT/US2005/032040
申请日：2005-09-06
申请人： MENTOR GRAPHICS CORPORATION , RAJSKI, Janusz , CHEN, Gang , KEIM, Martin , TAMARAPALLI, Nagesh , TANG, Huaxing , SHARMA, Manish
发明人： RAJSKI, Janusz , CHEN, Gang , KEIM, Martin , TAMARAPALLI, Nagesh , TANG, Huaxing , SHARMA, Manish
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/2273 , G01R31/01 , G01R31/2846 , G01R31/2853 , G01R31/2894 , G01R31/31704 , G01R31/31835
摘要： Methods, apparatus, and systems for testing, analyzing, and improving integrated circuit yield and quality are disclosed herein. For example, in one exemplary embodiment, design defect extraction rules are derived at least partially from a set of design manufacturing rules. Potential defects are extracted from a representation of an integrated circuit layout using the design defect extraction rules. Circuit test stimuli applied during one or more circuit tests are determined. Test responses resulting from the applied circuit tests are evaluated to identify integrated circuits that fail and to identify the occurrence in the failing integrated circuits of one or more potential types of defects associated with the applied circuit tests. Information concerning the repetitive identification in the failing integrated circuits of the occurrence of potential types of defects is collected and analyzed to determine the likelihood of potential types of defects being present in integrated circuits manufactured in accordance with the layout.
摘要翻译：本文公开了用于测试，分析和提高集成电路产量和质量的方法，装置和系统。例如，在一个示例性实施例中，至少部分地从一组设计制造规则导出设计缺陷提取规则。使用设计缺陷提取规则从集成电路布局的表示中提取潜在缺陷。确定在一个或多个电路测试期间施加的电路测试刺激。评估由应用电路测试产生的测试响应，以识别故障的集成电路，并识别故障集成电路中与应用电路测试相关的一种或多种潜在类型的缺陷的发生。收集和分析关于发生潜在类型缺陷的故障集成电路中的重复识别的信息，以确定存在于根据布局制造的集成电路中的潜在类型的缺陷的可能性。

6. 发明申请

WO2012150970A1 TEST SCHEDULING WITH PATTERN-INDEPENDENT TEST ACCESS MECHANISM 审中-公开
标题翻译：具有独特的测试访问机制的测试调度
公开(公告)号：WO2012150970A1
公开(公告)日：2012-11-08
申请号：PCT/US2012/021575
申请日：2012-01-17
申请人： MENTOR GRAPHICS CORPORATION , RAJSKI, Janusz , KASSAB, Mark, A. , GRZEGORZ, Mrugalski , MUKHERJEE, Nilanjan , JANICKI, Jakub , TYSZER, Jerzy , DUTTA, Avijit
发明人： RAJSKI, Janusz , KASSAB, Mark, A. , GRZEGORZ, Mrugalski , MUKHERJEE, Nilanjan , JANICKI, Jakub , TYSZER, Jerzy , DUTTA, Avijit
IPC分类号： G06F11/263 , G01R31/3183 , G01R31/319 , G06F11/07 , G06F11/22
CPC分类号： H04L43/50 , G01R31/318335 , G06F11/263
摘要： Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling for testing a plurality of cores in a system on circuit. Test data are encoded to derive compressed test patterns that require small numbers of core input channels. Core input/output channel requirement information for each of the compressed test patterns is determined accordingly. The compressed patterns are grouped into test pattern classes. The formation of the test pattern classes is followed by allocation circuit input and output channels and test application time slots that may comprise merging complementary test pattern classes into clusters that can work with a particular test access mechanism. The test access mechanism may be designed independent of the test data.
摘要翻译：公开了用于在电路系统中测试多个核的测试调度的方法，装置和系统的代表性实施例。编码测试数据以导出需要少量核心输入通道的压缩测试模式。相应地确定每个压缩测试图案的核心输入/输出通道要求信息。压缩的模式被分组成测试模式类。测试模式类的形成之后是分配电路输入和输出通道以及测试应用时隙，其可以包括将互补测试模式类合并成可以与特定测试访问机制一起工作的集群。可以独立于测试数据设计测试访问机制。

7. 发明申请

WO2010124148A1 AT-SPEED SCAN TESTING WITH CONTROLLED SWITCHING ACTIVITY 审中-公开
标题翻译：具有控制切换活动的AT速度扫描测试
公开(公告)号：WO2010124148A1
公开(公告)日：2010-10-28
申请号：PCT/US2010/032136
申请日：2010-04-22
申请人： MENTOR GRAPHICS CORPORATION , RAJSKI, Janusz , MOGHADDAM, Elham, K. , MUKHERJEE, Nilanjan , KASSAB, Mark, A. , XIJIANG, Lin
发明人： RAJSKI, Janusz , MOGHADDAM, Elham, K. , MUKHERJEE, Nilanjan , KASSAB, Mark, A. , XIJIANG, Lin
IPC分类号： G01R31/3185
CPC分类号： G01R31/318547 , G01R31/318575
摘要： Test patterns for at-speed scan tests are generated by filling unspecified bits of test cubes with functional background data. Functional background data are scan cell values observed when switching activity of the circuit under test is near a steady state. Hardware implementations in EDT (embedded deterministic test) environment are also disclosed.
摘要翻译：通过用功能背景数据填充测试立方体的未指定位来生成速度扫描测试的测试模式。功能背景数据是当被测电路的开关活动接近稳定状态时观察到的扫描单元值。还公布了EDT（嵌入式确定性测试）环境中的硬件实现。

8. 发明申请

WO2010102235A1 FAULT DIAGNOSIS FOR NON-VOLATILE MEMORIES 审中-公开
标题翻译：故障诊断非易失性存储器
公开(公告)号：WO2010102235A1
公开(公告)日：2010-09-10
申请号：PCT/US2010/026403
申请日：2010-03-05
申请人： MENTOR GRAPHICS CORPORATION , MUKHERJEE, Nilanjan , POGIEL, Artur , RAJSKI, Janusz , TYSZER, Jerzy
发明人： MUKHERJEE, Nilanjan , POGIEL, Artur , RAJSKI, Janusz , TYSZER, Jerzy
IPC分类号： G11C29/20 , G11C29/40 , G11C29/56
CPC分类号： G11C29/40 , G11C16/04 , G11C17/14 , G11C29/20 , G11C29/56 , G11C29/56008 , G11C2029/0401 , G11C2029/1208 , G11C2029/5606
摘要： Fault diagnosis techniques for non-volatile memories are disclosed. The techniques are based on deterministic partitioning of rows and/or columns of cells in a memory array. Through deterministic partitioning, signatures are generated for identification of failing rows, columns and single memory cells. A row/column selector or a combined row and column selector may be built on chip to implement the process of deterministic partitioning. An optional shadow register may be used to transfer obtained signatures to an automated test equipment (ATE).
摘要翻译：公开了用于非易失性存储器的故障诊断技术。这些技术基于对存储器阵列中的单元格行和/或列的确定性划分。通过确定性分区，生成签名以识别失败的行，列和单个存储单元。行/列选择器或组合的行和列选择器可以构建在芯片上以实现确定性分区的过程。可以使用可选的影子寄存器将获得的签名转移到自动测试设备（ATE）。

9. 发明申请

WO2008100520A3 LOW POWER SCAN TESTING TECHNIQUES AND APPARATUS 审中-公开
标题翻译：低功耗扫描测试技术与设备
公开(公告)号：WO2008100520A3
公开(公告)日：2008-12-11
申请号：PCT/US2008001866
申请日：2008-02-12
申请人： MENTOR GRAPHICS CORP , LIN XIJIANG , CZYSZ DARIUSZ , KASSAB MARK , MRUGALSKI GRZEGORZ , RAJSKI JANUSZ , TYSZER JERZY
发明人： LIN XIJIANG , CZYSZ DARIUSZ , KASSAB MARK , MRUGALSKI GRZEGORZ , RAJSKI JANUSZ , TYSZER JERZY
IPC分类号： G06F11/00
CPC分类号： G01R31/318575
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures {e.g., an embedded deterministic test ("EDT") architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.
摘要翻译：下面公开了用于在集成电路测试期间降低功耗的方法，设备和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案并且可以与各种压缩硬件体系结构（例如，嵌入式确定性测试（“EDT”体系结构））集成。在所公开的实施例中，具有可编程测试激励选择器，可编程扫描使能电路，可编程时钟使能电路，可编程移位使能电路和/或可编程复位使能电路的集成电路。还公开了可以用于生成供任何所公开的实施例使用的测试模式的示例性测试模式生成方法。

10. 发明申请

WO2005111796A3 DEFECT LOCATION IDENTIFICATION FOR MICRODEVICE MANUFACTURING AND TEST 审中-公开
标题翻译：用于MICRODEVICE制造和测试的缺陷位置识别
公开(公告)号：WO2005111796A3
公开(公告)日：2007-04-12
申请号：PCT/US2005016054
申请日：2005-05-09
申请人： MENTOR GRAPHICS CORP , SAWICKI JOSEPH D , FERGUSON JOHN G , DHAR SANJAY , ROBLES JUAN ANDRES TORRES , RAJSKI JANUSZ E
发明人： SAWICKI JOSEPH D , FERGUSON JOHN G , DHAR SANJAY , ROBLES JUAN ANDRES TORRES , RAJSKI JANUSZ E
IPC分类号： G06F17/50 , G01R31/3183 , G06F9/455
CPC分类号： G06F17/50 , G01R31/318357 , G06F11/263 , G06F2217/14 , G06F2217/74
摘要： A defect identification tool is disclosed that predicts locations at which defects in a microdevice are most likely to occur (Fig. 6, #601). The tool may identify both a type of defect and the particular netlists in which that defect is likely to occur (Fig. 6, #603). A test circuit generation tool can then subsequently use this defect information to generate a test circuit that tests for the defect in the identified portions of the microcircuit (Fig. 6, #619). Similarly, an automatic test pattern generation tool may use the defect location information to generate test data custom-tailored to check for faults corresponding to the identified defect in the specified portions of the microcircuit. Various implementations of the tool may be used both to identify the locations at which defects caused by systematic errors, such as manufacturing process deficiencies or flaws, are most likely to occur and the locations at which randomly-created defects are most likely to occur.
摘要翻译：公开了一种缺陷识别工具，其预测微型设备中最有可能发生缺陷的位置（图6，＃601）。该工具可以识别缺陷的类型和可能发生缺陷的特定网表（图6，＃603）。然后，测试电路生成工具可以随后使用该缺陷信息来生成测试电路，以测试微电路的识别部分中的缺陷（图6，＃619）。类似地，自动测试图形生成工具可以使用缺陷位置信息来生成定制的测试数据，以检查与微电路的指定部分中的所识别的缺陷相对应的故障。工具的各种实现可以用于识别由系统错误（诸如制造过程缺陷或缺陷）最可能发生的缺陷以及随机创建的缺陷最可能发生的位置的位置。

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