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1. 发明申请

WO2014108740A1 ELECTRONIC DEVICE AND METHOD FOR STATE RETENTION 审中-公开
标题翻译：用于状态保持的电子设备和方法
公开(公告)号：WO2014108740A1
公开(公告)日：2014-07-17
申请号：PCT/IB2013/050178
申请日：2013-01-09
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , FLESHEL, Leonid , KUZMIN, Dan
发明人： PRIEL, Michael , FLESHEL, Leonid , KUZMIN, Dan
IPC分类号： G06F13/14 , G06F13/38
CPC分类号： G01R31/3177 , G01R31/318533 , G01R31/318536 , G01R31/318555 , G01R31/318558 , G01R31/318575 , G06F1/3243 , G06F1/3275 , G06F3/0625 , G06F3/064 , G06F3/0653 , G06F9/3869 , G06F11/1402 , G06F13/14 , G06F13/38 , G11C7/1036 , G11C19/28
摘要： An electronic device (10) comprising a set of two or more scan chains (C0, C1) and a memory unit (MEM) is described. Each of the scan chains (C0, C1) has an input end and an output end, which are opposite ends of the respective scan chain, and each of the scan chains (C0, C1, C2) comprises a sequence of stateful elements (F3, F2, F1, F0) connected in series between the input end and the output end, and each of the scan chains (C0, C1) is arranged to hold a string (ABCDEFGH; IJKLMN) having a length identical to the length of the respective scan chain (C0; C1), namely identical to the number of stateful elements of the chain. The strings of the scan chains (C0, C1 ) are shifted in parallel from the scan chains (C0, C1) into the memory unit (MEM) via the respective output ends in a store operation (S1— S8) and back from the memory unit (MEM) into the respective scan chains (C0, C1) via the respective input ends in a restore operation (S9—S16). The store operation and the restore operation each comprise at least NO elementary downstream shift operations. The set of scan chains (C0, C1) includes a short chain (C1) and a detour chain (C0; C1), wherein the short chain (C1) has a length N1 shorter than NO, and the electronic device (10) comprises a buffer chain (B1) with a length of K = N0 - N1, which has an input end and an output end, which are opposite ends of the buffer chain (B1), with the output end of the short chain (C0) connected or connectable to the input end of the buffer chain (B1 ) and the output end of the buffer chain (B1) connected or connectable to the memory unit (MEM). The buffer chain (B1) is provided at least partly by the detour chain (C0; C1). A method of operating the electronic device (10) is also proposed.
摘要翻译：描述了包括一组两个或更多个扫描链（C0，C1）和存储单元（MEM）的电子设备（10）。每个扫描链（C0，C1）具有作为相应扫描链的相对端的输入端和输出端，并且每个扫描链（C0，C1，C2）包括一系列有状态元件（F3 ，F2，F1，F0），并且每个扫描链（C0，C1）被布置成保持具有与所述输入端和输出端的长度相同的长度的串（ABCDEFGH; IJKLMN）相应的扫描链（C0; C1），即与链的有状态元素的数量相同。扫描链（C0，C1）的串在存储操作（S1- S8）中经由相应的输出端从扫描链（C0，C1）并行移位到存储单元（MEM）中并从存储器返回单元（MEM）在恢复操作中通过相应的输入端进入相应的扫描链（C0，C1）（S9-S16）。存储操作和恢复操作每个至少包括没有基本的下游移位操作。扫描链（C0，C1）组包括短链（C1）和绕行链（C0; C1），其中短链（C1）具有比NO短的长度N1，电子装置（10）包括具有长度为K = N0-N1的缓冲链（B1），其具有作为缓冲链（B1）的相对端的输入端和输出端，短链（C0）的输出端连接或可连接到缓冲链（B1）的输入端和连接或连接到存储器单元（MEM）的缓冲链（B1）的输出端。缓冲链（B1）至少部分地由迂回链（C0; C1）提供。还提出了一种操作电子设备（10）的方法。

2. 发明申请

WO2010083004A2 SYSTEMS AND METHODS OF IMPLEMENTING REMOTE BOUNDARY SCAN FEATURES 审中-公开
标题翻译：实现远程边界扫描特征的系统和方法
公开(公告)号：WO2010083004A2
公开(公告)日：2010-07-22
申请号：PCT/US2009/068666
申请日：2009-12-18
申请人： ELECTRONIC WARFARE ASSOCIATES, INC. , LA FEVER, George, B. , YELLIN, Carmy , FLAUM, Iser, B. , MUSE, David, R.
发明人： LA FEVER, George, B. , YELLIN, Carmy , FLAUM, Iser, B. , MUSE, David, R.
IPC分类号： G01R31/28 , G01R31/303
CPC分类号： G01R31/3177 , G01R31/3025 , G01R31/318536 , G01R31/318552 , G01R31/318555 , G01R31/318594 , G06F11/2294 , G06F21/10
摘要： A system and method for remotely performing boundary scans on a circuit board, device and/or system across a network. A first computing component, connected to the network, includes a computer readable media including computer executable instructions. The instructions cause the computing component to maintain or access a library of test scan procedures for a plurality of subject circuit boards. At least one of the test scan procedure is downloaded to a second computing component proximate the circuit board, device and/or system. The second computing component and the test scan procedure are monitored and controlled remotely via the network.
摘要翻译：一种用于跨越网络在电路板，设备和/或系统上远程执行边界扫描的系统和方法。连接到网络的第一计算组件包括包括计算机可执行指令的计算机可读介质。指令使计算组件维护或访问多个主题电路板的测试扫描程序库。至少一个测试扫描过程被下载到靠近电路板，设备和/或系统的第二计算部件。通过网络远程监控和控制第二计算组件和测试扫描过程。

3. 发明申请

WO2009059207A1 METHODS FOR ANALYZING SCAN CHAINS, AND FOR DETERMINING NUMBERS OR LOCATIONS OF HOLD TIME FAULTS IN SCAN CHAINS 审中-公开
标题翻译：用于分析扫描链的方法，以及用于确定扫描链中保持时间故障的数字或位置
公开(公告)号：WO2009059207A1
公开(公告)日：2009-05-07
申请号：PCT/US2008/082088
申请日：2008-10-31
申请人： INOVYS CORPORATION , CANNON, Stephen A. , DOKKEN, Richard C. , CROUCH, Alfred L. , WINBLAD, Gary A.
发明人： CANNON, Stephen A. , DOKKEN, Richard C. , CROUCH, Alfred L. , WINBLAD, Gary A.
IPC分类号： H03K19/00
CPC分类号： G01R31/318536
摘要： An environmental variable of a scan chain is set to a value believed to cause a hold time fault, and a pattern is shifted through the scan chain. The pattern has a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is the scan chain's length. The number of possible hold time faults in the scan chain is determined as a difference between i) a clock cycle when the at least one bit is expected to cause a transition at the scan chain's output, and ii) a clock cycle when the at least one bit actually causes a transition at the scan chain's output. If there is a value of the environmental variable at which the scan chain operates correctly, the location(s) of hold time faults can be determined.
摘要翻译：扫描链的环境变量被设置为被认为导致保持时间故障的值，并且图案被移动通过扫描链。该模式具有第一逻辑状态的至少n个连续位的后台模式，随后是第二逻辑状态的至少一位，其中n是扫描链的长度。扫描链中可能的保持时间故障的数量被确定为i）当预期至少一个位导致扫描链的输出处的转换时的时钟周期之间的差异，以及ii）当至少一个时钟周期一点实际上导致扫描链输出的转换。如果存在扫描链正确运行的环境变量的值，则可以确定保持时间故障的位置。

4. 发明申请

WO2008144167A1 BALANCING SCAN CHAINS AND INSERTING THE BALANCED-LENGTH SCAN CHAINS INTO HIERARCHICALLY DESIGNED INTEGRATED CIRCUITS 审中-公开
标题翻译：平衡扫描链，并将平衡长扫描链插入到高度设计的集成电路
公开(公告)号：WO2008144167A1
公开(公告)日：2008-11-27
申请号：PCT/US2008/061526
申请日：2008-04-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , LITTEN, David, D. , OAKLAND, Steven, F.
发明人： LITTEN, David, D. , OAKLAND, Steven, F.
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/318544
摘要： A system and methods of balancing scan chains and, more particularly, a system and methods of load balancing scan chains into hierarchically designed integrated circuits. The method includes estimating or calculating a maximum scan chain length L and creating a maximum number of scan chains of length L in each hierarchical block. The method further includes distributing remaining scan bits in each hierarchical block into additional scan chains, and creating chip-level scan chains by using the scan chains of maximum length L and by forming additional chip- level scan chains of maximum length L by distributing the additional scan chains of maximum length LR, plus any remaining top-level scan bits, among the additional chip-level scan chains of maximum length L.
摘要翻译：平衡扫描链的系统和方法，更具体地，将扫描链的负载平衡的系统和方法分层设计成集成电路。该方法包括估计或计算最大扫描链长度L并在每个分层块中产生长度为L的扫描链的最大数量。该方法还包括将每个分级块中的剩余扫描比特分配到另外的扫描链中，并且通过使用最大长度L的扫描链来创建码片级扫描链，并且通过分配附加的数据来形成附加的最大长度L的码片级扫描链在最大长度L的附加芯片级扫描链中的最大长度LR的扫描链以及任何剩余的顶级扫描位。

5. 发明申请

WO2007059025B1 METHOD AND SYSTEM FOR TESTING BACKPLANES UTILIZING A BOUNDARY SCAN PROTOCOL 审中-公开
标题翻译：利用边界扫描协议测试背板的方法和系统
公开(公告)号：WO2007059025B1
公开(公告)日：2007-11-08
申请号：PCT/US2006043973
申请日：2006-11-13
申请人： TELLABS OPERATIONS INC , GOVANI ATUL V , TALEN GERALD A
发明人： GOVANI ATUL V , TALEN GERALD A
IPC分类号： G01R31/3185
CPC分类号： G01R31/318508 , G01R31/318536
摘要： A system is provided for testing connectivity of a backplane having card slots with multiple nets in each card slot. The system includes a processor module that generates test vectors based on a net connectivity configuration for a predetermined backplane architecture. A master control card includes a card slot interconnect that is configured to be plugged into nets in the backplane. The master control card communicates over a serial interface with the processor module. The master control card receives the test vectors, associated with multiple card slots, over the serial interface. The master control card is configured to test the connectivity of the backplane based on the test vectors. Optionally, IOB test cards may be included that each have a card slot interconnect that is configured to be plugged into nets in a respective card slot of the backplane. The IOB test cards are joined in series with the master control card and with one another. Optionally, the test vectors may be defined based on an IEEE 1149.1 boundary scan test protocol.
摘要翻译：提供了一种用于测试具有在每个卡槽中具有多个网卡的卡槽的背板的连接性的系统。该系统包括处理器模块，其基于用于预定背板架构的网络连接配置来生成测试向量。主控卡包括卡插槽互连，该插槽互连被配置为插入背板中的网络。主控制卡通过串行接口与处理器模块进行通信。主控制卡通过串行接口接收与多个卡槽相关联的测试向量。主控卡配置为根据测试向量测试背板的连通性。可选地，可以包括IOB测试卡，每个IOB测试卡具有卡插槽互连，该卡插槽互连被配置为插入到背板的相应卡槽中的网络中。 IOB测试卡与主控制卡串联并相互连接。可选地，可以基于IEEE 1149.1边界扫描测试协议来定义测试向量。

6. 发明申请

WO2007100406A2 REDUCED PIN COUNT SCAN CHAIN IMPLEMENTATION 审中-公开
标题翻译：减少PIN码扫描链实现
公开(公告)号：WO2007100406A2
公开(公告)日：2007-09-07
申请号：PCT/US2006/061857
申请日：2006-12-11
申请人： TEXAS INSTRUMENTS INCORPORATED , DOORENBOS, Jerry, L. , TRIFONOV, Dimitar , GARDNER, Marco, A.
发明人： DOORENBOS, Jerry, L. , TRIFONOV, Dimitar , GARDNER, Marco, A.
CPC分类号： G01R31/318536 , G01R31/3172
摘要： The synchronous logic device with reduced pin count scan chain includes: more than two flip/flops (SDC0, SDC1, SDC2) coupled to form a shift register for receiving a scan data input signal (ScanDataIn); a combinational logic circuit (20) for receiving device inputs, generating flip/flop inputs for the more than two flip/flops, and generating an output signal; a first multiplexer (MUX10) for providing a clock signal to the more than two flip/flops during a test mode; a second multiplexer (MUX12) for selecting between a test mode output from the shift register and the output signal from the combinational logic circuit (20), and for providing a scan data output signal (ScanDataOut). In one embodiment, the scan data input signal and the scan data output signal share an input/output pin.
摘要翻译：具有减少引脚数扫描链的同步逻辑器件包括：多于两个触发器（SDC0，SDC1，SDC2）耦合以形成用于接收扫描数据输入信号（ScanDataIn）的移位寄存器; 用于接收设备输入的组合逻辑电路（20），为所述多于两个的触发器产生触发器/触发器输入，并产生输出信号; 用于在测试模式期间向多于两个触发器提供时钟信号的第一多路复用器（MUX10）第二多路复用器（MUX12），用于在从移位寄存器输出的测试模式与来自组合逻辑电路（20）的输出信号之间进行选择，以及用于提供扫描数据输出信号（ScanDataOut）。在一个实施例中，扫描数据输入信号和扫描数据输出信号共享输入/输出引脚。

7. 发明申请

WO2007092952A2 SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS 审中-公开
标题翻译：用于共享多个通信协议之间的通信链路的系统和方法
公开(公告)号：WO2007092952A2
公开(公告)日：2007-08-16
申请号：PCT/US2007/061922
申请日：2007-02-09
申请人： TEXAS INSTRUMENTS INCORPORATED , SWOBODA, Gary, L.
发明人： SWOBODA, Gary, L.
CPC分类号： G01R31/3177 , G01R31/31705 , G01R31/31723 , G01R31/31724 , G01R31/31727 , G01R31/318536 , G01R31/318544 , G01R31/318572
摘要： A system and method for sharing a communications link between multiple protocols is described that comprises a system comprising a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register (1108) that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.
摘要翻译：描述了用于共享多个协议之间的通信链路的系统和方法，其包括：系统，其包括被配置为使用多个协议中的至少一个与其他系统交换信息的通信接口; 协议选择寄存器（1108），其存储从所述多个协议之中选择协议以成为有效协议的值; 以及通信接口可访问的状态机，用于根据活动协议通过通信接口来控制信息交换的状态机。通信接口使用活动协议来交换信息，而多个协议的剩余协议保持不活动。状态机通过使通信接口根据活动协议进行操作的一系列状态进行排序，并在其余协议下被指定为惰性序列。

8. 发明申请

WO2006056951A1 INTEGRATED CIRCUIT SELF-TEST ARCHITECTURE 审中-公开
标题翻译：集成电路自检结构
公开(公告)号：WO2006056951A1
公开(公告)日：2006-06-01
申请号：PCT/IB2005/053883
申请日：2005-11-23
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PELGROM, Marcel , VEENDRICK, Hendricus, J., M.
发明人： PELGROM, Marcel , VEENDRICK, Hendricus, J., M.
IPC分类号： G01R31/3185 , G01R31/3167
CPC分类号： G01R31/318536 , G01R31/3167
摘要： An integrated circuit (1) comprises a monitor (Ml, M3, M3) operable to produce monitor data in dependence upon a measured parameter of the integrated circuit (1); and a self test controller (28) connected to receive monitor data from the monitor (Ml, M2, M3). The self-test controller is also operable to output self test data from the integrated circuit. The monitor includes an output shift register (SRl, SR2, SR3) and is operable to output monitor data through the shift register (SRl, SR2, SR3). Such a system enables simplified communication of system self test results on an integrated circuit.
摘要翻译：集成电路（1）包括可操作以根据集成电路（1）的测量参数产生监视数据的监视器（M1，M3，M3）; 以及连接以从监视器（M1，M2，M3）接收监视数据的自检控制器（28）。自检控制器还可以从集成电路输出自检数据。监视器包括输出移位寄存器（SR1，SR2，SR3），并且可操作以通过移位寄存器（SR1，SR2，SR3）输出监视数据。这样的系统能够简化集成电路系统自检结果的通信。

9. 发明申请

WO2005069025A1 JTAG TEST ARCHITECTURE FOR MULTI-CHIP PACK 审中-公开
标题翻译：用于多芯片包的JTAG测试架构
公开(公告)号：WO2005069025A1
公开(公告)日：2005-07-28
申请号：PCT/IB2005/000072
申请日：2005-01-05
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , TALAYSSAT, Jacky , BUWALDA, Sake
发明人： TALAYSSAT, Jacky , BUWALDA, Sake
IPC分类号： G01R31/3185
CPC分类号： G01R31/318558 , G01R31/318536
摘要： A test-communication path is provided between chips in a multi-chip package. Externally-accessible JTAG input and output pins are provided to a first chip in the multi-chip package, and this first chip is configured to allow signals received on these JTAG pins to be routed to other chips in the multi-chip package. Control signals provided to the first chip control the routing of the JTAG signals to each chip.
摘要翻译：在多芯片封装中的芯片之间提供测试通信路径。外部可访问的JTAG输入和输出引脚被提供给多芯片封装中的第一芯片，并且该第一芯片被配置为允许在这些JTAG引脚上接收的信号被路由到多芯片封装中的其他芯片。提供给第一芯片的控制信号控制JTAG信号到每个芯片的路由。

10. 发明申请

WO2004072660A3 COMPRESSING TEST RESPONSES USING A COMPACTOR 审中-公开
标题翻译：使用压缩机压缩测试响应
公开(公告)号：WO2004072660A3
公开(公告)日：2005-04-28
申请号：PCT/US2004004271
申请日：2004-02-13
申请人： MENTOR GRAPHICS CORP , RAJSKI JANUSZ , TYSZER JERZY , WANG CHEN , MRUGALSKI GRZEGORZ , POGIEL ARTUR
发明人： RAJSKI JANUSZ , TYSZER JERZY , WANG CHEN , MRUGALSKI GRZEGORZ , POGIEL ARTUR
IPC分类号： G01R31/3185 , G01R31/319 , G11C29/40 , G11C29/48 , G06F11/00 , G01R31/28
CPC分类号： G01R31/318566 , G01R31/31703 , G01R31/318536 , G01R31/318583 , G01R31/31921 , G11C29/40 , G11C29/48 , G11C2029/3202
摘要： The present disclosure describes embodiments of a compactor (706) for compressing test results in an integrated circuit (704) and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation ("EDA") software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.
摘要翻译：本公开描述了用于压缩集成电路（704）中的测试结果的压实器（706）的实施例以及用于使用和设计这些实施例的方法。所公开的压实机可以例如用作任何基于扫描的设计的一部分。此外，任何公开的压实机可以在诸如电子设计自动化（“EDA”）软件工具的计算机执行的应用中被设计，模拟和/或验证。还描述了在公开的压实机实施例中用于诊断故障的方法的实施例。

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