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1. 发明申请

WO2007044286A3 MEMORY SCAN TESTING 审中-公开
标题翻译：内存扫描测试
公开(公告)号：WO2007044286A3
公开(公告)日：2007-08-30
申请号：PCT/US2006038354
申请日：2006-10-03
申请人： TEXAS INSTRUMENTS INC , GROSE WILLIAM E , LAMBERT LONNIE L , PITZ JEANNE KRAYER , TANAKA TORU
发明人： GROSE WILLIAM E , LAMBERT LONNIE L , PITZ JEANNE KRAYER , TANAKA TORU
IPC分类号： G01R31/28
CPC分类号： G11C29/12 , G11C16/04 , G11C29/48 , G11C2029/3202
摘要： A method is provided for testing a semiconductor device that includes both a digital (310) and analog (320) portion. The digital portion may include a plurality of latch devices (361-364), and the analog portion may include a plurality of memory cells (321) and a plurality of selector devices (325). Each of the plurality of selector devices is electrically coupled to a respective one of the memory cells, is at least indirectly coupled to one of the plurality of latch devices, and is controlled by a selector input (215). A load clock (372) is applied to load a pattern into the plurality of latch devices. The selector input is asserted such that a derivative of the pattern is received by the plurality of selectors and returned to the plurality of latch devices. A system clock (371) is applied to the plurality of latch devices such that the derivative of the pattern is loaded into the plurality of latch devices.
摘要翻译：提供了一种用于测试包括数字（310）和模拟（320）部分的半导体器件的方法。数字部分可以包括多个锁存装置（361-364），并且模拟部分可以包括多个存储器单元（321）和多个选择器装置（325）。多个选择器装置中的每一个电耦合到相应的一个存储单元，至少间接耦合到多个锁存装置中的一个，并由选择器输入端（215）控制。施加负载时钟（372）以将图案加载到多个闩锁装置中。选择器输入被断言，使得图案的导数被多个选择器接收并返回到多个锁存装置。系统时钟（371）被施加到多个锁存装置，使得图案的导数被加载到多个锁存装置中。

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