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91. 发明申请

WO99060620A1 SEMICONDUCTOR DEVICE FABRICATION PROCESS 审中-公开
标题翻译：半导体器件制造工艺
公开(公告)号：WO99060620A1
公开(公告)日：1999-11-25
申请号：PCT/US1999/009392
申请日：1999-04-29
IPC分类号： H01L21/28 , H01L21/302 , H01L21/304 , H01L21/306 , H01L21/3065 , H01L21/311 , H01L21/336
CPC分类号： H01L21/0206 , H01L21/31116 , H01L21/31138 , H01L29/665 , H01L29/6656 , H01L29/66575
摘要： In a process for treating a semiconductor substrate (25), polymeric etchant deposits (190), silicon lattice damage (195), and native silicon dioxide layers (185), are removed in sequential process steps. The polymeric etchant deposits (190) are removed using an activated cleaning gas comprising inorganic fluorinated gas and an oxygen gas. Silicon lattice damage (195) are etched using an activated etching gas. Thereafter, an activated reducing gas comprising a hydrogen-containing gas is used to reduce the native silicon dioxide layer (185), on the substrate (25), to a silicon layer. Subsequently, a metal layer (200) is deposited on the substrate (25) and the substrate annealed to form a metal silicide layer (205). Removal of the polymeric etchant deposits (190), the silicon lattice damage (195), and the native silicon oxide layer (185) increases the interfacial conductivity of the metal silicide layer (205) to the underlying silicon-containing substrate (25).
摘要翻译：在处理半导体衬底（25）的方法中，在顺序的工艺步骤中去除聚合物蚀刻剂沉积物（190），硅晶格损伤（195）和天然二氧化硅层（185）。使用包含无机氟化气体和氧气的活性清洁气体除去聚合物蚀刻剂沉积物（190）。使用活化的蚀刻气体蚀刻硅晶格损伤（195）。此后，使用包含含氢气体的活化的还原气体将底物（25）上的天然二氧化硅层（185）还原成硅层。随后，在衬底（25）上沉积金属层（200），并且将衬底退火以形成金属硅化物层（205）。去除聚合物蚀刻剂沉积物（190），硅晶格损伤（195）和天然氧化硅层（185）增加金属硅化物层（205）与下面的含硅衬底（25）的界面导电性。

92. 发明申请

WO99035696A1 METHOD FOR PRODUCING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：生产半导体集成电路器件的方法
公开(公告)号：WO99035696A1
公开(公告)日：1999-07-15
申请号：PCT/JP1998/000058
申请日：1998-01-09
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/768 , H01L21/8238 , H01L29/78
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28052 , H01L21/76895 , H01L21/823835
摘要： A method for producing a semiconductor integrated circuit device having field effect transistors, comprising the step of forming a parent body layer having the shape of a gate electrode pattern made of a silicon film on the surface of a device formation area of a silicon substrate through a gate insulating film and then froming a pair of semiconductor areas as source and drain regions in a surface layer portion of the device formation area of the silicon substrate, the step of forming an amorphous layer by implanting ions of a Group IV element heavier than silicon into the surface layer portion of the parent body layer and into the surface layer portion of the semiconductor area, and the step of forming a high melting metal film on the surface of the silicon substrate inclusive of the surface of the amorphous layer, applying then the first heat-treatment to form a silicide layer, removing selectively the high melting metal film and thereafter applying the second heat-treatment to activate the silicide layer. Ion implantation of a Group IV element heavier than silicon is effected in an energy quantity such that the range of the implanted ion is greater than the thickness of the high melting metal film. Ion implantation of the Group IV element heavier than silicon is effected in a dose in the range of 1x10 [atoms/cm ] to 1x10 [atoms/cm ].
摘要翻译：一种具有场效应晶体管的半导体集成电路器件的制造方法，其特征在于，包括以下工序：在硅衬底的器件形成区域的表面上形成由硅膜形成的栅电极图案的母体层，栅极绝缘膜，然后从硅衬底的器件形成区域的表面层部分中的一对半导体区域作为源极和漏极区域，通过将比硅重的IV族元素的离子注入到非晶层中形成非晶层的步骤母体层的表层部分和半导体区域的表层部分，以及在包括非晶层的表面的硅衬底的表面上形成高熔点金属膜的步骤，然后施加第一热处理以形成硅化物层，选择性地除去高熔点金属膜，然后将第二热处理施加到活性物质上吃了硅化物层。离子注入比硅更重的IV族元素以能量的形式实现，使得注入离子的范围大于高熔点金属膜的厚度。比硅重的IV族元素的离子注入以1×10 14 [原子/ cm 2]至1×10 15 [原子/ cm 2]的剂量进行。

93. 发明申请

WO9853491A3 MANUFACTURE OF A SEMICONDUCTOR DEVICE WITH A MOS TRANSISTOR HAVING AN LDD STRUCTURE 审中-公开
标题翻译：具有LDD结构的MOS晶体管的半导体器件的制造
公开(公告)号：WO9853491A3
公开(公告)日：1999-02-25
申请号：PCT/IB9800633
申请日：1998-04-27
申请人： KONINKL PHILIPS ELECTRONICS NV , PHILIPS SVENSKA AB
发明人： SCHMITZ JURRIAAN , PONOMAREV YOURI V , WOERLEE PIERRE HERMANUS
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/2254 , H01L21/28247 , H01L21/823864 , H01L29/665 , Y10S438/923
摘要： A method of manufacturing a semiconductor device with a MOS transistor having an LDD structure. A gate dielectric (6) and a gate electrode (7, 8) are formed on a surface (5) of a silicon substrate (1). The surface adjacent the gate electrode is then exposed, and a layer of semiconductor material (10) is formed on an edge (9) of the surface adjoining the gate electrode. Ions (13, 14) are subsequently implanted, with the gate electrode and the layer of semiconductor material acting as a mask. Finally, a heat treatment is carried out whereby a source zone (16, 17) and a drain zone (18, 19) are formed through activation of the implanted ions and through diffusion of atoms of a dopant from the layer of semiconductor material. The portions (b) of these zones formed by diffusion are weakly doped here and lie between the more strongly doped portions (a) formed through activation of implanted ions and the channel zone (20, 21). An LDD structure has thus been formed. In the method, a layer of semiconductor material formed by Si1-xGex, with 0.1

94. 发明申请

WO1995006328A1 SELF-ALIGNED CMOS PROCESS 审中-公开
标题翻译：自对准CMOS工艺
公开(公告)号：WO1995006328A1
公开(公告)日：1995-03-02
申请号：PCT/US1994007181
申请日：1994-06-24
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： NATIONAL SEMICONDUCTOR CORPORATION , DEMIRLIOGLU, Esin, Kutlu , ARONOWITZ, Sheldon
IPC分类号： H01L21/225
CPC分类号： H01L29/66575 , H01L21/2254 , H01L21/823835 , H01L29/41783 , H01L29/456 , H01L29/4925 , H01L29/665 , H01L29/66545
摘要： A method for manufacturing CMOS semiconductor devices wherein damage to the active regions of the devices due to the direct implantation of impurities is suppressed. A material is selectively deposited on a semiconductor substrate, the material having a characteristic such that formation of the material occurs on some substances such as silicon and polysilicon, and formation of the material is suppressed on other substances such as silicon dioxide and silicon nitride. Impurities are introduced into the material rather than into the substrate. The impurities are then diffused into the active regions by standard processes such as rapid thermal anneal (RTA) or furnace anneal. The material generally contains germanium, and usually is a polycrystalline silicon-germanium alloy. The diffusion depth of the impurities may be controlled with great precision by manipulating several parameters. The parameters include the thickness of the material, the energy of the impurity implants, the density of the impurity implants, and the concentration of germanium in the material.
摘要翻译：制造CMOS半导体器件的方法，其中由于直接注入杂质而损坏器件的有源区被抑制。材料被选择性地沉积在半导体衬底上，该材料具有这样的特性，使得在诸如硅和多晶硅的某些物质上发生材料的形成，并且材料的形成被抑制在其它物质如二氧化硅和氮化硅上。杂质被引入材料而不是衬底中。然后通过诸如快速热退火（RTA）或炉退火的标准工艺将杂质扩散到活性区域。该材料通常含有锗，通常是多晶硅锗合金。可以通过操作几个参数以高精度控制杂质的扩散深度。参数包括材料的厚度，杂质植入物的能量，杂质植入物的密度以及材料中锗的浓度。

95. 发明申请

WO2017079307A1 SPLIT-GATE LATERAL EXTENDED DRAIN MOS TRANSISTOR STRUCTURE AND PROCESS 审中-公开
标题翻译：分裂栅延伸漏极MOS晶体管结构和工艺
公开(公告)号：WO2017079307A1
公开(公告)日：2017-05-11
申请号：PCT/US2016/060125
申请日：2016-11-02
申请人： TAXAS INSTRUMENTS INCORPORATED , TAXAS INSTRUMENTS JAPAN LIMITED
发明人： STRACHAN, Andrew, D. , SADOVNIKOV, Alexei , KOCON, Christopher, Boguslaw
IPC分类号： H01L29/78
CPC分类号： H01L21/28114 , H01L21/28158 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0696 , H01L29/0865 , H01L29/0882 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/42356 , H01L29/42368 , H01L29/42376 , H01L29/665 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7831 , H01L29/7835
摘要： In described examples, a semiconductor device (100) includes a split-gate lateral extended drain MOS transistor (108), which includes a first gate (128) and a second gate (130) laterally adjacent to the first gate (128). The first gate (128) is laterally separated from the second gate (130) by a gap (132) of 10 nanometers to 250 nanometers. The first gate (128) extends at least partially over a body (110), and the second gate (130) extends at least partially over a drain drift region (116). The drain drift region (116) abuts the body (110) at a top surface (112) of the substrate (102). A boundary between the drain drift region (116) and the body (110) at the top surface (112) of the substrate (102) is located under at least one of the first gate (128), the second gate (130) and the gap (132) between the first gate (128) and the second gate (130). The second gate (130) may be coupled to a gate bias voltage node or a gate signal node.
摘要翻译：在所述示例中，半导体器件（100）包括分离栅侧向延伸漏极MOS晶体管（108），所述分裂栅侧向延伸漏极MOS晶体管（108）包括第一栅极（128）和第二栅极（130）第一门（128）。第一栅极（128）与第二栅极（130）横向隔开10纳米至250纳米的间隙（132）。第一栅极（128）至少部分地在主体（110）上方延伸，并且第二栅极（130）至少部分地在漏极漂移区域（116）上方延伸。漏极漂移区（116）在衬底（102）的顶表面（112）处邻接本体（110）。在衬底（102）的顶表面（112）处的漏极漂移区（116）与主体（110）之间的边界位于第一栅极（128），第二栅极（130）和第一门（128）和第二门（130）之间的间隙（132）。第二栅极（130）可以耦合到栅极偏置电压节点或栅极信号节点。

96. 发明申请

WO2017024274A1 LOW COST FLASH MEMORY FABRICATION FLOW BASED ON METAL GATE PROCESS 审中-公开
标题翻译：基于金属门工艺的低成本闪存存储器制造流程
公开(公告)号：WO2017024274A1
公开(公告)日：2017-02-09
申请号：PCT/US2016/045895
申请日：2016-08-05
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： TAN, Ning , TIAN, Weidong
IPC分类号： H01L27/115 , H01L21/336 , H01L21/266
CPC分类号： H01L27/11521 , H01L21/26586 , H01L21/266 , H01L21/28008 , H01L21/28273 , H01L21/761 , H01L21/823412 , H01L21/823443 , H01L21/823456 , H01L21/823814 , H01L23/528 , H01L23/53228 , H01L27/1052 , H01L27/11526 , H01L27/11539 , H01L27/11541 , H01L27/11543 , H01L29/0847 , H01L29/42324 , H01L29/42328 , H01L29/45 , H01L29/4916 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/66825
摘要： In described examples, an integrated circuit (100) contains a flash cell (106) in which the top gate (136) of the sense transistor (108) is a metal sense gate (106) over the floating gate (130). The source/drain regions (138) of the sense transistor (108) extend under the floating gate (130) so that the source region is separated from the drain region by a sense channel length (126) less than 200 nanometers. The floating gate (130) is at least 400 nanometers wide, so the source/drain regions (138) of the sense transistor (108) extend under the floating gate (130) at least 100 nanometers on each side. The integrated circuit (100) is formed by forming the sense transistor source and drain regions (138) before forming the floating gate (130).
摘要翻译：在所描述的示例中，集成电路（100）包含闪存单元（106），其中感测晶体管（108）的顶栅极（136）是浮置栅极（130）上的金属感应栅极（106）。读出晶体管（108）的源极/漏极区域（138）在浮动栅极（130）下方延伸，使得源极区域与漏极区域分开小于200纳米的感测沟道长度（126）。浮动栅极（130）至少为400纳米宽，因此感测晶体管（108）的源极/漏极区域（138）在浮动栅极（130）下方在每一侧延伸至少100纳米。集成电路（100）通过在形成浮置栅极（130）之前形成读出晶体管源极和漏极区域（138）而形成。

97. 发明申请

WO2016179596A1 LOW-STRESS LOW-HYDROGEN LPCVD SILICON NITRIDE 审中-公开
标题翻译：低应力低氢LPCVD硅氮
公开(公告)号：WO2016179596A1
公开(公告)日：2016-11-10
申请号：PCT/US2016/031509
申请日：2016-05-09
申请人： TEXAS INSTRUMENTS INCOPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： DELLAS, Nicholas, Stephen
IPC分类号： H01L21/318 , C23C16/34 , H05K3/02
CPC分类号： H01L29/408 , B81B3/0072 , B81B2203/0118 , B81C1/00666 , B81C2201/0167 , H01L21/0217 , H01L21/02211 , H01L21/02271 , H01L21/3245 , H01L21/823864 , H01L23/291 , H01L29/2003 , H01L29/205 , H01L29/402 , H01L29/665 , H01L29/6659 , H01L29/778 , H01L29/7787
摘要： In described examples, a microelectronic device (102) contains a high performance silicon nitride layer, which is stoichiometric within 2 atomic percent, has a low stress of 600 MPa to 1000 MPa, and has a low hydrogen content, less than 5 atomic percent, formed by an LPCVD process. The LPCVD process uses ammonia NH3 and dichlorosilane DCS gases in a ratio of 4 to 6, at a pressure of 150 millitorr to 250 millitorr, and at a temperature of 800°C to 820°C.
摘要翻译：在所述实施例中，微电子器件（102）包含化学计量在2原子％以内的高性能氮化硅层，具有600MPa〜1000MPa的低应力，低于5原子％的氢含量，由LPCVD过程形成。 LPCVD方法使用氨的NH 3和二氯硅烷DCS气体，其比例为4至6，压力为150毫托，250毫托，温度为800℃至820℃。

98. 发明申请

WO2016088196A1 半導体装置の製造方法および半導体装置审中-公开
标题翻译：用于生产半导体器件和半导体器件的方法
公开(公告)号：WO2016088196A1
公开(公告)日：2016-06-09
申请号：PCT/JP2014/081839
申请日：2014-12-02
申请人：ルネサスエレクトロニクス株式会社
发明人：山口　直
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L29/7845 , H01L21/28518 , H01L21/28568 , H01L27/115 , H01L27/11568 , H01L27/11573 , H01L28/00 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66545
摘要：　ＭＯＮＯＳメモリのゲート電極上のシリサイド層が断線することを防ぎ、かつ、ＭＩＳＦＥＴの特性を向上させる。その手段として、メモリセルと、いわゆるゲートラストプロセスにより形成されるＭＩＳＦＥＴとを混載する場合に、比較的高い温度の熱処理を伴うサリサイドプロセスによりソース・ドレイン領域上のシリサイド層を形成した後、メモリセルの制御ゲート電極およびメモリゲート電極のそれぞれの上に、比較的低い温度の熱処理を伴うサリサイドプロセスによりシリサイド層を形成する。
摘要翻译：本发明改进了MISFET特性，并且防止了MONOS存储器的栅电极上的硅化物层的断开。作为这样做的手段，当共同安装通过所谓的最后工艺形成的存储单元和MISFET时，通过进行相对高温热处理的自对准硅化物工艺在源极 - 漏极区域上形成硅化物层之后，通过进行相对低温热处理的自对准硅化物处理，在存储单元的存储栅电极和控制栅电极的顶部形成硅化物层。

99. 发明申请

WO2016058324A1 低温多晶硅薄膜晶体管及制作方法、阵列基板、显示装置审中-公开
公开(公告)号：WO2016058324A1
公开(公告)日：2016-04-21
申请号：PCT/CN2015/074489
申请日：2015-03-18
申请人：京东方科技集团股份有限公司
发明人：陆小勇 , 刘政 , 孙亮 , 李小龙 , 龙春平
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/78618 , H01L21/28518 , H01L21/28568 , H01L27/1222 , H01L27/1274 , H01L29/458 , H01L29/665 , H01L29/66757 , H01L29/78675 , H01L29/78696
摘要：一种低温多晶硅薄膜晶体管及制作方法、阵列基板和显示装置，该低温多晶硅薄膜晶体管的制作方法包括：S1：在衬底基板（1）上依次形成有源层（3）、栅极绝缘层（4）、栅极（5）以及层间绝缘层（6）；S2：形成第一金属薄膜层（8）；S3：对所述有源层（3）和栅极绝缘层（6）进行氢化处理；S4：形成第二金属薄膜层（7），所述第二金属薄膜层（7）用于形成源极和漏极。

100. 发明申请

WO2015089450A1 FORMING SILICIDE AND CONTACT AT EMBEDDED EPITAXIAL FACET 审中-公开
标题翻译：形成硅胶并与嵌入式外墙面接触
公开(公告)号：WO2015089450A1
公开(公告)日：2015-06-18
申请号：PCT/US2014/070111
申请日：2014-12-12
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： LIM, Kwan-Yong , BLATCHFORD, James, Walter , EKBOTE, Shashank, S. , CHOI, Younsung
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/092 , H01L21/76897 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L23/535 , H01L29/0847 , H01L29/4175 , H01L29/665 , H01L29/66636
摘要： In described examples, an integrated circuit (100) is formed with an MOS transistor (108) abutting field oxide (106) and a gate structure (110) on the field oxide (106) adjacent to the MOS transistor (108). A gap (146) between an epitaxial source/drain (124) and the field oxide (106) is formed with a silicon dioxide-based gap filler (148) in the gap (146). Metal silicide (150) is formed on the exposed epitaxial source/drain region (124). A CESL (152) is formed over the integrated circuit (100), and a PMD layer (154) is formed over the CESL (152). A contact (156) is formed through the PMD layer (154) and CESL (152) to make an electrical connection to the metal silicide (150) on the epitaxial source/drain region (124).
摘要翻译：在所述实施例中，集成电路（100）形成有与氧化物（106）邻接的MOS晶体管（108）和与MOS晶体管（108）相邻的场氧化物（106）上的栅极结构（110）。外延源/漏极（124）和场氧化物（106）之间的间隙（146）在间隙（146）中形成有二氧化硅基间隙填料（148）。金属硅化物（150）形成在暴露的外延源极/漏极区（124）上。 CESL（152）形成在集成电路（100）上，并且在CESL（152）上形成PMD层（154）。通过PMD层（154）和CESL（152）形成触点（156）以与外延源极/漏极区域（124）上的金属硅化物（150）形成电连接。

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