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1. 发明授权

US07157951B1 Digital clock manager capacitive trim unit 有权
标题翻译：数字时钟管理器电容调整单元
公开(公告)号：US07157951B1
公开(公告)日：2007-01-02
申请号：US10837186
申请日：2004-04-30
申请人： Shawn K. Morrison , Raymond C. Pang
发明人： Shawn K. Morrison , Raymond C. Pang
IPC分类号： H03H11/26
CPC分类号： H03K5/15013 , G06F1/10
摘要： A delay line for a digital clock manager includes a tap delay structure and a trim delay structure. The trim delay structure includes a first buffer coupled to receive a clock signal from the tap delay structure, and in response, provide a delayed clock signal to a set of clock lines. The trim delay structure also includes a capacitive trim unit having a plurality of capacitive trim elements tapped off the set of clock lines. The capacitive trim elements are selectively enabled or disabled, thereby introducing additional delay to the delayed clock signal on the set of clock lines. Each capacitive trim element can include a transmission gate structure, which is turned on to introduce significant junction capacitance to the set of clock lines. The trim delay structure can also include a second buffer adapted to buffer the delayed clock signal on the set of clock lines.
摘要翻译：数字时钟管理器的延迟线包括抽头延迟结构和修整延迟结构。修剪延迟结构包括第一缓冲器，其被耦合以从抽头延迟结构接收时钟信号，并且作为响应，向一组时钟线提供延迟的时钟信号。修剪延迟结构还包括电容修剪单元，其具有从该组时钟线分离的多个电容修剪元件。电容调整元件被选择性地使能或禁止，从而对该组时钟线上的延迟的时钟信号引入额外的延迟。每个电容调整元件可以包括传输门结构，其被导通以将显着的结电容引入该组时钟线。修剪延迟结构还可以包括适于缓冲该组时钟线上延迟的时钟信号的第二缓冲器。

2. 发明授权

US07515452B1 Interleaved memory cell with single-event-upset tolerance 有权
标题翻译：具有单事件不正常容限的交错记忆单元
公开(公告)号：US07515452B1
公开(公告)日：2009-04-07
申请号：US11649447
申请日：2007-01-03
申请人： Jan L. de Jong , Susan Xuan Nguyen , Raymond C. Pang
发明人： Jan L. de Jong , Susan Xuan Nguyen , Raymond C. Pang
IPC分类号： G11C11/00
CPC分类号： G11C8/04 , H03K19/00392 , H03K19/1776 , H03K19/17764 , H03K19/1778
摘要： A memory array has a first memory cell with a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value. A first portion of the plurality of transistors is in a first cell portion and a second portion of the plurality of transistors is in a second cell portion. A second memory cell has a third cell portion and a fourth cell portion. The third cell portion is between the first cell portion and the second cell portion and adjacent to each of the first cell portion and the second cell portion. In a particular embodiment, the memory cell is a single-event-upset (“SEU”) tolerant memory cell and the first and second cell portions are each a half cell of a sixteen transistor memory cell.
摘要翻译：存储器阵列具有连接有多个晶体管的第一存储器单元，以便在事件颠倒初始值之后将数据值恢复到存储器单元的节点到初始值。多个晶体管的第一部分在第一单元部分中，并且多个晶体管的第二部分在第二单元部分中。第二存储单元具有第三单元部分和第四单元部分。第三单元部分在第一单元部分和第二单元部分之间并且与第一单元部分和第二单元部分中的每一个相邻。在特定实施例中，存储器单元是单事件不正常（“SEU”）容限存储器单元，并且第一和第二单元部分各自是十六晶体管存储单元的半单元。

3. 发明授权

US07402443B1 Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes 有权
标题翻译：使用产品选择代码为集成电路系列提供类似模具的方法部分禁用
公开(公告)号：US07402443B1
公开(公告)日：2008-07-22
申请号：US11333819
申请日：2006-01-17
申请人： Raymond C. Pang , Trevor J. Bauer , F. Erich Goetting , Bruce E. Talley , Steven P. Young
发明人： Raymond C. Pang , Trevor J. Bauer , F. Erich Goetting , Bruce E. Talley , Steven P. Young
IPC分类号： G01R31/26
CPC分类号： H01L27/11807 , H01L27/0207
摘要： A method of providing a family of integrated circuits (ICs) includes applying a first product selection code (PSC) to a first IC die, applying a second PSC to a second IC die, and providing a third packaged IC die. The first IC die includes first and second portions, both of which are operational based on the first PSC. The second IC die is a duplicate of the first die, but the second portion is rendered non-operational by the second PSC. The third IC die is substantially similar to the first portion of the first die. The second and third packages can be the same and the packaged dies can be interchangeable in a system. When the dies are programmable logic device (PLD) dies, the second and third dies use the same configuration bit stream, which may be smaller than the configuration bit stream for the first IC die.
摘要翻译：提供集成电路（IC）系列的方法包括：将第一产品选择代码（PSC）应用于第一IC芯片，将第二PSC应用于第二IC芯片，以及提供第三封装IC芯片。第一IC芯片包括第一和第二部分，它们都基于第一PSC而可操作。第二IC芯片是第一裸片的副本，但是第二部分由第二PSC不可操作。第三IC管芯基本上类似于第一管芯的第一部分。第二和第三包可以是相同的，并且包装的模具可以在系统中互换。当管芯是可编程逻辑器件（PLD）管芯时，第二和第三管芯使用与第一IC管芯的配置位流相同的配置位流。

4. 发明授权

US06981153B1 Programmable logic device with method of preventing readback 有权
标题翻译：可编程逻辑器件，具有防止回读的方法
公开(公告)号：US06981153B1
公开(公告)日：2005-12-27
申请号：US09724975
申请日：2000-11-28
申请人： Raymond C. Pang , Walter N. Sze , John M. Thendean , Stephen M. Trimberger , Jennifer Wong
发明人： Raymond C. Pang , Walter N. Sze , John M. Thendean , Stephen M. Trimberger , Jennifer Wong
IPC分类号： H03K19/173 , G06F17/50 , G06F21/00 , G09C1/00 , H04L9/10 , G06F12/14
CPC分类号： H04N21/23476 , G06F17/5054 , G06F21/76
摘要： It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, the design may be encrypted as it is read into the PLD and decrypted within the PLD before being loaded into configuration memory cells for configuring the PLD. According to the invention, in such a device, a method is provided to prevent the design from being read back from the PLD in its decrypted state if it had been encrypted when loaded into the PLD.
摘要翻译：有时期望保护PLD中使用的设计不被复制。如果设计存储在与PLD不同的设备中并且通过比特流读入PLD，则在加载到用于配置PLD的配置存储器单元之前，设计可以在PLD中被读入PLD并被解密并被解密。根据本发明，在这种设备中，提供了一种方法，用于防止在被加载到PLD中时将设计从PLD解密的状态下读回PLD。

5. 发明授权

US06282127B1 Block RAM with reset to user selected value 有权
标题翻译：将RAM重置为用户选择的值
公开(公告)号：US06282127B1
公开(公告)日：2001-08-28
申请号：US09625672
申请日：2000-07-24
申请人： Raymond C. Pang , Steven P. Young , Trevor J. Bauer
发明人： Raymond C. Pang , Steven P. Young , Trevor J. Bauer
IPC分类号： G11C700
CPC分类号： G11C7/1051 , G11C7/1057
摘要： A RAM block includes a circuit for causing the RAM to provide a reset value on the output or a previously captured output value from the RAM when a Reset signal is active. The Reset signal does not change the RAM contents but causes all outputs of the block RAM to be either a reset value or a capture value, as selected by the user. This is useful when the RAM block is configured as a state machine. Thus, in an FPGA or other programmable device, an application can start the state machine in a known state with all address bits equal to 0 and can reset the state machine to this startup state. When the reset signal is active, the state machine can feed back the reset value or capture value to the address inputs of the RAM block that receive state feedback data, regardless of the data actually in those locations.
摘要翻译： RAM块包括用于当复位信号有效时使RAM在输出上提供复位值或从RAM提供先前捕获的输出值的电路。复位信号不会更改RAM内容，但会导致块RAM的所有输出为用户选择的复位值或捕捉值。当RAM块被配置为状态机时，这是有用的。因此，在FPGA或其他可编程器件中，应用程序可以在所有地址位等于0的已知状态下启动状态机，并可将状态机复位到该启动状态。当复位信号有效时，状态机可以将接收状态反馈数据的复位值或捕获值反馈给RAM块的地址输入，无论这些位置中的数据如何。

6. 发明授权

US07501879B1 eFuse resistance sensing scheme with improved accuracy 有权
标题翻译： eFuse电阻传感方案具有提高的精度
公开(公告)号：US07501879B1
公开(公告)日：2009-03-10
申请号：US11717836
申请日：2007-03-13
申请人： Kwansuhk Oh , Raymond C. Pang , Hsung Jai Im , Sunhom Paak
发明人： Kwansuhk Oh , Raymond C. Pang , Hsung Jai Im , Sunhom Paak
IPC分类号： G11C17/18 , H01H85/00
CPC分类号： G11C17/16 , G11C17/18
摘要： An eFuse sensing circuit replaces the inverters used to provide the “read” output state of a conventional eFuse circuit. The sensing circuit includes a comparator with one input coupled to the eFuse circuitry, and a second input coupled to a reference voltage generator circuit. The reference voltage generator circuit includes an internal resistor. Transistors of the sense circuit are provided to mimic the transistors of the eFuse circuit, so that variations of transistors due to process, voltage and temperature will be substantially the same. The resistor of the sense circuit is then effectively compared with the resistance of the eFuse by the comparator irrespective of temperature and process variations.
摘要翻译： eFuse感测电路取代了用于提供常规eFuse电路的“读取”输出状态的逆变器。感测电路包括具有耦合到eFuse电路的一个输入和耦合到参考电压发生器电路的第二输入的比较器。参考电压发生器电路包括内部电阻器。提供感测电路的晶体管以模拟eFuse电路的晶体管，使得由于工艺，电压和温度而导致的晶体管的变化将基本相同。然后将感测电路的电阻与比较器的eFuse的电阻进行有效的比较，而与温度和工艺变化无关。

7. 发明授权

US07242633B1 Memory device and method of transferring data in memory device 有权
标题翻译：存储器件和在存储器件中传送数据的方法
公开(公告)号：US07242633B1
公开(公告)日：2007-07-10
申请号：US11044740
申请日：2005-01-26
申请人： Alvin Y. Ching , Raymond C. Pang , Steven P. Young , Thanh Pham
发明人： Alvin Y. Ching , Raymond C. Pang , Steven P. Young , Thanh Pham
IPC分类号： G11C8/00
CPC分类号： H03K19/1776 , G11C7/1075 , G11C8/10 , G11C8/16 , G11C11/412 , G11C11/413 , G11C15/00
摘要： According to one aspect of the invention, a circuit for accessing data in a memory is disclosed. The circuit generally comprises a first port having a read logic circuit and a first output which generates data from the memory. A second port has a read logic circuit and a write logic circuit. A second output is coupled to the second port, and also generates data from the memory. Circuits for separately selecting read and write widths for a port of a memory, such as a random access memory, are disclosed. Finally, other embodiments related to implementing a content addressable memory in a programmable logic device are disclosed. Further, a method of accessing data in a memory is disclosed.
摘要翻译：根据本发明的一个方面，公开了一种用于访问存储器中的数据的电路。电路通常包括具有读逻辑电路的第一端口和从存储器产生数据的第一输出。第二端口具有读逻辑电路和写逻辑电路。第二输出耦合到第二端口，并且还从存储器产生数据。公开了用于单独选择存储器的端口（例如随机存取存储器）的读取和写入宽度的电路。最后，公开了在可编程逻辑器件中实现内容可寻址存储器的其它实施例。此外，公开了一种访问存储器中的数据的方法。

8. 发明授权

US07038519B1 Digital clock manager having cascade voltage switch logic clock paths 有权
标题翻译：数字时钟管理器具有级联电压开关逻辑时钟路径
公开(公告)号：US07038519B1
公开(公告)日：2006-05-02
申请号：US10837324
申请日：2004-04-30
申请人： Raymond C. Pang , Jennifer Wong
发明人： Raymond C. Pang , Jennifer Wong
IPC分类号： H03H11/26
CPC分类号： H03K19/1738 , H03H11/26 , H03K2005/00195 , H03K2005/00228 , H03K2005/00234
摘要： A digital clock manager having differential clock signal paths is provided. The differential clock signal paths are provided by replacing single-ended circuit elements of a conventional digital clock manager with symmetrical cascade voltage switch logic (CVSL) circuit elements, including CVSL delay buffers, CVSL multiplexers, CVSL AND gates, CVSL OR gates and CVSL set-reset latches. These symmetrical CVSL AND gates, CVSL OR gates and CVSL set-reset latches represent new circuit elements.
摘要翻译：提供具有差分时钟信号路径的数字时钟管理器。差分时钟信号路径通过用传统数字时钟管理器的单端电路元件替代对称级联电压开关逻辑（CVSL）电路元件来提供，包括CVSL延迟缓冲器，CVSL多路复用器，CVSL与门，CVSL或门和CVSL组 - 锁存器。这些对称的CVSL与门，CVSL或门和CVSL设置复位锁存器代表新的电路元件。

9. 发明授权

US06441641B1 Programmable logic device with partial battery backup 有权
标题翻译：具有部分电池备份的可编程逻辑器件
公开(公告)号：US06441641B1
公开(公告)日：2002-08-27
申请号：US09724735
申请日：2000-11-28
申请人： Raymond C. Pang , Venu M. Kondapalli , Jane W. Sowards , Scott O. Frake , Jennifer Wong , F. Erich Goetting , Peter H. Alfke , Schuyler E. Shimanek
发明人： Raymond C. Pang , Venu M. Kondapalli , Jane W. Sowards , Scott O. Frake , Jennifer Wong , F. Erich Goetting , Peter H. Alfke , Schuyler E. Shimanek
IPC分类号： H01L2500
CPC分类号： G06F21/76
摘要： A PLD can be manufactured to include power supply lines from two sources so that a portion of the PLD can be backed up with a battery when power to the PLD is removed. A switch that supplies power to the backed up portion of the PLD receives power from both an external power supply and from the battery, and detects voltage level of the external power supply, switching to battery power when voltage from the external power supply is not sufficient.
摘要翻译：可以制造PLD以包括来自两个源的电源线，使得当PLD的电源被去除时，一部分PLD可以用电池备份。向PLD的备用部分供电的开关从外部电源和电池两者接收电力，并检测外部电源的电压，当来自外部电源的电压不足时切换到电池电力。

10. 发明授权

US06346825B1 Block RAM with configurable data width and parity for use in a field programmable gate array 有权
标题翻译：块RAM具有可配置的数据宽度和奇偶校验，用于现场可编程门阵列
公开(公告)号：US06346825B1
公开(公告)日：2002-02-12
申请号：US09680205
申请日：2000-10-06
申请人： Raymond C. Pang , Steven P. Young , Trevor J. Bauer
发明人： Raymond C. Pang , Steven P. Young , Trevor J. Bauer
IPC分类号： H03K19177
CPC分类号： H03K19/1776
摘要： A dedicated block random access memory (RAM) is provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA). The block RAM includes a memory cell array and control logic that is configurable to select one of a plurality of parity or non-parity modes for accessing the memory cell array. In one embodiment, the non-parity modes include a 1×16384 mode, a 2×8192 mode, and a 4×4096 mode, while the parity modes include a 9×2048 mode, a 18×1024 mode and an 36×512 mode. The control logic selects the parity/non-parity mode in response to configuration bits stored in corresponding configuration memory cells of the PLD. The configuration bits are programmed during configuration of the PLD. In one variation, the control logic selects the parity/non-parity mode in response to user signals. In a particular embodiment, the block RAM is a dual-port memory having a first port and a second port. In this embodiment, the first and second ports can be independently configured to have different (or the same) parity or non-parity modes.
摘要翻译：为诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）提供专用块随机存取存储器（RAM）。块RAM包括存储单元阵列和控制逻辑，可配置为选择用于访问存储单元阵列的多个奇偶校验或非奇偶校验模式之一。在一个实施例中，非奇偶校验模式包括1x16384模式，2x8192模式和4×4096模式，而奇偶校验模式包括9×2048模式，18×1024模式和36×512模式。响应于存储在PLD的相应配置存储器单元中的配置位，控制逻辑选择奇偶校验/非奇偶校验模式。在配置PLD期间对配置位进行编程。在一个变化中，控制逻辑响应于用户信号选择奇偶校验/非奇偶校验模式。在特定实施例中，块RAM是具有第一端口和第二端口的双端口存储器。在该实施例中，第一和第二端口可以被独立地配置为具有不同的（或相同的）奇偶校验或非奇偶校验模式。

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