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1. 发明授权

US06441641B1 Programmable logic device with partial battery backup 有权
标题翻译：具有部分电池备份的可编程逻辑器件
公开(公告)号：US06441641B1
公开(公告)日：2002-08-27
申请号：US09724735
申请日：2000-11-28
申请人： Raymond C. Pang , Venu M. Kondapalli , Jane W. Sowards , Scott O. Frake , Jennifer Wong , F. Erich Goetting , Peter H. Alfke , Schuyler E. Shimanek
发明人： Raymond C. Pang , Venu M. Kondapalli , Jane W. Sowards , Scott O. Frake , Jennifer Wong , F. Erich Goetting , Peter H. Alfke , Schuyler E. Shimanek
IPC分类号： H01L2500
CPC分类号： G06F21/76
摘要： A PLD can be manufactured to include power supply lines from two sources so that a portion of the PLD can be backed up with a battery when power to the PLD is removed. A switch that supplies power to the backed up portion of the PLD receives power from both an external power supply and from the battery, and detects voltage level of the external power supply, switching to battery power when voltage from the external power supply is not sufficient.
摘要翻译：可以制造PLD以包括来自两个源的电源线，使得当PLD的电源被去除时，一部分PLD可以用电池备份。向PLD的备用部分供电的开关从外部电源和电池两者接收电力，并检测外部电源的电压，当来自外部电源的电压不足时切换到电池电力。

2. 发明授权

US08224637B1 Method and apparatus for modeling transistors in an integrated circuit design 有权
标题翻译：用于在集成电路设计中建模晶体管的方法和装置
公开(公告)号：US08224637B1
公开(公告)日：2012-07-17
申请号：US11732194
申请日：2007-04-02
申请人： Jane W. Sowards , Shuxian Wu , Kaiman Chan
发明人： Jane W. Sowards , Shuxian Wu , Kaiman Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： An aspect of the invention relates to modeling a transistor in an integrated circuit design. Layout data for the integrated circuit design is obtained. A geometry relating the transistor to at least one well edge of at least one implant well is extracted from the layout data. An effective well proximity value for the transistor is calculated based on the at least one well edge using a complementary error function. The transistor is modeled using the effective well proximity value. In one embodiment, the effective well proximity value is added to a post-layout extracted netlist for the integrated circuit design. The integrated circuit design may be simulated using the post-layout extracted netlist. The effective well proximity value may be used to calculate a threshold voltage for the transistor during the step of simulating the integrated circuit.
摘要翻译：本发明的一个方面涉及对集成电路设计中的晶体管进行建模。获得集成电路设计的布局数据。从布局数据中提取将晶体管与至少一个注入井的至少一个阱边缘相关联的几何形状。基于使用互补误差函数的至少一个阱边缘来计算晶体管的有效阱接近值。晶体管使用有效的阱接近值进行建模。在一个实施例中，将有效阱接近值添加到用于集成电路设计的后布局提取的网表。可以使用后布局提取的网表来模拟集成电路设计。在模拟集成电路的步骤期间，可以使用有效阱接近度来计算晶体管的阈值电压。

3. 发明授权

US07765498B1 Methods of incorporating process-induced layout dimension changes into an integrated circuit simulation netlist 有权
标题翻译：将过程引起的布局维度变化纳入集成电路仿真网表的方法
公开(公告)号：US07765498B1
公开(公告)日：2010-07-27
申请号：US11805739
申请日：2007-05-24
申请人： Jonathan J. Ho , Yan Wang , Xin X. Wu , Jane W. Sowards
发明人： Jonathan J. Ho , Yan Wang , Xin X. Wu , Jane W. Sowards
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5081
摘要： Computer-implemented methods of generating netlists for use in post-layout simulation procedures. A lookup table includes a predetermined set of features (e.g., transistors of specified sizes and shapes) supported by an integrated circuit (IC) fabrication process, with dimensions and process induced dimension variations being included for each feature. A netlist is extracted from an IC layout, the extracted netlist specifying circuit elements (e.g., transistors) implemented by the IC layout and interconnections between the circuit elements. A search pattern is run on the IC layout to identify features in the IC layout corresponding to features included in the lookup table. Circuit elements in the extracted netlist that correspond to the identified features are then modified using values from the lookup table, and the modified netlist is output. In some embodiments, the netlist extraction, search pattern, and netlist modification are all performed as a single netlist generation step.
摘要翻译：计算机实现的生成用于后布局模拟程序的网表的方法。查找表包括由集成电路（IC）制造过程支持的预定的一组特征（例如，特定尺寸和形状的晶体管），其中每个特征包括尺寸和工艺引起的尺寸变化。从IC布局提取网表，提取的网表指定电路元件（例如，晶体管）由IC布局实现，并且电路元件之间的互连。在IC布局上运行搜索模式，以识别与查找表中包含的功能相对应的IC布局中的功能。然后使用来自查找表的值来修改对应于所识别的特征的提取的网表中的电路元件，并输出修改的网表。在一些实施例中，网表提取，搜索模式和网表修改都被执行为单个网表生成步骤。

4. 发明授权

US07932563B2 Techniques for improving transistor-to-transistor stress uniformity 有权
标题翻译：提高晶体管至晶体管应力均匀性的技术
公开(公告)号：US07932563B2
公开(公告)日：2011-04-26
申请号：US12363666
申请日：2009-01-30
申请人： Jung-Ching J. Ho , Jane W. Sowards , Shuxian Wu
发明人： Jung-Ching J. Ho , Jane W. Sowards , Shuxian Wu
IPC分类号： G06F17/50
CPC分类号： H01L21/823807 , H01L27/0207 , H01L27/11807 , H01L29/7843
摘要： An integrated circuit has a transistor with an active gate structure overlying an active diffusion area formed in a semiconductor substrate. A dummy gate structure is formed over a diffusion area and separated from the active gate structure by a selected distance (d2). A stress layer overlying the transistor array produces stress in a channel region of the transistor.
摘要翻译：集成电路具有覆盖在半导体衬底中形成的有源扩散区域的有源栅极结构的晶体管。在扩散区域上形成虚拟栅极结构，并与有源栅极结构分开一定距离（d2）。覆盖晶体管阵列的应力层在晶体管的沟道区域产生应力。

5. 发明授权

US07793238B1 Method and apparatus for improving a circuit layout using a hierarchical layout description 有权
标题翻译：使用层次布局描述改进电路布局的方法和装置
公开(公告)号：US07793238B1
公开(公告)日：2010-09-07
申请号：US12053874
申请日：2008-03-24
申请人： Peter Rabkin , Zhiyuan Wu , Min-Hsing Peter Chen , Jane W. Sowards , Michael J. Hart , Min-Fang Ho
发明人： Peter Rabkin , Zhiyuan Wu , Min-Hsing Peter Chen , Jane W. Sowards , Michael J. Hart , Min-Fang Ho
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： Various approaches for improving an integrated circuit layout. In one approach, a tree-type hierarchical layout representation of the circuit design is traversed. At each block visited during the traversing, a process determines whether there exists an improvement opportunity for each cell associated with the block. In response to determining that an improvement opportunity exists for a cell of a first block of the plurality of blocks, the process determines whether a modification to the cell satisfies one or more rules for every other block of the block type of the first block in the hierarchical representation. If the rules are satisfied, the modification is stored. Otherwise, the modification is discarded.
摘要翻译：用于改善集成电路布局的各种方法。在一种方法中，遍历了电路设计的树型分层布局表示。在遍历期间访问的每个块处，确定是否存在与该块相关联的每个单元的改进机会。响应于确定对于所述多个块的第一块的小区存在改进机会，所述过程确定对所述小区的修改是否满足所述小区的所述第一块的块类型的每个其他块的一个或多个规则分层表示。如果规则满足，则修改被存储。否则，修改被丢弃。

6. 发明申请

US20100193870A1 TECHNIQUES FOR IMPROVING TRANSISTOR-TO-TRANSISTOR STRESS UNIFORMITY 有权
标题翻译：改进晶体管到晶体管应力均匀性的技术
公开(公告)号：US20100193870A1
公开(公告)日：2010-08-05
申请号：US12363666
申请日：2009-01-30
申请人： Jung-Ching J. Ho , Jane W. Sowards , Shuxian Wu
发明人： Jung-Ching J. Ho , Jane W. Sowards , Shuxian Wu
IPC分类号： H01L29/772 , G06F17/50 , H03K17/693
CPC分类号： H01L21/823807 , H01L27/0207 , H01L27/11807 , H01L29/7843
摘要： An integrated circuit (100) has a transistor with an active gate structure 108 overlying an active diffusion area 112 formed in a semiconductor substrate 126. A dummy gate structure 110 is formed over a diffusion area and separated from the active gate structure by a selected distance (d2). A stress layer (130) overlying the transistor array produces stress in a channel region (107) of the transistor.
摘要翻译：集成电路（100）具有晶体管，其具有覆盖形成在半导体衬底126中的有源扩散区域112的有源栅极结构108.伪栅极结构110形成在扩散区域上，并与有源栅极结构分开一定距离（d2）。覆盖晶体管阵列的应力层（130）在晶体管的沟道区（107）中产生应力。

7. 发明授权

US07420392B2 Programmable gate array and embedded circuitry initialization and processing 有权
标题翻译：可编程门阵列和嵌入式电路的初始化和处理
公开(公告)号：US07420392B2
公开(公告)日：2008-09-02
申请号：US10898582
申请日：2004-07-23
申请人： David P. Schultz , Stephen M. Douglass , Steven P. Young , Nigel G. Herron , Mehul R. Vashi , Jane W. Sowards
发明人： David P. Schultz , Stephen M. Douglass , Steven P. Young , Nigel G. Herron , Mehul R. Vashi , Jane W. Sowards
IPC分类号： H01L25/00 , H03K19/173
CPC分类号： H03K19/17772 , G06F15/7867 , H03K17/22 , H03K19/0016 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and interconnect of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric. In one operation, the programmable logic fabric is configured prior to the startup/boot sequence of the fixed logic circuit. In another operation, the fixed logic circuit is started up and is employed to configure the programmable logic fabric.
摘要翻译：互连逻辑提供嵌入式固定逻辑电路或电路与可编程门阵列的可编程逻辑结构的连接，使得固定逻辑电路用作可编程逻辑结构的扩展。互连逻辑包括互连瓦片，并且还可以包括接口逻辑。互连瓦片提供了固定逻辑电路的输入和/或输出之间的选择性连接以及可编程逻辑结构的互连。接口逻辑（包含在内）提供逻辑电路，用于对固定逻辑电路和可编程逻辑结构之间的数据传输进行调节。在一个操作中，可编程逻辑结构在固定逻辑电路的启动/引导顺序之前被配置。在另一个操作中，固定逻辑电路被启动并用于配置可编程逻辑结构。

8. 发明授权

US06798239B2 Programmable gate array having interconnecting logic to support embedded fixed logic circuitry 有权
标题翻译：具有互连逻辑以支持嵌入式固定逻辑电路的可编程门阵列
公开(公告)号：US06798239B2
公开(公告)日：2004-09-28
申请号：US09968446
申请日：2001-09-28
申请人： Stephen M. Douglass , Steven P. Young , Nigel G. Herron , Mehul R. Vashi , Jane W. Sowards
发明人： Stephen M. Douglass , Steven P. Young , Nigel G. Herron , Mehul R. Vashi , Jane W. Sowards
IPC分类号： H03K19177
CPC分类号： G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and the interconnects of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric.
摘要翻译：互连逻辑提供嵌入式固定逻辑电路或电路与可编程门阵列的可编程逻辑结构的连接，使得固定逻辑电路用作可编程逻辑结构的扩展。互连逻辑包括互连瓦片，并且还可以包括接口逻辑。互连瓦片提供固定逻辑电路的输入和/或输出与可编程逻辑结构的互连之间的选择性连接。接口逻辑（包含在内）提供逻辑电路，用于对固定逻辑电路和可编程逻辑结构之间的数据传输进行调节。

9. 发明授权

US06366117B1 Nonvolatile/battery-backed key in PLD 有权
标题翻译： PLD中的非易失性/电池供电密钥
公开(公告)号：US06366117B1
公开(公告)日：2002-04-02
申请号：US09724973
申请日：2000-11-28
申请人： Raymond C. Pang , Jennifer Wong , Scott O. Frake , Jane W. Sowards , Venu M. Kondapalli , F. Erich Goetting , Stephen M. Trimberger , Kameswara K. Rao
发明人： Raymond C. Pang , Jennifer Wong , Scott O. Frake , Jane W. Sowards , Venu M. Kondapalli , F. Erich Goetting , Stephen M. Trimberger , Kameswara K. Rao
IPC分类号： H04L900
CPC分类号： G06F21/76
摘要： It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, the encrypted design is decrypted by a key or keys within the PLD that are preserved when power is removed by either being stored in nonvolatile memory or by being backed up with a battery that switches into operation when the power is removed from the PLD.
摘要翻译：有时期望加密设计以加载到PLD中，使得攻击者可能不会在将设计复制到PLD中时学习和复制设计。根据本发明，加密设计由PLD内的密钥或密钥解密，当通过存储在非易失性存储器中的电力被去除或通过在电力被从 PLD。

10. 发明授权

US06218864B1 Structure and method for generating a clock enable signal in a PLD 有权
标题翻译：用于在PLD中产生时钟使能信号的结构和方法
公开(公告)号：US06218864B1
公开(公告)日：2001-04-17
申请号：US09370854
申请日：1999-08-10
申请人： Steven P. Young , Jane W. Sowards , Wilson K. Yee
发明人： Steven P. Young , Jane W. Sowards , Wilson K. Yee
IPC分类号： H03K19096
CPC分类号： H03K19/1774 , H03K19/17744
摘要： The invention provides a structure and method of generating a clock enable signal in a programmable logic device (PLD). A first embodiment of the invention comprises a clock enable circuit implemented such that the critical paths have only two levels of logic. In this embodiment, the critical paths are implemented in dedicated logic while other portions of the clock enable circuit are implemented using programmable logic. According to another embodiment of the invention, the clock enable circuit is located near the center of a first edge of the device. A first plurality of output registers are located along the first edge on either side of the clock enable circuit, with additional output registers being located along the two adjacent half-edges. Programmable interconnection points (PIPs) permit a clock enable interconnect line along the first edge to be programmably extended to the additional output registers. In another embodiment, the clock enable circuit is duplicated in two opposite edges of the device.
摘要翻译：本发明提供了一种在可编程逻辑器件（PLD）中产生时钟使能信号的结构和方法。本发明的第一实施例包括实现为使得关键路径仅具有两个逻辑电平的时钟使能电路。在本实施例中，关键路径以专用逻辑实现，而使用可编程逻辑实现时钟使能电路的其他部分。根据本发明的另一实施例，时钟使能电路位于设备的第一边缘的中心附近。第一组多个输出寄存器位于时钟使能电路两侧的第一边沿，附加的输出寄存器位于两个相邻的半边。可编程互连点（PIP）允许沿着第一边沿的时钟使能互连线可编程地扩展到附加输出寄存器。在另一个实施例中，时钟使能电路在设备的两个相对的边缘被复制。

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