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1. 发明授权

US07501879B1 eFuse resistance sensing scheme with improved accuracy 有权
标题翻译： eFuse电阻传感方案具有提高的精度
公开(公告)号：US07501879B1
公开(公告)日：2009-03-10
申请号：US11717836
申请日：2007-03-13
申请人： Kwansuhk Oh , Raymond C. Pang , Hsung Jai Im , Sunhom Paak
发明人： Kwansuhk Oh , Raymond C. Pang , Hsung Jai Im , Sunhom Paak
IPC分类号： G11C17/18 , H01H85/00
CPC分类号： G11C17/16 , G11C17/18
摘要： An eFuse sensing circuit replaces the inverters used to provide the “read” output state of a conventional eFuse circuit. The sensing circuit includes a comparator with one input coupled to the eFuse circuitry, and a second input coupled to a reference voltage generator circuit. The reference voltage generator circuit includes an internal resistor. Transistors of the sense circuit are provided to mimic the transistors of the eFuse circuit, so that variations of transistors due to process, voltage and temperature will be substantially the same. The resistor of the sense circuit is then effectively compared with the resistance of the eFuse by the comparator irrespective of temperature and process variations.
摘要翻译： eFuse感测电路取代了用于提供常规eFuse电路的“读取”输出状态的逆变器。感测电路包括具有耦合到eFuse电路的一个输入和耦合到参考电压发生器电路的第二输入的比较器。参考电压发生器电路包括内部电阻器。提供感测电路的晶体管以模拟eFuse电路的晶体管，使得由于工艺，电压和温度而导致的晶体管的变化将基本相同。然后将感测电路的电阻与比较器的eFuse的电阻进行有效的比较，而与温度和工艺变化无关。

2. 发明授权

US07598749B1 Integrated circuit with fuse programming damage detection 有权
标题翻译：具有保险丝编程损伤检测的集成电路
公开(公告)号：US07598749B1
公开(公告)日：2009-10-06
申请号：US11449171
申请日：2006-06-08
申请人： Boon Yong Ang , Sunhom Paak , Hsung Jai Im , Kwansuhk Oh , Raymond C. Pang
发明人： Boon Yong Ang , Sunhom Paak , Hsung Jai Im , Kwansuhk Oh , Raymond C. Pang
IPC分类号： G01R31/07 , H01L29/00
CPC分类号： G01R31/07 , G01R31/31717 , G11C29/02 , G11C29/027
摘要： An integrated circuit with an efuse having an efuse link includes a damage detection structure disposed in relation to the efuse so as to detect damage in the IC resulting from programming the efuse. Damage sensing circuitry is optionally included on the IC. Embodiments are used in evaluation wafers to determine proper efuse fabrication and programming parameters, and in production ICs to identify efuse programming damage that might create a latent defect.
摘要翻译：具有efuse链路的efuse的集成电路包括相对于efuse设置的损坏检测结构，以便检测由于对efuse进行编程而导致的IC中的损坏。 IC上可选地包含损伤感测电路。在评估晶片中使用实施例来确定适当的efuse制造和编程参数，并且在生产IC中用于识别可能产生潜在缺陷的efuse编程损伤。

3. 发明授权

US07710813B1 Electronic fuse array 有权
标题翻译：电子保险丝阵列
公开(公告)号：US07710813B1
公开(公告)日：2010-05-04
申请号：US12043099
申请日：2008-03-05
申请人： Hsung Jai Im , Sunhom Paak , Raymond C. Pang , Boon Yong Ang , Serhii Tumakha
发明人： Hsung Jai Im , Sunhom Paak , Raymond C. Pang , Boon Yong Ang , Serhii Tumakha
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C17/18
摘要： An electronic fuse memory array has an array core with a plurality of selectable unit cells. A unit cell has a fuse and a cell transistor (M12). A programming current path goes through the fuse and the cell transistor to a word line ground and a read current path also goes through the fuse and the cell transistor to the word line ground.
摘要翻译：电子熔丝存储器阵列具有带有多个可选单元单元的阵列芯。单元电池具有熔丝和单元晶体管（M12）。编程电流路径通过熔丝和单元晶体管到字线接地，并且读电流路径也穿过熔丝和单元晶体管到字线地。

4. 发明授权

US07345507B1 Multi-product die configurable as two or more programmable integrated circuits of different logic capacities 有权
标题翻译：多产品管芯可配置为具有不同逻辑容量的两个或多个可编程集成电路
公开(公告)号：US07345507B1
公开(公告)日：2008-03-18
申请号：US11333991
申请日：2006-01-17
申请人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
发明人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
IPC分类号： H01L25/00
CPC分类号： H03K19/177
摘要： A multi-product integrated circuit die includes at least two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A selection code storage circuit stores a product selection code. A first value of the product selection code selects the option where both the first and second portions of the first die are operational. A second value of the product selection code selects the option where only the first portion of the first die is operational. The selection code storage circuit can include non-volatile memory or a fuse structure, or the product selection code can be configured as a package bonding option. The product selection code can also enable boundary scan for the operational portion of the die, and omit from the boundary scan chain any portions of the die that are deliberately rendered non-operational.
摘要翻译：多产品集成电路管芯包括至少两个不同的部分，其中至少一个部分可以以某种方式（例如，非功能的，不可访问的和/或不可编程的）被故意地变为不可操作的。选择码存储电路存储产品选择码。产品选择代码的第一个值选择第一模具的第一和第二部分都可操作的选项。产品选择代码的第二个值选择仅第一个模具的第一部分可操作的选项。选择代码存储电路可以包括非易失性存储器或熔丝结构，或者可以将产品选择代码配置为封装绑定选项。产品选择代码还可以为模具的操作部分启用边界扫描，并且从边界扫描链中省略故意使其不可操作的模具的任何部分。

5. 发明授权

US07451369B1 Scalable columnar boundary scan architecture for integrated circuits 有权
标题翻译：用于集成电路的可扩展柱状边界扫描架构
公开(公告)号：US07451369B1
公开(公告)日：2008-11-11
申请号：US11498372
申请日：2006-08-03
申请人： Kwansuhk Oh , Raymond C. Pang
发明人： Kwansuhk Oh , Raymond C. Pang
IPC分类号： G01R31/28
CPC分类号： G01R31/318552
摘要： An integrated circuit having a scalable boundary scan architecture. Logic elements, each including at least one data storage element, are arranged in rows and columns. A data distribution system couples the data storage elements together to form a boundary scan chain that traverses the columns in order, e.g., a first column, then a second column, and so forth, from top to bottom in each column. A clock distribution system is coupled to each of the data storage elements in the chain, and provides a clock signal to the first and second columns, again from top to bottom. The clock distribution system provides the clock signal to the top of the second column prior to providing it to the top of the first column. In some embodiments, an additional flip-flop is added to the boundary scan chain for each logic element, to increase the overall operating frequency of the scan chain.
摘要翻译：具有可扩展边界扫描架构的集成电路。每个包括至少一个数据存储元件的逻辑元件以行和列排列。数据分配系统将数据存储元件耦合在一起以形成跨越列的边界扫描链，从而从每个列的顶部到底部依次穿过列，例如第一列，然后是第二列等等。时钟分配系统耦合到链中的每个数据存储元件，并且从顶部到底部再次向第一和第二列提供时钟信号。时钟分配系统在将其提供到第一列的顶部之前将时钟信号提供给第二列的顶部。在一些实施例中，为每个逻辑元件向边界扫描链增加了一个附加的触发器，以增加扫描链的总体工作频率。

6. 发明授权

US06664837B1 Delay line trim unit having consistent performance under varying process and temperature conditions 有权
标题翻译：延迟线修剪单元在不同的工艺和温度条件下具有一致的性能
公开(公告)号：US06664837B1
公开(公告)日：2003-12-16
申请号：US10247241
申请日：2002-09-18
申请人： Kwansuhk Oh , Raymond C. Pang
发明人： Kwansuhk Oh , Raymond C. Pang
IPC分类号： H03H1126
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00065 , H03K2005/00221 , H03L7/0818
摘要： A delay circuit has a delay that is consistent under varying process and temperature conditions. The delay through a delay path is controlled by inserting resistors on the pull-up and pull-down paths of the delaying inverters. Each resistor has a resistance value that is determined by a varying a number of enabled similarly-sized transistors coupled in parallel across the resistor, rather than by varying the size of a single transistor. In one embodiment, a first transistor in each resistor is always enabled, while additional transistors are enabled using select signals. In one embodiment, the select signals are provided by configuration memory cells in a PLD. Other embodiments include additional delay paths and a multiplexer circuit that selects one of the delay paths. The described delay circuit is particularly useful in a DLL trim unit, where variations between resistors can cause jitter and locking problems in the DLL.
摘要翻译：延迟电路具有在变化的工艺和温度条件下是一致的延迟。通过延迟路径的延迟通过在延迟逆变器的上拉和下拉路径上插入电阻来控制。每个电阻器具有由在电阻器上并联耦合的使能相似尺寸的晶体管的数量的变化确定的电阻值，而不是通过改变单个晶体管的尺寸来确定。在一个实施例中，每个电阻器中的第一晶体管总是使能，而使用选择信号启用附加晶体管。在一个实施例中，选择信号由PLD中的配置存储器单元提供。其他实施例包括额外的延迟路径和选择延迟路径之一的多路复用器电路。所描述的延迟电路在DLL修剪单元中特别有用，其中电阻之间的变化可能导致DLL中的抖动和锁定问题。

7. 发明授权

US07535278B1 Circuits and methods of using parallel counter controlled delay lines to generate a clock signal 有权
标题翻译：使用并行计数器控制的延迟线来产生时钟信号的电路和方法
公开(公告)号：US07535278B1
公开(公告)日：2009-05-19
申请号：US11717810
申请日：2007-03-13
申请人： Robert M. Ondris , Raymond C. Pang , Kwansuhk Oh
发明人： Robert M. Ondris , Raymond C. Pang , Kwansuhk Oh
IPC分类号： G06F1/04 , H03H11/26
CPC分类号： G06F1/08
摘要： A clock manager circuit includes a number of clock output blocks, each providing an independent output. Counter controlled delay devices (CCDs) are used in these clock output blocks. To achieve full cycle delays, the CCDs are placed in parallel with outputs of the CCD outputs driving set and reset terminals of a common latch. The parallel connection of the CCDs, as opposed to a series connection, offers an increase in maximum frequency and possibly fewer needed CCDs than if the CCDs are placed in series. In one embodiment, at least one of the CCDs includes a counter/compare circuit with a frequency divider enabling the frequency of the CCD to be varied relative to the common input clock.
摘要翻译：时钟管理器电路包括多个时钟输出块，每个时钟输出块提供独立的输出。这些时钟输出块中使用了计数器控制延迟器（CCD）。为了实现全周期延迟，CCD与公共锁存器的CCD输出驱动装置和复位端子的输出并联放置。与串联连接相比，CCD的并联连接提供了最大频率的增加，并且与CCD串联放置相比，可能需要更少的CCD。在一个实施例中，CCD中的至少一个包括具有使得CCD的频率相对于公共输入时钟变化的分频器的计数器/比较电路。

8. 发明授权

US07491576B1 Yield-enhancing methods of providing a family of scaled integrated circuits 有权
标题翻译：提供一系列缩放集成电路的产量增强方法
公开(公告)号：US07491576B1
公开(公告)日：2009-02-17
申请号：US11333990
申请日：2006-01-17
申请人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
发明人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
IPC分类号： H01L21/66 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L22/22 , H01L23/544 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit die (e.g., a programmable logic device (PLD) die) is manufactured that has the capability of being configured as at least two differently-sized family members. The IC die is tested prior to packaging. If a first portion of the IC die is fully functional, but a second portion includes a localized defect, then the IC die is packaged with a product selection code that configures the IC die to operate as only the first portion of the die. The second portion of the die is deliberately rendered non-operational. Therefore, the IC die can still be sold as a fully functional packaged IC.
摘要翻译：制造集成电路管芯（例如，可编程逻辑器件（PLD）管芯），其具有被配置为至少两个不同尺寸的家庭部件的能力。在封装之前测试IC芯片。如果IC芯片的第一部分是完全功能的，但是第二部分包括局部缺陷，则IC芯片被封装成产品选择代码，所述产品选择代码构成IC裸片仅作为芯片的第一部分进行操作。死亡的第二部分故意使其不能运作。因此，IC芯片仍然可以作为全功能封装IC出售。

9. 发明授权

US07190202B1 Trim unit having less jitter 有权
标题翻译：修剪单元具有较少的抖动
公开(公告)号：US07190202B1
公开(公告)日：2007-03-13
申请号：US11099908
申请日：2005-04-05
申请人： Kwansuhk Oh , Raymond C. Pang
发明人： Kwansuhk Oh , Raymond C. Pang
IPC分类号： H03L7/00
CPC分类号： H03L7/0814 , H03L7/0818
摘要： A trim unit includes a delay line and one or more individually selectable load elements. The delay line has a first end to receive an input clock signal, and has a second end to generate an output clock signal. Each load element includes a select transistor and a load capacitor coupled in series between the delay line and ground potential, and includes a filter circuit having an input to receive a select signal and having an output coupled to a gate of the select transistor. Upon assertion of each select signal, the filter circuit gradually charges the gate of the select transistor, which in turn causes the load element to gradually increase the phase-delay between the input and output clock signals.
摘要翻译：修剪单元包括延迟线和一个或多个可单独选择的负载元件。延迟线具有接收输入时钟信号的第一端，并具有产生输出时钟信号的第二端。每个负载元件包括在延迟线和接地电位之间串联耦合的选择晶体管和负载电容器，并且包括具有输入以接收选择信号并具有耦合到选择晶体管的栅极的输出的滤波器电路。在确定每个选择信号时，滤波器电路逐渐对选择晶体管的栅极充电，这又导致负载元件逐渐增加输入和输出时钟信号之间的相位延迟。

10. 发明授权

US07515452B1 Interleaved memory cell with single-event-upset tolerance 有权
标题翻译：具有单事件不正常容限的交错记忆单元
公开(公告)号：US07515452B1
公开(公告)日：2009-04-07
申请号：US11649447
申请日：2007-01-03
申请人： Jan L. de Jong , Susan Xuan Nguyen , Raymond C. Pang
发明人： Jan L. de Jong , Susan Xuan Nguyen , Raymond C. Pang
IPC分类号： G11C11/00
CPC分类号： G11C8/04 , H03K19/00392 , H03K19/1776 , H03K19/17764 , H03K19/1778
摘要： A memory array has a first memory cell with a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value. A first portion of the plurality of transistors is in a first cell portion and a second portion of the plurality of transistors is in a second cell portion. A second memory cell has a third cell portion and a fourth cell portion. The third cell portion is between the first cell portion and the second cell portion and adjacent to each of the first cell portion and the second cell portion. In a particular embodiment, the memory cell is a single-event-upset (“SEU”) tolerant memory cell and the first and second cell portions are each a half cell of a sixteen transistor memory cell.
摘要翻译：存储器阵列具有连接有多个晶体管的第一存储器单元，以便在事件颠倒初始值之后将数据值恢复到存储器单元的节点到初始值。多个晶体管的第一部分在第一单元部分中，并且多个晶体管的第二部分在第二单元部分中。第二存储单元具有第三单元部分和第四单元部分。第三单元部分在第一单元部分和第二单元部分之间并且与第一单元部分和第二单元部分中的每一个相邻。在特定实施例中，存储器单元是单事件不正常（“SEU”）容限存储器单元，并且第一和第二单元部分各自是十六晶体管存储单元的半单元。

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