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1. 发明授权

US07157951B1 Digital clock manager capacitive trim unit 有权
标题翻译：数字时钟管理器电容调整单元
公开(公告)号：US07157951B1
公开(公告)日：2007-01-02
申请号：US10837186
申请日：2004-04-30
申请人： Shawn K. Morrison , Raymond C. Pang
发明人： Shawn K. Morrison , Raymond C. Pang
IPC分类号： H03H11/26
CPC分类号： H03K5/15013 , G06F1/10
摘要： A delay line for a digital clock manager includes a tap delay structure and a trim delay structure. The trim delay structure includes a first buffer coupled to receive a clock signal from the tap delay structure, and in response, provide a delayed clock signal to a set of clock lines. The trim delay structure also includes a capacitive trim unit having a plurality of capacitive trim elements tapped off the set of clock lines. The capacitive trim elements are selectively enabled or disabled, thereby introducing additional delay to the delayed clock signal on the set of clock lines. Each capacitive trim element can include a transmission gate structure, which is turned on to introduce significant junction capacitance to the set of clock lines. The trim delay structure can also include a second buffer adapted to buffer the delayed clock signal on the set of clock lines.
摘要翻译：数字时钟管理器的延迟线包括抽头延迟结构和修整延迟结构。修剪延迟结构包括第一缓冲器，其被耦合以从抽头延迟结构接收时钟信号，并且作为响应，向一组时钟线提供延迟的时钟信号。修剪延迟结构还包括电容修剪单元，其具有从该组时钟线分离的多个电容修剪元件。电容调整元件被选择性地使能或禁止，从而对该组时钟线上的延迟的时钟信号引入额外的延迟。每个电容调整元件可以包括传输门结构，其被导通以将显着的结电容引入该组时钟线。修剪延迟结构还可以包括适于缓冲该组时钟线上延迟的时钟信号的第二缓冲器。

2. 发明授权

US07564264B1 Preventing transistor damage 有权
标题翻译：防止晶体管损坏
公开(公告)号：US07564264B1
公开(公告)日：2009-07-21
申请号：US11803530
申请日：2007-05-14
申请人： Shawn K. Morrison , James J. Koning , Greg W. Starr , John D. Logue , Robert M. Ondris
发明人： Shawn K. Morrison , James J. Koning , Greg W. Starr , John D. Logue , Robert M. Ondris
IPC分类号： H03K19/094
CPC分类号： H03K19/00315
摘要： Preventing transistor damage to an integrated circuit is described. The circuit includes a switch with a first pair of p-type transistors respectively coupled in source-drain parallel with second pair of p-type transistors for preventing Negative Bias Temperature Instability (“NBTI”) damage to the second pair of p-type transistors. The switch is configured to such that when in a state associated with causing, or potentially causing, NBTI damage, both of the second pair of p-type transistors are in an OFF state for preventing NBTI damage thereto.
摘要翻译：描述了防止晶体管损坏集成电路。该电路包括具有第一对p型晶体管的开关，该第一对p型晶体管分别以与第二对p型晶体管并联的源极漏极耦合，用于防止对第二对p型晶体管的负偏压温度不稳定性（“NBTI”）损伤。开关被配置为使得当处于与引起或可能引起NBTI损坏相关联的状态时，第二对p型晶体管都处于关断状态，以防止NBTI损坏。

3. 发明授权

US06983394B1 Method and apparatus for clock signal performance measurement 有权
标题翻译：时钟信号性能测量的方法和装置
公开(公告)号：US06983394B1
公开(公告)日：2006-01-03
申请号：US10351033
申请日：2003-01-24
申请人： Shawn K. Morrison , Andrew K. Percey , John D. Logue , James M. Simkins , Nicholas J. Sawyer
发明人： Shawn K. Morrison , Andrew K. Percey , John D. Logue , James M. Simkins , Nicholas J. Sawyer
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , G01R31/31708 , G01R31/31725 , H04L7/0337
摘要： Method and apparatus for providing a measure of jitter and skew of a clock signal is described. The clock signal may be used as an input to a digital circuit. In one embodiment, a digital delay circuit is used in conjunction with a processing circuit to continuously measure the jitter of an input clock signal, thus providing clock signal performance measurement over time. In another embodiment, a pair of digital delay circuits are used to continuously measure the skew or delay between a reference clock signal and a input clock signal, thus providing a measurement of the skew of the input clock signal over time. The digital delay circuit(s) are formed on-chip, and thus an on-chip determination of jitter or skew may be provided.
摘要翻译：描述了用于提供时钟信号的抖动和偏斜的量度的方法和装置。时钟信号可以用作数字电路的输入。在一个实施例中，数字延迟电路与处理电路结合使用，以连续测量输入时钟信号的抖动，从而随时间提供时钟信号性能测量。在另一个实施例中，使用一对数字延迟电路来连续测量参考时钟信号和输入时钟信号之间的偏差或延迟，从而提供输入时钟信号随时间偏移的测量。数字延迟电路形成在片上，因此可以提供抖动或偏斜的片上确定。

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