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1. 发明授权

US07501879B1 eFuse resistance sensing scheme with improved accuracy 有权
标题翻译： eFuse电阻传感方案具有提高的精度
公开(公告)号：US07501879B1
公开(公告)日：2009-03-10
申请号：US11717836
申请日：2007-03-13
申请人： Kwansuhk Oh , Raymond C. Pang , Hsung Jai Im , Sunhom Paak
发明人： Kwansuhk Oh , Raymond C. Pang , Hsung Jai Im , Sunhom Paak
IPC分类号： G11C17/18 , H01H85/00
CPC分类号： G11C17/16 , G11C17/18
摘要： An eFuse sensing circuit replaces the inverters used to provide the “read” output state of a conventional eFuse circuit. The sensing circuit includes a comparator with one input coupled to the eFuse circuitry, and a second input coupled to a reference voltage generator circuit. The reference voltage generator circuit includes an internal resistor. Transistors of the sense circuit are provided to mimic the transistors of the eFuse circuit, so that variations of transistors due to process, voltage and temperature will be substantially the same. The resistor of the sense circuit is then effectively compared with the resistance of the eFuse by the comparator irrespective of temperature and process variations.
摘要翻译： eFuse感测电路取代了用于提供常规eFuse电路的“读取”输出状态的逆变器。感测电路包括具有耦合到eFuse电路的一个输入和耦合到参考电压发生器电路的第二输入的比较器。参考电压发生器电路包括内部电阻器。提供感测电路的晶体管以模拟eFuse电路的晶体管，使得由于工艺，电压和温度而导致的晶体管的变化将基本相同。然后将感测电路的电阻与比较器的eFuse的电阻进行有效的比较，而与温度和工艺变化无关。

2. 发明授权

US07598749B1 Integrated circuit with fuse programming damage detection 有权
标题翻译：具有保险丝编程损伤检测的集成电路
公开(公告)号：US07598749B1
公开(公告)日：2009-10-06
申请号：US11449171
申请日：2006-06-08
申请人： Boon Yong Ang , Sunhom Paak , Hsung Jai Im , Kwansuhk Oh , Raymond C. Pang
发明人： Boon Yong Ang , Sunhom Paak , Hsung Jai Im , Kwansuhk Oh , Raymond C. Pang
IPC分类号： G01R31/07 , H01L29/00
CPC分类号： G01R31/07 , G01R31/31717 , G11C29/02 , G11C29/027
摘要： An integrated circuit with an efuse having an efuse link includes a damage detection structure disposed in relation to the efuse so as to detect damage in the IC resulting from programming the efuse. Damage sensing circuitry is optionally included on the IC. Embodiments are used in evaluation wafers to determine proper efuse fabrication and programming parameters, and in production ICs to identify efuse programming damage that might create a latent defect.
摘要翻译：具有efuse链路的efuse的集成电路包括相对于efuse设置的损坏检测结构，以便检测由于对efuse进行编程而导致的IC中的损坏。 IC上可选地包含损伤感测电路。在评估晶片中使用实施例来确定适当的efuse制造和编程参数，并且在生产IC中用于识别可能产生潜在缺陷的efuse编程损伤。

3. 发明授权

US07710813B1 Electronic fuse array 有权
标题翻译：电子保险丝阵列
公开(公告)号：US07710813B1
公开(公告)日：2010-05-04
申请号：US12043099
申请日：2008-03-05
申请人： Hsung Jai Im , Sunhom Paak , Raymond C. Pang , Boon Yong Ang , Serhii Tumakha
发明人： Hsung Jai Im , Sunhom Paak , Raymond C. Pang , Boon Yong Ang , Serhii Tumakha
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C17/18
摘要： An electronic fuse memory array has an array core with a plurality of selectable unit cells. A unit cell has a fuse and a cell transistor (M12). A programming current path goes through the fuse and the cell transistor to a word line ground and a read current path also goes through the fuse and the cell transistor to the word line ground.
摘要翻译：电子熔丝存储器阵列具有带有多个可选单元单元的阵列芯。单元电池具有熔丝和单元晶体管（M12）。编程电流路径通过熔丝和单元晶体管到字线接地，并且读电流路径也穿过熔丝和单元晶体管到字线地。

4. 发明授权

US07312625B1 Test circuit and method of use thereof for the manufacture of integrated circuits 有权
标题翻译：用于制造集成电路的测试电路及其使用方法
公开(公告)号：US07312625B1
公开(公告)日：2007-12-25
申请号：US11449197
申请日：2006-06-08
申请人： Sunhom Paak , Hsung Jai Im , Boon Yong Ang , Jan L. de Jong
发明人： Sunhom Paak , Hsung Jai Im , Boon Yong Ang , Jan L. de Jong
IPC分类号： G01R31/00
CPC分类号： G01R31/2884 , G01R31/2831 , G01R31/2858
摘要： A test circuit for fabrication of transistors for Very Large Scale Integration (“VLSI”) processing and method of use thereof are described. Transistors are formed in an array. A first decoder is coupled to gates of the transistors and configured to selectively pass voltage to the gates. A second decoder is coupled to drain regions of the transistors and configured to selectively pass voltage to the drain regions of the transistors. A third decoder is coupled to source regions of the transistors and configured to selectively pass voltage to the source regions of the transistors. A fourth decoder is coupled to body regions of the transistors and configured to selectively pass voltage to the body regions of the transistors.
摘要翻译：描述了用于制造用于超大规模集成（“VLSI”）处理的晶体管的测试电路及其使用方法。晶体管形成阵列。第一解码器耦合到晶体管的栅极并被配置为选择性地将电压传递到栅极。第二解码器耦合到晶体管的漏极区域并且被配置为选择性地将电压传递到晶体管的漏极区域。第三解码器耦合到晶体管的源极区域并且被配置为选择性地将电压传递到晶体管的源极区域。第四解码器耦合到晶体管的体区，并且被配置为选择性地将电压传递到晶体管的体区。

5. 发明授权

US07923811B1 Electronic fuse cell with enhanced thermal gradient 有权
标题翻译：具有增强热梯度的电子保险丝盒
公开(公告)号：US07923811B1
公开(公告)日：2011-04-12
申请号：US12043910
申请日：2008-03-06
申请人： Hsung Jai Im , Sunhom Paak , Boon Yong Ang
发明人： Hsung Jai Im , Sunhom Paak , Boon Yong Ang
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electronic fuse (“E-fuse”) cell is formed on a semiconductor substrate. The E-fuse cell has a fuse element with a fuse link extending from a first fuse terminal across a thick dielectric structure to a second fuse terminal. The first and second fuse terminals are separated from the semiconductor substrate by a thin dielectric layer.
摘要翻译：电子熔丝（“E-fuse”）单元形成在半导体衬底上。电子熔断器单元具有熔丝元件，熔丝链从第一熔丝端子穿过厚电介质结构延伸到第二熔丝端子。第一和第二熔丝端子通过薄的电介质层与半导体衬底分离。

6. 发明申请

US20080101146A1 One-time-programmable logic bit with multiple logic elements 有权
标题翻译：具有多个逻辑元件的一次可编程逻辑位
公开(公告)号：US20080101146A1
公开(公告)日：2008-05-01
申请号：US11588775
申请日：2006-10-27
申请人： Sunhom Paak , Hsung Jai Im , Boon Yong Ang
发明人： Sunhom Paak , Hsung Jai Im , Boon Yong Ang
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , H01L23/5252 , H01L23/5256 , H01L27/101 , H01L27/105 , H01L27/112 , H01L27/11206 , H01L27/11286 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A memory cell with a logic bit has a first one-time-programmable (“OTP”) memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element.
摘要翻译：具有逻辑位的存储器单元具有提供第一OTP存储器元件输出的第一一次可编程（“OTP”）存储器元件和提供第二OTP存储器元件输出的第二OTP存储器元件。耦合到第一OTP存储器元件输出和第二OTP存储器元件输出的逻辑运算器，并提供存储器单元的二进制存储器输出。在特定实施例中，第一OTP存储器元件是与第二OTP存储器元件不同类型的OTP存储器。

7. 发明授权

US07688639B1 CMOS-compatible non-volatile memory cell with lateral inter-poly programming layer 失效
标题翻译： CMOS兼容非易失性存储单元，具有横向多层间编程层
公开(公告)号：US07688639B1
公开(公告)日：2010-03-30
申请号：US11974361
申请日：2007-10-12
申请人： Sunhom Paak , Boon Yong Ang , Hsung Jai Im , Daniel Gitlin
发明人： Sunhom Paak , Boon Yong Ang , Hsung Jai Im , Daniel Gitlin
IPC分类号： G11C16/06
CPC分类号： H01L21/28282 , G11C16/0466 , H01L29/66833
摘要： An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.
摘要翻译：使用标准CMOS制造工艺制造电可擦除可编程只读存储器（“CMOS NON-VOLATILE MEMORY”）单元。第一和第二多晶硅栅极在源极和漏极区域之间的电池的有源区域上被图案化。在多晶硅栅极上生长热氧化物以提供隔离层。氮化硅沉积在第一和第二多晶硅栅极之间以形成横向编程层。

8. 发明申请

US20090224323A1 INTEGRATED CIRCUIT WITH MOSFET FUSE ELEMENT 有权
标题翻译：集成电路与MOSFET保险丝元件
公开(公告)号：US20090224323A1
公开(公告)日：2009-09-10
申请号：US12043914
申请日：2008-03-06
申请人： Hsung Jai Im , Sunhom Paak , Boon Yong Ang
发明人： Hsung Jai Im , Sunhom Paak , Boon Yong Ang
IPC分类号： H01L23/62 , H01L21/336
CPC分类号： H01L27/101 , G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： At least one MOS parameter of a MOS fuse is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse is programmed by applying a programming signal to the fuse terminals so that programming current flows through the fuse link. The fuse resistance is measured to provide a measured fuse resistance associated with a first logic value. A MOS parameter of the programmed MOS fuse is measured to provide a measured MOS parameter value. The measured MOS parameter value is compared to the reference MOS parameter value to determine a second logic value of the MOS fuse, and a bit value is output based on the comparison.
摘要翻译： MOS熔丝的至少一个MOS参数的特征在于提供至少一个MOS参数参考值。然后，通过向熔丝端子施加编程信号来编程MOS熔丝，使得编程电流流过熔丝链。测量熔丝电阻以提供与第一逻辑值相关联的测量的熔丝电阻。测量编程的MOS保险丝的MOS参数，以提供测量的MOS参数值。将测量的MOS参数值与参考MOS参数值进行比较，以确定MOS熔丝的第二逻辑值，并且基于比较输出位值。

9. 发明授权

US07724600B1 Electronic fuse programming current generator with on-chip reference 有权
标题翻译：电子熔断器编程电流发生器，具有片上参考
公开(公告)号：US07724600B1
公开(公告)日：2010-05-25
申请号：US12043091
申请日：2008-03-05
申请人： Hsung Jai Im , Sunhom Paak , Boon Yong Ang
发明人： Hsung Jai Im , Sunhom Paak , Boon Yong Ang
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C17/16
摘要： An integrated circuit includes an electronic fuse (“E-fuse”) cell having a fuse link and an E-fuse programming current generator. The fuse link has a width (FLw) and a thickness (FLT) and is fabricated from a layer of link material. An E-fuse programming current generator includes a reference link array having a plurality of reference links. Each of the reference links has the fuse link width and the fuse link thickness, and is fabricated from the layer of link material.
摘要翻译：集成电路包括具有熔丝链的电子熔丝（“E-fuse”）单元和E熔丝编程电流发生器。熔断体具有宽度（FLw）和厚度（FLT），并且由一层连接材料制成。电子熔丝编程电流发生器包括具有多个参考链路的参考链路阵列。每个参考链路具有熔丝链路宽度和熔丝链路厚度，并且由链路材料层制成。

10. 发明授权

US07294888B1 CMOS-compatible non-volatile memory cell with lateral inter-poly programming layer 有权
标题翻译： CMOS兼容非易失性存储单元，具有横向多层间编程层
公开(公告)号：US07294888B1
公开(公告)日：2007-11-13
申请号：US11240030
申请日：2005-09-30
申请人： Sunhom Paak , Boon Yong Ang , Hsung Jai Im , Daniel Gitlin
发明人： Sunhom Paak , Boon Yong Ang , Hsung Jai Im , Daniel Gitlin
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L21/28282 , G11C16/0466 , H01L29/66833
摘要： An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.
摘要翻译：使用标准CMOS制造工艺制造电可擦除可编程只读存储器（“CMOS NON-VOLATILE MEMORY”）单元。第一和第二多晶硅栅极在源极和漏极区域之间的电池的有源区域上被图案化。在多晶硅栅极上生长热氧化物以提供隔离层。氮化硅沉积在第一和第二多晶硅栅极之间以形成横向编程层。

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