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1. 发明申请

US20180248800A1 MEMORY DEVICE 审中-公开
公开(公告)号：US20180248800A1
公开(公告)日：2018-08-30
申请号：US15753826
申请日：2016-08-09
申请人： POCO-APOCO NETWORKS CO. LTD.
发明人： Kazunari INOUE
IPC分类号： H04L12/743 , G06F12/00 , G11C15/04 , H04L12/26
CPC分类号： H04L45/7453 , G06F12/00 , G06F12/0875 , G06F12/1483 , G11C15/00 , G11C15/04 , H04L43/026 , H04L43/12 , H04L45/7457 , H04L47/6215 , H04L49/109 , H04L49/557 , H04L49/9047
摘要： A memory device is configured as single chip to achieve routing control, bandwidth control, traffic monitoring, buffering, and access control of network functions. The memory device includes a search unit that includes a first memory unit and performs a search operation by searching, from the first memory unit, a piece of data corresponding to an input search key, a statistical information processing unit that includes a second memory unit that stores statistical information including the input search key, with which the piece of data has been successfully searched by the search unit, and an address of the piece of data in the first memory unit, and an arithmetic operation unit that updates the statistical information when the search unit successfully searches the pieces of data corresponding to the input search key.

2. 发明授权

US09870824B2 Iterator register for structured memory 有权
公开(公告)号：US09870824B2
公开(公告)日：2018-01-16
申请号：US15461262
申请日：2017-03-16
申请人： Intel Corporation
发明人： David R. Cheriton , Amin Firoozshahian , Alexandre Y. Solomatnikov
IPC分类号： G11C15/00
CPC分类号： G06F12/0811 , G06F12/0826 , G06F12/0862 , G06F2212/283 , G06F2212/602 , G06F2212/622 , G11C15/00
摘要： Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one or more pointer-linked data structures. One or more iterator registers are provided. A first pointer chain is loaded, having two or more pointers leading to a first element of a selected pointer-linked data structure to a selected iterator register. A second pointer chain is loaded, having two or more pointers leading to a second element of the selected pointer-linked data structure to the selected iterator register. The loading of the second pointer chain reuses portions of the first pointer chain that are common with the second pointer chain.Modifying data stored in a computer memory system is disclosed. A memory system is provided. One or more iterator registers are provided, wherein the iterator registers each include two or more pointer fields for storing two or more pointers that form a pointer chain leading to a data element. A local state associated with a selected iterator register is generated by performing one or more register operations relating to the selected iterator register and involving pointers in the pointer fields of the selected iterator register. A pointer-linked data structure is updated in the memory system according to the local state.

3. 发明申请

US20170337295A1 CONTENT ADDRESSABLE MEMORY (CAM) IMPLEMENTED TUPLE SPACES 审中-公开
公开(公告)号：US20170337295A1
公开(公告)日：2017-11-23
申请号：US15157982
申请日：2016-05-18
申请人： KnuEdge, Inc.
发明人： Ricardo Jorge Lopez , Ramon Zuniga , Robert Nicholas Hilton
IPC分类号： G06F17/30 , G06F3/06
CPC分类号： G06F3/0683 , G06F3/061 , G06F3/0647 , G11C15/00
摘要： A multi-processor system with a portion of content-addressable memory (CAM) configured as a tuple space to control data flow between processing element. A writing processor may write to a tuple space followed by a reading processor reading from the tuple space. However the system may control access to the tuple space so that no read operations may be performed for a particular tuple space before that space is written to. Further, no write operations may be performed to the tuple space prior to previous written data being read from the tuple space. A processor wishing to use the tuple space before being permitted to do so may be stalled, thus controlling data flow between operating processors.

4. 发明申请

US20170309341A1 METHODS OF OPERATING A MEMORY DEVICE COMPARING INPUT DATA TO DATA STORED IN MEMORY CELLS COUPLED TO A DATA LINE 审中-公开
公开(公告)号：US20170309341A1
公开(公告)日：2017-10-26
申请号：US15645009
申请日：2017-07-10
申请人： MICRON TECHNOLOGY, INC.
发明人： Kenneth J. Eldredge , Frankie F. Roohparvar , Luca De Santis , Tommaso Vali
IPC分类号： G11C16/28 , G11C15/00 , G11C15/04 , G11C16/04
CPC分类号： G11C16/28 , G11C15/00 , G11C15/046 , G11C16/0483
摘要： Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.

5. 发明申请

US20170285950A1 SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF 有权
公开(公告)号：US20170285950A1
公开(公告)日：2017-10-05
申请号：US15259262
申请日：2016-09-08
申请人： SK hynix Inc.
发明人： Hee Youl LEE
IPC分类号： G06F3/06
CPC分类号： G06F3/0679 , G06F3/061 , G06F3/064 , G11C7/1015 , G11C15/00 , G11C16/10 , G11C16/26
摘要： Provided herein is a semiconductor memory device and an operating method thereof. The semiconductor memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform a program operation or read operation on a selected memory block of the memory cell array. The control logic may select between a first program method and a second program method depending on program mode information for the selected memory block, and may control the peripheral circuit to perform the program operation on the selected memory block using the selected program method.

6. 发明授权

US09697899B1 Parallel deflate decoding method and apparatus 有权
公开(公告)号：US09697899B1
公开(公告)日：2017-07-04
申请号：US14977377
申请日：2015-12-21
申请人： Intel Corporation
发明人： Lokpraveen B. Mosur , Sailesh Bissessur , Pradnyesh S. Gudadhe , Quinn W. Merrell
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , H03M7/3086 , H03M7/4037 , H03M7/6005 , H03M7/6023
摘要： Described are apparatuses, methods and storage media associated with performing deflate decompression using multiple parallel content addressable memory cells.

7. 发明授权

US09659628B2 Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements 有权
公开(公告)号：US09659628B2
公开(公告)日：2017-05-23
申请号：US15228250
申请日：2016-08-04
申请人： III HOLDINGS 2, LLC
发明人： Michael C. Stephens, Jr.
IPC分类号： G11C11/4076 , G11C11/406 , G11C5/06 , G11C5/04 , G11C29/02 , G11C29/50 , G11C5/14 , G11C16/30 , G11C5/02 , G11C11/401 , G11C7/10 , G11C15/00 , G11C11/4093 , G11C11/4094 , G11C29/44 , G11C7/22
CPC分类号： G11C11/4076 , G11C5/02 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/14 , G11C5/147 , G11C7/10 , G11C7/106 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C11/4093 , G11C11/4094 , G11C15/00 , G11C16/30 , G11C29/023 , G11C29/028 , G11C29/50016 , G11C2029/4402 , G11C2211/4061 , G11C2211/4067 , G11C2213/71 , H01L2224/16145
摘要： Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

8. 发明授权

US09645904B2 Dynamic cache row fail accumulation due to catastrophic failure 有权
公开(公告)号：US09645904B2
公开(公告)日：2017-05-09
申请号：US15247239
申请日：2016-08-25
申请人： International Business Machines Corporation
发明人： Michael F. Fee , Patrick J. Meaney , Arthur J. O'Neill, Jr.
IPC分类号： G06F11/07 , G06F11/10 , G06F11/20 , G11C29/00 , G06F3/06 , G11C29/42 , G11C29/52 , G11C29/56 , G06F12/0811 , G06F12/084 , G06F12/0842 , H03M13/19 , G11C29/24 , G11C15/00 , G11C29/04
CPC分类号： G06F11/2094 , G06F3/0619 , G06F3/0653 , G06F3/0673 , G06F3/0679 , G06F11/07 , G06F11/0727 , G06F11/073 , G06F11/076 , G06F11/0763 , G06F11/0772 , G06F11/079 , G06F11/0793 , G06F11/1008 , G06F11/1024 , G06F11/1028 , G06F11/1048 , G06F11/106 , G06F11/1064 , G06F11/20 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F2201/805 , G06F2201/82 , G06F2201/85 , G06F2212/1032 , G11C15/00 , G11C29/00 , G11C29/24 , G11C29/42 , G11C29/52 , G11C29/56008 , G11C29/76 , G11C2029/0411 , H03M13/19
摘要： A technique is provided for accumulating failures. A failure of a first row is detected in a group of array macros, the first row having first row address values. A mask has mask bits corresponding to each of the first row address values. The mask bits are initially in active status. A failure of a second row, having second row address values, is detected. When none of the first row address values matches the second row address values, and when mask bits are all in the active status, the array macros are determined to be bad. When at least one of the first row address values matches the second row address values, mask bits that correspond to at least one of the first row address values that match are kept in active status, and mask bits that correspond to non-matching first address values are set to inactive status.

9. 发明申请

US20170092358A1 CONTENT ADDRESSABLE MEMORY WITH AN ORDERED SEQUENCE 有权
公开(公告)号：US20170092358A1
公开(公告)日：2017-03-30
申请号：US14863711
申请日：2015-09-24
申请人： International Business Machines Corporation
发明人： Samuel Scott ADAMS , Suparna BHATTACHARYA , Robert R. FRIEDLANDER , James R. KRAEMER
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , G11C15/04
摘要： A content addressable memory system, method and computer program product is described. The memory system comprises a location addressable store having data identified by location and multiple levels of content addressable stores each holding ternary content words. The content words are associated with references to data in the location addressable store and the content words containing at least one next entry bit for sorting content words in a physical ordered sequence to create content ordered memory. The content store levels might be implemented using different technologies that have different performance, capacity, and cost attributes. The memory system includes a content based cache for improved performance and a content addressable memory management unit for managing memory access operations and virtual memory addressing.

10. 发明授权

US09583191B1 CAM design for bit string lookup 有权
标题翻译： CAM设计用于位串查询
公开(公告)号：US09583191B1
公开(公告)日：2017-02-28
申请号：US14847020
申请日：2015-09-08
申请人： Cisco Technology, Inc.
发明人： IJsbrand Wijnands , Gregory J. Shepherd
IPC分类号： G11C15/04 , G11C15/00
CPC分类号： G11C15/00
摘要： In one embodiment, a programming content addressable memory (CAM) comprising at least one match line, the at least one match line being preloaded to high, and being logically OR-ed for all selector lines the at least one match line being inverted to low upon a match result the at least one match line comprising transistors and grounding which are activated only when a stored data value and a corresponding selector line evaluate to 1 and the corresponding selector line having a logical AND with the stored data value, wherein the programming CAM is implemented as a Bit Indexed Explicit Replication (BIER) table. Related apparatus, systems and methods are also described.
摘要翻译：在一个实施例中，编程内容可寻址存储器（CAM）包括至少一个匹配线，所述至少一个匹配线被预加载到高电平，并且对所有选择器线路进行逻辑或运算，所述至少一个匹配线被反转到低电平在匹配结果中，至少一个匹配线包括晶体管和接地，只有当存储的数据值和相应的选择器线求值为1并且相应的选择线与存储的数据值具有逻辑“与”时才被激活，其中编程CAM 被实现为位索引显式复制（BIER）表。还描述了相关装置，系统和方法。

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