专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08117577B1 Determining timing paths within a circuit block of a programmable integrated circuit 有权
标题翻译：确定可编程集成电路的电路块内的定时路径
公开(公告)号：US08117577B1
公开(公告)日：2012-02-14
申请号：US12361516
申请日：2009-01-28
申请人： Vasisht M. Vadi , Alvin Y. Ching , Subodh Kumar , Richard D. Freeman , Ian L. McEwen , Philip R. Haratsaris , Jaime D. Lujan , Eric M. Schwarz
发明人： Vasisht M. Vadi , Alvin Y. Ching , Subodh Kumar , Richard D. Freeman , Ian L. McEwen , Philip R. Haratsaris , Jaime D. Lujan , Eric M. Schwarz
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5054 , G06F17/5031 , G06F2217/84
摘要： A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a map file including a text description of each element within the block diagram, wherein the text description of each element specifies a bypass indicator for the element. The method also can include generating a plurality of sub-paths from the map file, determining timing paths from the plurality of sub-paths by selectively combining different ones of the plurality of sub-paths according to commonality of starting points and ending points of the plurality of sub-paths, and outputting the timing paths.
摘要翻译：识别电路块的定时路径的计算机实现的方法可以包括表示包括至少一个可旁路组件的电路块作为具有由节点链接的多个元件的框图。该方法可以包括生成包括框图中每个元素的文本描述的地图文件，其中每个元素的文本描述指定该元素的旁路指示符。该方法还可以包括从地图文件生成多个子路径，根据多个子路径的起始点和终点的共同点选择性地组合多个子路径中的不同子路径，从多个子路径确定定时路径多个子路径，并输出定时路径。

2. 发明授权

US07865542B2 Digital signal processing block having a wide multiplexer 有权
标题翻译：具有宽多路复用器的数字信号处理块
公开(公告)号：US07865542B2
公开(公告)日：2011-01-04
申请号：US11433120
申请日：2006-05-12
申请人： Bernard J. New , Vasisht Mantra Vadi , Jennifer Wong , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , James M. Simkins
发明人： Bernard J. New , Vasisht Mantra Vadi , Jennifer Wong , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , James M. Simkins
IPC分类号： G06F7/38
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.
摘要翻译：一种数字信号处理块，具有：1）第一数字信号处理元件，包括：第一多路复用器的第一多路复用器，所述第一多路复用器在第一数据输入和第一零常数输入之间进行选择; 以及耦合到所述第一多个复用器的第一算术单元，所述第一算术逻辑单元被配置为用于相加; 以及2）第二数字信号处理元件，包括：第二多路复用器的第二多路复用器，所述第二多路复用器在第二数据输入和第二零常数输入之间进行选择; 以及耦合到所述第二多路复用器的第二运算单元和所述第一多路复用器的第三多路复用器，所述第二运算单元被配置为相加。

3. 发明授权

US07849119B2 Digital signal processing circuit having a pattern detector circuit 有权
标题翻译：具有图案检测电路的数字信号处理电路
公开(公告)号：US07849119B2
公开(公告)日：2010-12-07
申请号：US11432846
申请日：2006-05-12
申请人： Vasisht Mantra Vadi , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , James M. Simkins
发明人： Vasisht Mantra Vadi , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , James M. Simkins
IPC分类号： G06F7/04
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： An integrated circuit for pattern detection including: an arithmetic logic unit coupled to a comparison circuit, where the arithmetic logic unit is programmed by an opcode; a selected pattern of a plurality of patterns selected by a first multiplexer, where the first multiplexer is coupled to the comparison circuit; and a register coupled to the comparison circuit for storing at least a partial comparison between an output of the arithmetic logic unit and the selected pattern.
摘要翻译：一种用于图案检测的集成电路，包括：耦合到比较电路的算术逻辑单元，其中算术逻辑单元由操作码编程; 由第一多路复用器选择的多个图案的选定图案，其中第一多路复用器耦合到比较电路; 以及耦合到所述比较电路的寄存器，用于存储所述算术逻辑单元的输出与所选择的模式之间的至少部分比较。

4. 发明申请

US20100191786A1 DIGITAL SIGNAL PROCESSING BLOCK WITH PREADDER STAGE 有权
标题翻译：数字信号处理块与前级
公开(公告)号：US20100191786A1
公开(公告)日：2010-07-29
申请号：US12360836
申请日：2009-01-27
申请人： James M. Simkins , Alvin Y. Ching , John M. Thendean , Vasisht M. Vadi , Chi Fung Poon , Muhammad Asim Rab
发明人： James M. Simkins , Alvin Y. Ching , John M. Thendean , Vasisht M. Vadi , Chi Fung Poon , Muhammad Asim Rab
IPC分类号： G06F5/01 , G06F7/50 , G06F9/38
CPC分类号： G06F7/5443 , H03H17/06 , H03H2220/04 , H03H2220/06 , H03K19/17732
摘要： A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a first input port of a first multiplexer coupled to the control bus; a second input port of a first logic gate coupled to the control bus; a third input port of a second logic gate coupled to the control bus; and a fourth input port of an adder/subtractor coupled to the control bus.
摘要翻译：描述了具有用于集成电路的前级的数字信号处理块。数字信号处理块包括一个前级和一个控制总线。控制总线耦合到前级，用于动态地控制前级的操作。前级级包括：耦合到控制总线的第一多路复用器的第一输入端口; 耦合到控制总线的第一逻辑门的第二输入端口; 耦合到控制总线的第二逻辑门的第三输入端口; 以及耦合到控制总线的加法器/减法器的第四输入端口。

5. 发明授权

US07564283B1 Automatic tap delay calibration for precise digital phase shift 有权
标题翻译：用于精确数字相移的自动抽头延迟校准
公开(公告)号：US07564283B1
公开(公告)日：2009-07-21
申请号：US10837059
申请日：2004-04-30
申请人： John D. Logue , Alvin Y. Ching , Wei Guang Lu
发明人： John D. Logue , Alvin Y. Ching , Wei Guang Lu
IPC分类号： H03L7/06 , H03H11/16
CPC分类号： G06F1/10 , H03L7/07 , H03L7/0814
摘要： An automatic calibration scheme is provided, which calibrates the equivalent taps per period ETT/P every time a delay lock loop is used. More specifically, a digital phase shifter is used to measure equivalent taps per period ETT/P. Alternately, the digital phase shifter is used to directly measure the signal delay through a clock phase shifter of the delay lock loop, thereby directly determining the high frequency and low frequency overhead constants.
摘要翻译：提供了一种自动校准方案，每次使用延迟锁定环时，校准每个ETT / P周期的等效抽头。更具体地说，数字移相器用于测量ETT / P周期的等效抽头。或者，数字移相器用于通过延迟锁定环路的时钟移相器直接测量信号延迟，从而直接确定高频和低频开销常数。

6. 发明授权

US07472155B2 Programmable logic device with cascading DSP slices 有权
标题翻译：具有级联DSP片的可编程逻辑器件
公开(公告)号：US07472155B2
公开(公告)日：2008-12-30
申请号：US11019783
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/38
CPC分类号： H03K19/17736 , G06F15/7867 , H03K19/17732
摘要： Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.
摘要翻译：描述了可编程逻辑器件（PLD），其具有可以级联的DSP片段，以创建不同大小和复杂度的DSP电路。每个DSP片包括多个操作数输入端口和片输出端口，所有这些端口都可编程地连接到通用路由和逻辑资源。操作数端口接收处理的操作数，切片输出端口传送处理结果。每个切片还包括连接到相应切片输出端口的反馈端口，以支持在该实施例中的累积功能，以及连接到上游切片的输出端口以支持级联的级联输入端口。

7. 发明授权

US07467175B2 Programmable logic device with pipelined DSP slices 有权
标题翻译：可编程逻辑器件，带流水线DSP片
公开(公告)号：US07467175B2
公开(公告)日：2008-12-16
申请号：US11019782
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/38
CPC分类号： H03K19/17736 , H03K19/17732
摘要： Described is a programmable logic device (PLD) with columns of DSP slices that can be combined to create DSP circuits of varying size and complexity. DSP slices in accordance with some embodiments includes programmable operand input registers that can be configured to introduce different amounts of delay, from zero to two clock cycles, for example, to support pipelining. In one such embodiment, each DSP slice includes a partial-product generator having a multiplier port, a multiplicand port, and a product port. The multiplier and multiplicand ports connect to the operand input port via respective first and second operand input registers, each of which is capable of introducing from zero to two clock cycles of delay. In another embodiment, the output of at least one operand input register can connect to the input of an operand input register of a downstream DSP slice so that operands can be transferred among one or more slices.
摘要翻译：描述了可编程逻辑器件（PLD），其具有可以组合的DSP片段，以创建不同大小和复杂度的DSP电路。根据一些实施例的DSP片段包括可被配置为从零到两个时钟周期引入不同量的延迟的可编程操作数输入寄存器，例如以支持流水线化。在一个这样的实施例中，每个DSP片包括具有乘法器端口，被乘数端口和产品端口的部分乘积生成器。乘法器和被乘数端口通过相应的第一和第二操作数输入寄存器连接到操作数输入端口，每个第一和第二操作数输入寄存器能够从零延迟到两个延迟的时钟周期。在另一个实施例中，至少一个操作数输入寄存器的输出可以连接到下游DSP片的操作数输入寄存器的输入，使得操作数可以在一个或多个片之间传送。

8. 发明授权

US08495122B2 Programmable device with dynamic DSP architecture 有权
标题翻译：具有动态DSP架构的可编程器件
公开(公告)号：US08495122B2
公开(公告)日：2013-07-23
申请号：US11019735
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/38
CPC分类号： H03K19/17736 , H03K19/17732
摘要： Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each slice includes a mode port that receives mode control signals for dynamically altering the function and connectivity of related slices. Such alterations can occur with or without reconfiguring the PLD.
摘要翻译：描述了可编程逻辑器件（PLD），其具有可以级联的DSP片段，以创建不同大小和复杂度的DSP电路。每个片包括一个模式端口，它接收模式控制信号，用于动态地改变相关片段的功能和连通性。这种改变可以在或不配置PLD的情况下发生。

9. 发明授权

US07882165B2 Digital signal processing element having an arithmetic logic unit 有权
标题翻译：具有算术逻辑单元的数字信号处理单元
公开(公告)号：US07882165B2
公开(公告)日：2011-02-01
申请号：US11408364
申请日：2006-04-21
申请人： James M. Simkins , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi , David P. Schultz
发明人： James M. Simkins , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi , David P. Schultz
IPC分类号： G06F7/38
CPC分类号： G06K9/00986 , G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , H03K19/1737
摘要： A digital signal processing circuit including: a multiplier circuit; a plurality of multiplexers coupled to the multiplier circuit and controlled by a first opcode; and an arithmetic logic unit coupled to plurality of multiplexers and controlled by a second opcode.
摘要翻译：一种数字信号处理电路，包括：乘法器电路; 耦合到所述乘法电路并由第一操作码控制的多个多路复用器; 以及耦合到多个多路复用器并由第二操作码控制的算术逻辑单元。

10. 发明授权

US07417918B1 Method and apparatus for configuring the operating speed of a programmable logic device through a self-timed reference circuit 有权
标题翻译：用于通过自定时参考电路配置可编程逻辑器件的工作速度的方法和装置
公开(公告)号：US07417918B1
公开(公告)日：2008-08-26
申请号：US10954927
申请日：2004-09-29
申请人： Eunice Y. D. Hao , Tony K. Ngai , Jennifer Wong , Alvin Y. Ching
发明人： Eunice Y. D. Hao , Tony K. Ngai , Jennifer Wong , Alvin Y. Ching
IPC分类号： G11C8/18
CPC分类号： G11C29/02 , G11C11/41 , G11C29/023 , G11C29/028 , H03K19/17748 , H03K19/17764 , H03K19/17792
摘要： Method and apparatus for configuring a programmable logic device to operate at a plurality of clock frequencies comprising configurable programmable self-timed delay circuits and associated configuration software. The configurable IC clock frequencies increase device performance and manufacturing yield.
摘要翻译：用于配置可编程逻辑器件以在多个时钟频率下操作的方法和装置，包括可配置可编程自定时延迟电路和相关配置软件。可配置的IC时钟频率提高了器件性能和制造产量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式