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1. 发明授权

US06441641B1 Programmable logic device with partial battery backup 有权
标题翻译：具有部分电池备份的可编程逻辑器件
公开(公告)号：US06441641B1
公开(公告)日：2002-08-27
申请号：US09724735
申请日：2000-11-28
申请人： Raymond C. Pang , Venu M. Kondapalli , Jane W. Sowards , Scott O. Frake , Jennifer Wong , F. Erich Goetting , Peter H. Alfke , Schuyler E. Shimanek
发明人： Raymond C. Pang , Venu M. Kondapalli , Jane W. Sowards , Scott O. Frake , Jennifer Wong , F. Erich Goetting , Peter H. Alfke , Schuyler E. Shimanek
IPC分类号： H01L2500
CPC分类号： G06F21/76
摘要： A PLD can be manufactured to include power supply lines from two sources so that a portion of the PLD can be backed up with a battery when power to the PLD is removed. A switch that supplies power to the backed up portion of the PLD receives power from both an external power supply and from the battery, and detects voltage level of the external power supply, switching to battery power when voltage from the external power supply is not sufficient.
摘要翻译：可以制造PLD以包括来自两个源的电源线，使得当PLD的电源被去除时，一部分PLD可以用电池备份。向PLD的备用部分供电的开关从外部电源和电池两者接收电力，并检测外部电源的电压，当来自外部电源的电压不足时切换到电池电力。

2. 发明授权

US5958026A Input/output buffer supporting multiple I/O standards 失效
标题翻译：输入/输出缓冲器支持多种I / O标准
公开(公告)号：US5958026A
公开(公告)日：1999-09-28
申请号：US837022
申请日：1997-04-11
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli
IPC分类号： H03K19/0175 , H03K19/0185 , G06F13/00
CPC分类号： H03K19/018585 , H03K19/017581
摘要： The invention comprises a configurable input/output buffer for an FPGA that can be configured to comply with any of two or more different I/O standards. Factors such as output drive strength, receiver type, output driver type, and output signal slew rate are configurably controlled. In some embodiments, the input power supply and the output power supply can be different from the core voltage supply. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad are configurably connected to the input reference voltage line. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage or a single output voltage supply is applied to each Input/Output Block (IOB), with IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.
摘要翻译：本发明包括用于FPGA的可配置输入/输出缓冲器，其可以被配置为符合两个或更多个不同I / O标准中的任何一个。可配置控制输出驱动强度，接收器类型，输出驱动器类型，输出信号转换速率等因素。在一些实施例中，输入电源和输出电源可以不同于核心电压源。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘可配置地连接到输入参考电压线。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。根据本发明的另一方面，将单个输入参考电压或单个输出电压电源施加到每个输入/输出块（IOB），其中IOB被分组成集合。每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

3. 发明授权

US06204695B1 Clock-gating circuit for reducing power consumption 有权
标题翻译：时钟门控电路，用于降低功耗
公开(公告)号：US06204695B1
公开(公告)日：2001-03-20
申请号：US09336357
申请日：1999-06-18
申请人： Peter H. Alfke , Alvin Y. Ching , Scott O. Frake , Jennifer Wong , Steven P. Young
发明人： Peter H. Alfke , Alvin Y. Ching , Scott O. Frake , Jennifer Wong , Steven P. Young
IPC分类号： H03H19096
CPC分类号： G06F1/10
摘要： A clock gating circuit is provided for a logic device that reduces device resource requirements, eliminates the need for users to define their own clock gating circuit, and eliminates undesirable clock signal disturbances, such as glitches and runt pulses. In one embodiment, the clock gating circuit includes an input terminal for receiving an input clock signal; an input terminal for receiving a clock enable signal; a storage latch coupled to receive the input clock signal and the clock enable signal, and in response, provide a clock gate control signal; and a logic gate coupled to receive the input clock signal and the clock gate control signal. The logic gate selectively routes the input clock signal in response to the clock gate control signal, thereby providing an output clock signal.
摘要翻译：为逻辑器件提供时钟选通电路，可降低器件资源需求，消除用户定义自己的时钟选通电路的需要，并消除不期望的时钟信号干扰，如毛刺和欠压脉冲。在一个实施例中，时钟选通电路包括用于接收输入时钟信号的输入端; 用于接收时钟使能信号的输入端; 存储锁存器，其耦合以接收所述输入时钟信号和所述时钟使能信号，并且作为响应，提供时钟门控制信号; 以及耦合以接收输入时钟信号和时钟门控制信号的逻辑门。逻辑门选择地响应于时钟门控制信号路由输入时钟信号，由此提供输出时钟信号。

4. 发明授权

US06204691B1 FPGA with a plurality of input reference voltage levels grouped into sets 有权
标题翻译： FPGA具有多个输入参考电压电平分组成组
公开(公告)号：US06204691B1
公开(公告)日：2001-03-20
申请号：US09569745
申请日：2000-05-11
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
IPC分类号： H03K19094
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.
摘要翻译：本发明包括具有多个输入参考电压和/或输出电压源的FPGA。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

5. 发明授权

US06366117B1 Nonvolatile/battery-backed key in PLD 有权
标题翻译： PLD中的非易失性/电池供电密钥
公开(公告)号：US06366117B1
公开(公告)日：2002-04-02
申请号：US09724973
申请日：2000-11-28
申请人： Raymond C. Pang , Jennifer Wong , Scott O. Frake , Jane W. Sowards , Venu M. Kondapalli , F. Erich Goetting , Stephen M. Trimberger , Kameswara K. Rao
发明人： Raymond C. Pang , Jennifer Wong , Scott O. Frake , Jane W. Sowards , Venu M. Kondapalli , F. Erich Goetting , Stephen M. Trimberger , Kameswara K. Rao
IPC分类号： H04L900
CPC分类号： G06F21/76
摘要： It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, the encrypted design is decrypted by a key or keys within the PLD that are preserved when power is removed by either being stored in nonvolatile memory or by being backed up with a battery that switches into operation when the power is removed from the PLD.
摘要翻译：有时期望加密设计以加载到PLD中，使得攻击者可能不会在将设计复制到PLD中时学习和复制设计。根据本发明，加密设计由PLD内的密钥或密钥解密，当通过存储在非易失性存储器中的电力被去除或通过在电力被从 PLD。

6. 发明授权

US5764564A Write-assisted memory cell and method of operating same 失效
标题翻译：写辅助存储单元及其操作方法
公开(公告)号：US5764564A
公开(公告)日：1998-06-09
申请号：US814248
申请日：1997-03-11
申请人： Scott O. Frake , Philip D. Costello
发明人： Scott O. Frake , Philip D. Costello
IPC分类号： G11C11/412 , G11C11/00
CPC分类号： G11C11/412
摘要： For a memory cell comprising a latch with cross-coupled inverters and an n-channel access transistor, the inverter that can contend with the access transistor is connected not between power and ground but between power and a transistor that disconnects the inverter from ground when the memory cell is being written. This allows transistors in the memory cell to be small and still function properly, without requiring that a port be provided for the complement of the data signal. The invention is important when there are several write ports to the memory cell and the addressing overhead is significant.
摘要翻译：对于包括具有交叉耦合的反相器的锁存器和n沟道存取晶体管的存储器单元，可以与存取晶体管相抗衡的反相器不是连接在电源和地之间，而是连接在功率与晶体管之间，当晶体管与地内存单元正在写入。这允许存储器单元中的晶体管小并且仍然正常工作，而不需要为数据信号的补码提供端口。当存在存储单元的多个写入端口并且寻址开销很大时，本发明是重要的。

7. 发明授权

US06526466B1 Method and system for PLD swapping 有权
标题翻译： PLD交换的方法和系统
公开(公告)号：US06526466B1
公开(公告)日：2003-02-25
申请号：US09438220
申请日：1999-11-12
申请人： Scott O. Frake , James L. McManus , David P. Schultz , Wilson K. Yee
发明人： Scott O. Frake , James L. McManus , David P. Schultz , Wilson K. Yee
IPC分类号： G06F1300
CPC分类号： G06F13/4081
摘要： An apparatus and method for enabling hot swapping of programmable logic devices (PLDs) and boards containing PLDs is provided. If the hot swap capability is desired, a hot swap terminal on the PLD is set to facilitate a floating state on the input/output pad of the PLD. Further, the input buffer and the output buffer of the PLD are disabled. In one embodiment, a predetermined voltage is provided on the output terminal of the input buffer. In this configuration, the hot swap circuit eliminates any leakage current, ensures no static current occurs, and provides appropriate signals to the internal circuits of the PLD.
摘要翻译：提供了一种用于实现可编程逻辑器件（PLD）和包含PLD的板的热插拔的装置和方法。如果需要热插拔功能，则PLD上的热插拔端子被设置为便于PLD的输入/输出焊盘上的浮动状态。此外，PLD的输入缓冲器和输出缓冲器被禁用。在一个实施例中，在输入缓冲器的输出端上提供预定电压。在这种配置中，热插拔电路消除了任何漏电流，确保不发生静电流，并向PLD的内部电路提供适当的信号。

8. 发明授权

US06448809B2 FPGA with a plurality of input reference voltage levels 有权
标题翻译： FPGA具有多个输入参考电压电平
公开(公告)号：US06448809B2
公开(公告)日：2002-09-10
申请号：US09924356
申请日：2001-08-07
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
IPC分类号： G06F738
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.
摘要翻译：本发明包括具有多个输入参考电压和/或输出电压源的FPGA。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

9. 发明授权

US6049227A FPGA with a plurality of I/O voltage levels 有权
标题翻译：具有多个I / O电压电平的FPGA
公开(公告)号：US6049227A
公开(公告)日：2000-04-11
申请号：US187666
申请日：1998-11-05
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
IPC分类号： G06F7/38 , H03K19/003 , H03K19/094 , H03K19/177 , H03K19/0175 , H03K19/082
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.
摘要翻译：本发明包括具有多个输入参考电压和/或输出电压源的FPGA。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

10. 发明授权

US5166858A Capacitor formed in three conductive layers 失效
标题翻译：电容器形成在三个导电层
公开(公告)号：US5166858A
公开(公告)日：1992-11-24
申请号：US785391
申请日：1991-10-30
申请人： Scott O. Frake , Roger D. Carpenter
发明人： Scott O. Frake , Roger D. Carpenter
IPC分类号： H01L27/08
CPC分类号： H01L27/0805
摘要： A capacitor is formed in three adjacent conductive layers of a semiconductor integrated circuit chip. A first plate of the capacitor is formed in the middle layer. A second plate is formed in the upper and lower layers plus a small portion of the middle layer which interconnects the upper and lower layers and forms a U-shaped structure surrounding the first plate. These capacitors are preferably formed in pairs with the first plates interconnected. The second plates may be connected to different voltage supplies to form a capacitive voltage divider.
摘要翻译：在半导体集成电路芯片的三个相邻的导电层中形成电容器。电容器的第一板形成在中间层中。第二板形成在上层和下层加上中间层的小部分，其互连上层和下层并形成围绕第一板的U形结构。这些电容器优选地与互连的第一板成对地形成。第二板可以连接到不同的电压源以形成电容分压器。

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