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1. 发明授权

US07345507B1 Multi-product die configurable as two or more programmable integrated circuits of different logic capacities 有权
标题翻译：多产品管芯可配置为具有不同逻辑容量的两个或多个可编程集成电路
公开(公告)号：US07345507B1
公开(公告)日：2008-03-18
申请号：US11333991
申请日：2006-01-17
申请人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
发明人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
IPC分类号： H01L25/00
CPC分类号： H03K19/177
摘要： A multi-product integrated circuit die includes at least two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A selection code storage circuit stores a product selection code. A first value of the product selection code selects the option where both the first and second portions of the first die are operational. A second value of the product selection code selects the option where only the first portion of the first die is operational. The selection code storage circuit can include non-volatile memory or a fuse structure, or the product selection code can be configured as a package bonding option. The product selection code can also enable boundary scan for the operational portion of the die, and omit from the boundary scan chain any portions of the die that are deliberately rendered non-operational.
摘要翻译：多产品集成电路管芯包括至少两个不同的部分，其中至少一个部分可以以某种方式（例如，非功能的，不可访问的和/或不可编程的）被故意地变为不可操作的。选择码存储电路存储产品选择码。产品选择代码的第一个值选择第一模具的第一和第二部分都可操作的选项。产品选择代码的第二个值选择仅第一个模具的第一部分可操作的选项。选择代码存储电路可以包括非易失性存储器或熔丝结构，或者可以将产品选择代码配置为封装绑定选项。产品选择代码还可以为模具的操作部分启用边界扫描，并且从边界扫描链中省略故意使其不可操作的模具的任何部分。

2. 发明授权

US07491576B1 Yield-enhancing methods of providing a family of scaled integrated circuits 有权
标题翻译：提供一系列缩放集成电路的产量增强方法
公开(公告)号：US07491576B1
公开(公告)日：2009-02-17
申请号：US11333990
申请日：2006-01-17
申请人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
发明人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
IPC分类号： H01L21/66 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L22/22 , H01L23/544 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit die (e.g., a programmable logic device (PLD) die) is manufactured that has the capability of being configured as at least two differently-sized family members. The IC die is tested prior to packaging. If a first portion of the IC die is fully functional, but a second portion includes a localized defect, then the IC die is packaged with a product selection code that configures the IC die to operate as only the first portion of the die. The second portion of the die is deliberately rendered non-operational. Therefore, the IC die can still be sold as a fully functional packaged IC.
摘要翻译：制造集成电路管芯（例如，可编程逻辑器件（PLD）管芯），其具有被配置为至少两个不同尺寸的家庭部件的能力。在封装之前测试IC芯片。如果IC芯片的第一部分是完全功能的，但是第二部分包括局部缺陷，则IC芯片被封装成产品选择代码，所述产品选择代码构成IC裸片仅作为芯片的第一部分进行操作。死亡的第二部分故意使其不能运作。因此，IC芯片仍然可以作为全功能封装IC出售。

3. 发明授权

US07402443B1 Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes 有权
标题翻译：使用产品选择代码为集成电路系列提供类似模具的方法部分禁用
公开(公告)号：US07402443B1
公开(公告)日：2008-07-22
申请号：US11333819
申请日：2006-01-17
申请人： Raymond C. Pang , Trevor J. Bauer , F. Erich Goetting , Bruce E. Talley , Steven P. Young
发明人： Raymond C. Pang , Trevor J. Bauer , F. Erich Goetting , Bruce E. Talley , Steven P. Young
IPC分类号： G01R31/26
CPC分类号： H01L27/11807 , H01L27/0207
摘要： A method of providing a family of integrated circuits (ICs) includes applying a first product selection code (PSC) to a first IC die, applying a second PSC to a second IC die, and providing a third packaged IC die. The first IC die includes first and second portions, both of which are operational based on the first PSC. The second IC die is a duplicate of the first die, but the second portion is rendered non-operational by the second PSC. The third IC die is substantially similar to the first portion of the first die. The second and third packages can be the same and the packaged dies can be interchangeable in a system. When the dies are programmable logic device (PLD) dies, the second and third dies use the same configuration bit stream, which may be smaller than the configuration bit stream for the first IC die.
摘要翻译：提供集成电路（IC）系列的方法包括：将第一产品选择代码（PSC）应用于第一IC芯片，将第二PSC应用于第二IC芯片，以及提供第三封装IC芯片。第一IC芯片包括第一和第二部分，它们都基于第一PSC而可操作。第二IC芯片是第一裸片的副本，但是第二部分由第二PSC不可操作。第三IC管芯基本上类似于第一管芯的第一部分。第二和第三包可以是相同的，并且包装的模具可以在系统中互换。当管芯是可编程逻辑器件（PLD）管芯时，第二和第三管芯使用与第一IC管芯的配置位流相同的配置位流。

4. 发明授权

US08001511B1 Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies 有权
标题翻译：在多产品可编程IC芯片的可选边界实现和建模互连线路的方法
公开(公告)号：US08001511B1
公开(公告)日：2011-08-16
申请号：US12245858
申请日：2008-10-06
申请人： Trevor J. Bauer , Jeffrey V. Lindholm , F. Erich Goetting , Bruce E. Talley , Ramakrishna K. Tanikella , Steven P. Young
发明人： Trevor J. Bauer , Jeffrey V. Lindholm , F. Erich Goetting , Bruce E. Talley , Ramakrishna K. Tanikella , Steven P. Young
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： H03K19/177 , G06F17/5054 , G06F17/5068
摘要： A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second portion non-operational. At a boundary between the two portions, interconnect lines traversing the boundary include a first section in the first portion and a second section in the second portion. The second PLD die includes the first portion of the first PLD die, while omitting the second portion. The interconnect lines extending to the edge of the second die are coupled together in pairs. A software model for both die includes a termination model that omits the pair coupling, adds an RC load compensating for the omitted connection, and (for bidirectional interconnect lines) flags one interconnect line in each pair as being invalid for use by routing software.
摘要翻译：使用相同的软件模型对两个IC芯片建模的方法，尽管两个芯片包括物理差异。第一可编程逻辑器件（PLD）管芯包括第一和第二部分，并被编码以使第一部分可操作，第二部分不可操作。在两部分之间的边界处，穿过边界的互连线包括第一部分中的第一部分和第二部分中的第二部分。第二PLD管芯包括第一PLD管芯的第一部分，同时省略第二部分。延伸到第二管芯边缘的互连线成对连接在一起。两个芯片的软件模型包括一个省略对耦合的终端模型，增加了对省略连接进行补偿的RC负载，以及（对于双向互连线），标记每对中的一条互连线，因为无法使用路由软件。

5. 发明授权

US07498192B1 Methods of providing a family of related integrated circuits of different sizes 有权
标题翻译：提供不同尺寸的相关集成电路系列的方法
公开(公告)号：US07498192B1
公开(公告)日：2009-03-03
申请号：US11334341
申请日：2006-01-17
申请人： F. Erich Goetting , Trevor J. Bauer , Patrick J. McGuire , Bruce E. Talley , Paul Ying-Fung Wu , Steven P. Young
发明人： F. Erich Goetting , Trevor J. Bauer , Patrick J. McGuire , Bruce E. Talley , Paul Ying-Fung Wu , Steven P. Young
IPC分类号： H01L21/44
CPC分类号： H01L23/00 , H01L2924/0002 , H01L2924/00
摘要： Methods of manufacturing a family of packaged integrated circuits (ICs) having at least two different logic capacities. A first IC die includes two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A first set of the first IC dies are packaged such that both portions of the dies are operational. A second set of the first IC dies are packaged such that only the first portion of each die is operational. Once the first and second sets are packaged and the second set of ICs has been evaluated, a decision is made whether or not to manufacture a second IC die that includes the first portion of the first die, while excluding the second portion.
摘要翻译：制造具有至少两个不同逻辑容量的封装集成电路（IC）系列的方法。第一IC芯片包括两个不同的部分，其中至少一个部分可以以某种方式（例如，非功能的，不可访问的和/或不可编程的）被故意地变为不可操作的。第一组第一IC芯片被封装成使得模具的两个部分都可操作。封装第一组IC芯片，使得只有每个裸片的第一部分可操作。一旦封装了第一组和第二组，并且已经评估了第二组IC，则决定是否制造包括第一模具的第一部分的第二IC模具，同时排除第二部分。

6. 发明授权

US07451421B1 Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies 有权
标题翻译：在多产品可编程IC芯片的可选边界实现和建模互连线路的方法
公开(公告)号：US07451421B1
公开(公告)日：2008-11-11
申请号：US11333865
申请日：2006-01-17
申请人： Trevor J. Bauer , Jeffrey V. Lindholm , F. Erich Goetting , Bruce E. Talley , Ramakrishna K. Tanikella , Steven P. Young
发明人： Trevor J. Bauer , Jeffrey V. Lindholm , F. Erich Goetting , Bruce E. Talley , Ramakrishna K. Tanikella , Steven P. Young
IPC分类号： G06F9/455 , G06F17/50 , H03K19/173 , H03K19/177
CPC分类号： H03K19/177 , G06F17/5054 , G06F17/5068
摘要： A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second portion non-operational. At a boundary between the two portions, interconnect lines traversing the boundary include a first section in the first portion and a second section in the second portion. The second PLD die includes the first portion of the first PLD die, while omitting the second portion. The interconnect lines extending to the edge of the second die are coupled together in pairs. A software model for both die includes a termination model that omits the pair coupling, adds an RC load compensating for the omitted connection, and (for bidirectional interconnect lines) flags one interconnect line in each pair as being invalid for use by routing software.
摘要翻译：使用相同的软件模型对两个IC芯片建模的方法，尽管两个芯片包括物理差异。第一可编程逻辑器件（PLD）管芯包括第一和第二部分，并被编码以使第一部分可操作，第二部分不可操作。在两部分之间的边界处，穿过边界的互连线包括第一部分中的第一部分和第二部分中的第二部分。第二PLD管芯包括第一PLD管芯的第一部分，同时省略第二部分。延伸到第二管芯边缘的互连线成对连接在一起。两个芯片的软件模型包括一个省略对耦合的终端模型，增加了对省略连接进行补偿的RC负载，以及（对于双向互连线），标记每对中的一条互连线，因为无法使用路由软件。

7. 发明授权

US06282127B1 Block RAM with reset to user selected value 有权
标题翻译：将RAM重置为用户选择的值
公开(公告)号：US06282127B1
公开(公告)日：2001-08-28
申请号：US09625672
申请日：2000-07-24
申请人： Raymond C. Pang , Steven P. Young , Trevor J. Bauer
发明人： Raymond C. Pang , Steven P. Young , Trevor J. Bauer
IPC分类号： G11C700
CPC分类号： G11C7/1051 , G11C7/1057
摘要： A RAM block includes a circuit for causing the RAM to provide a reset value on the output or a previously captured output value from the RAM when a Reset signal is active. The Reset signal does not change the RAM contents but causes all outputs of the block RAM to be either a reset value or a capture value, as selected by the user. This is useful when the RAM block is configured as a state machine. Thus, in an FPGA or other programmable device, an application can start the state machine in a known state with all address bits equal to 0 and can reset the state machine to this startup state. When the reset signal is active, the state machine can feed back the reset value or capture value to the address inputs of the RAM block that receive state feedback data, regardless of the data actually in those locations.
摘要翻译： RAM块包括用于当复位信号有效时使RAM在输出上提供复位值或从RAM提供先前捕获的输出值的电路。复位信号不会更改RAM内容，但会导致块RAM的所有输出为用户选择的复位值或捕捉值。当RAM块被配置为状态机时，这是有用的。因此，在FPGA或其他可编程器件中，应用程序可以在所有地址位等于0的已知状态下启动状态机，并可将状态机复位到该启动状态。当复位信号有效时，状态机可以将接收状态反馈数据的复位值或捕获值反馈给RAM块的地址输入，无论这些位置中的数据如何。

8. 发明授权

US06346825B1 Block RAM with configurable data width and parity for use in a field programmable gate array 有权
标题翻译：块RAM具有可配置的数据宽度和奇偶校验，用于现场可编程门阵列
公开(公告)号：US06346825B1
公开(公告)日：2002-02-12
申请号：US09680205
申请日：2000-10-06
申请人： Raymond C. Pang , Steven P. Young , Trevor J. Bauer
发明人： Raymond C. Pang , Steven P. Young , Trevor J. Bauer
IPC分类号： H03K19177
CPC分类号： H03K19/1776
摘要： A dedicated block random access memory (RAM) is provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA). The block RAM includes a memory cell array and control logic that is configurable to select one of a plurality of parity or non-parity modes for accessing the memory cell array. In one embodiment, the non-parity modes include a 1×16384 mode, a 2×8192 mode, and a 4×4096 mode, while the parity modes include a 9×2048 mode, a 18×1024 mode and an 36×512 mode. The control logic selects the parity/non-parity mode in response to configuration bits stored in corresponding configuration memory cells of the PLD. The configuration bits are programmed during configuration of the PLD. In one variation, the control logic selects the parity/non-parity mode in response to user signals. In a particular embodiment, the block RAM is a dual-port memory having a first port and a second port. In this embodiment, the first and second ports can be independently configured to have different (or the same) parity or non-parity modes.
摘要翻译：为诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）提供专用块随机存取存储器（RAM）。块RAM包括存储单元阵列和控制逻辑，可配置为选择用于访问存储单元阵列的多个奇偶校验或非奇偶校验模式之一。在一个实施例中，非奇偶校验模式包括1x16384模式，2x8192模式和4×4096模式，而奇偶校验模式包括9×2048模式，18×1024模式和36×512模式。响应于存储在PLD的相应配置存储器单元中的配置位，控制逻辑选择奇偶校验/非奇偶校验模式。在配置PLD期间对配置位进行编程。在一个变化中，控制逻辑响应于用户信号选择奇偶校验/非奇偶校验模式。在特定实施例中，块RAM是具有第一端口和第二端口的双端口存储器。在该实施例中，第一和第二端口可以被独立地配置为具有不同的（或相同的）奇偶校验或非奇偶校验模式。

9. 发明授权

US06204691B1 FPGA with a plurality of input reference voltage levels grouped into sets 有权
标题翻译： FPGA具有多个输入参考电压电平分组成组
公开(公告)号：US06204691B1
公开(公告)日：2001-03-20
申请号：US09569745
申请日：2000-05-11
申请人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
发明人： F. Erich Goetting , Scott O. Frake , Venu M. Kondapalli , Steven P. Young
IPC分类号： H03K19094
CPC分类号： H03K19/17744 , H03K19/00361 , H03K19/1778 , H03K19/17788
摘要： The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.
摘要翻译：本发明包括具有多个输入参考电压和/或输出电压源的FPGA。在一个实施例中，同一可配置输入缓冲器中的两个或多个差分放大器使用不同的输入参考电压。根据本发明的第二方面，I / O焊盘线可配置地连接到输入参考电压线，使得可以使用任何可配置的输入/输出块（IOB）来提供输入参考电压。根据本发明的第三方面，I / O的参考输入可配置地连接到两个或更多个输入参考电压线中的任一个。根据本发明的另一方面，将单个输入参考电压和/或单个输出电压电源应用于每个IOB，其中IOB被分组成组。每组IOB具有单独的输入参考电压和/或单独的输出电压电源。

10. 发明授权

US06775342B1 Digital phase shifter 有权
标题翻译：数字移相器
公开(公告)号：US06775342B1
公开(公告)日：2004-08-10
申请号：US09684540
申请日：2000-10-06
申请人： Steven P. Young , John D. Logue , Andrew K. Percey , F. Erich Goetting , Alvin Y. Ching
发明人： Steven P. Young , John D. Logue , Andrew K. Percey , F. Erich Goetting , Alvin Y. Ching
IPC分类号： H04L2500
CPC分类号： H03L7/0814 , G06F1/10 , H03L7/07
摘要： After a delay lock loop synchronizes a reference clock signal with a skewed clock signal, a digital phase shifter can be used to shift the skewed clock signal by a small amount with respect to the reference clock signal. The tap/trim settings of a delay line in the main path of the delay lock loop can be transmitted to the digital phase shifter, thereby informing the digital phase shifter of the period of the reference clock signal. In response, the digital phase shifter provides a phase control signal that introduces a delay, which is referenced to the period of the reference clock signal, to either the reference clock signal or the skew clock signal. The phase control signal is proportional to a predetermined fraction of the period of the reference clock signal. The digital phase shifter can be controlled to operate in several modes. In a first fixed mode, the digital phase shifter introduces delay to the skew clock signal. In a second fixed mode, the digital phase shifter introduces delay to the reference clock signal. In a first variable mode, the digital phase shifter can cause the reference clock signal to lead or lag the skew clock signal by controlling the delay of the reference clock signal. In a second variable mode, the digital phase shifter can cause the reference clock signal to lead or lag the skew clock signal by controlling the delay of the skew clock signal.
摘要翻译：在延迟锁定环路使参考时钟信号与偏斜时钟信号同步之后，数字移相器可用于相对于参考时钟信号将偏斜的时钟信号移位一小段量。在延迟锁定环路的主路径上的延迟线的抽头/微调设置可被发送到数字移相器，由此通知数字移相器参考时钟信号的周期。作为响应，数字移相器提供相位控制信号，其将参考时钟信号的周期的延迟引入参考时钟信号或偏斜时钟信号。相位控制信号与参考时钟信号的周期的预定分数成比例。数字移相器可以控制在多种模式下工作。在第一固定模式中，数字移相器将延迟引入到偏斜时钟信号。在第二固定模式中，数字移相器将延迟引入参考时钟信号。在第一可变模式中，数字移相器可以通过控制参考时钟信号的延迟来引起参考时钟信号引导或延迟偏斜时钟信号。在第二可变模式中，数字移相器可以通过控制偏斜时钟信号的延迟来引起参考时钟信号引导或延迟偏斜时钟信号。

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