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1. 发明授权

US06933219B1 Tightly spaced gate formation through damascene process 有权
标题翻译：通过镶嵌工艺紧密间隔的浇口形成
公开(公告)号：US06933219B1
公开(公告)日：2005-08-23
申请号：US10716209
申请日：2003-11-18
申请人： Emmanuil H. Lingunis , Krishnashree Achuthan , Minh Van Ngo , Cyrus Tabery , Jean Y. Yang
发明人： Emmanuil H. Lingunis , Krishnashree Achuthan , Minh Van Ngo , Cyrus Tabery , Jean Y. Yang
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/66583
摘要： The invention includes an apparatus and a method of manufacturing such apparatus using a damascene process. The method includes the step of patterning a layer disposed over a substrate to include a line and space pattern. The line and space pattern in the layer includes at least one space comprising a width dimension of a feature to be formed. The feature may be, e.g., a wordline(s)/gate electrode(s). Additionally, the sidewalls of the feature, e.g., the wordline(s)/gate electrode(s) include relatively smooth surfaces.
摘要翻译：本发明包括使用镶嵌工艺制造这种装置的装置和方法。该方法包括图案化设置在衬底上的层以包括线和空间图案的步骤。层中的线和空间图案包括至少一个包含要形成的特征的宽度尺寸的空间。该特征可以是例如字线/栅极电极。另外，特征的侧壁，例如字线/栅电极包括相对光滑的表面。

2. 发明授权

US07091088B1 UV-blocking etch stop layer for reducing UV-induced charging of charge storage layer in memory devices in BEOL processing 有权
标题翻译：用于减少BEOL处理中的存储器件中的电荷存储层的UV诱导的充电的UV阻挡蚀刻停止层
公开(公告)号：US07091088B1
公开(公告)日：2006-08-15
申请号：US10861437
申请日：2004-06-03
申请人： Ning Cheng , Clarence B. Ferguson , Emmanuil H. Lingunis , Minh Van Ngo , Joerg Reiss , Jean Y. Yang , Jeffrey A. Shields , Cyrus Tabery
发明人： Ning Cheng , Clarence B. Ferguson , Emmanuil H. Lingunis , Minh Van Ngo , Joerg Reiss , Jean Y. Yang , Jeffrey A. Shields , Cyrus Tabery
IPC分类号： H01L21/336
CPC分类号： H01L23/53295 , H01L21/76829 , H01L27/115 , H01L27/11568 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing over the charge trapping dielectric flash memory cell at least one UV-protective layer; forming at least one layer over the at least one UV-protective layer; and etching the at least one layer to form an opening therein with an etchant species selective to stop on a layer below the at least one UV-protective layer, wherein the UV-protective layer comprises a substantially UV-opaque material.
摘要翻译：一种保护电荷捕获电介质闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造电荷俘获电介质闪存单元; 在电荷捕获电介质闪存单元上沉积至少一个UV保护层; 在所述至少一个UV保护层上形成至少一层; 以及蚀刻所述至少一个层以在其中形成具有选择性地停留在所述至少一个UV保护层下方的层上的蚀刻剂物质的开口，其中所述UV保护层包括基本上不透紫外线的材料。

3. 发明授权

US06989563B1 Flash memory cell with UV protective layer 有权
标题翻译：具有UV保护层的闪存单元
公开(公告)号：US06989563B1
公开(公告)日：2006-01-24
申请号：US10770260
申请日：2004-02-02
申请人： Krishnashree Achuthan , Patrick K. Cheung , Cyrus Tabery , Jean Y. Yang , Ning Cheng , Minh Van Ngo
发明人： Krishnashree Achuthan , Patrick K. Cheung , Cyrus Tabery , Jean Y. Yang , Ning Cheng , Minh Van Ngo
IPC分类号： H01L29/788
CPC分类号： H01L29/7923 , H01L23/53295 , H01L23/552 , H01L29/66833 , H01L2924/0002 , H01L2924/00
摘要： A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing and planarizing an interlevel dielectric layer over the charge trapping dielectric flash memory cell and depositing over the planarized interlevel dielectric layer at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material.
摘要翻译：一种保护电荷捕获电介质闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造电荷俘获电介质闪存单元; 在电荷俘获电介质闪存单元上沉积和平坦化层间电介质层，并在平坦化的层间电介质层上沉积至少一个UV保护层，UV保护层包括基本上不透紫外线的材料。

4. 发明授权

US06770523B1 Method for semiconductor wafer planarization by CMP stop layer formation 失效
标题翻译：通过CMP停止层形成的半导体晶片平面化方法
公开(公告)号：US06770523B1
公开(公告)日：2004-08-03
申请号：US10190397
申请日：2002-07-02
申请人： Kashmir S. Sahota , Jeffrey P. Erhardt , Arvind Halliyal , Minh Van Ngo , Krishnashree Achuthan
发明人： Kashmir S. Sahota , Jeffrey P. Erhardt , Arvind Halliyal , Minh Van Ngo , Krishnashree Achuthan
IPC分类号： H01L218238
CPC分类号： H01L21/76229 , H01L21/31053
摘要： A method of manufacturing an integrated circuit is provided having a semiconductor wafer. A chemical-mechanical polishing stop layer is deposited on the semiconductor wafer and a first photoresist layer is processed over the chemical-mechanical polishing stop layer. The chemical-mechanical polishing stop layer and the semiconductor wafer are patterned to form a shallow trench and a shallow trench isolation material is deposited on the chemical-mechanical polishing stop layer and in the shallow trench. A second photoresist layer is processed over the shallow trench isolation material leaving the shallow trench uncovered. The uncovered shallow trench is then treated to become a chemical-mechanical polishing stop area. The shallow trench isolation material is then chemical-mechanical polished to be co-planar with the chemical-mechanical stop layer and the chemical-mechanical polishing stop treated area.
摘要翻译：提供了具有半导体晶片的集成电路的制造方法。化学机械抛光停止层沉积在半导体晶片上，并且在化学机械抛光停止层上处理第一光致抗蚀剂层。化学机械抛光停止层和半导体晶片被图案化以形成浅沟槽，浅沟槽隔离材料沉积在化学机械抛光停止层和浅沟槽中。在浅沟槽隔离材料上处理第二光致抗蚀剂层，留下未覆盖的浅沟槽。然后将未覆盖的浅沟槽处理成为化学机械抛光停止区域。然后将浅沟槽隔离材料进行化学机械抛光以与化学 - 机械停止层和化学 - 机械抛光停止处理区共面。

5. 发明授权

US06905971B1 Treatment of dielectric material to enhance etch rate 有权
标题翻译：处理电介质材料以提高蚀刻速率
公开(公告)号：US06905971B1
公开(公告)日：2005-06-14
申请号：US10331938
申请日：2002-12-30
申请人： Cyrus Tabery , Chih-Yuh Yang , William G. En , Joong S. Jeon , Minh Van Ngo , Ming-Ren Lin
发明人： Cyrus Tabery , Chih-Yuh Yang , William G. En , Joong S. Jeon , Minh Van Ngo , Ming-Ren Lin
IPC分类号： H01L21/302 , H01L21/311 , H01L21/461
CPC分类号： H01L21/31116 , H01L21/31122
摘要： In one embodiment, the present invention relates to a method for pre-treating and etching a dielectric layer in a semiconductor device comprising the steps of: (A) pre-treating one or more exposed portions of a dielectric layer with a plasma in a plasma etching tool to increase removal rate of the one or more exposed portions upon etching; and (B) removing the one or more exposed portions of the dielectric layer in the same plasma etching tool of step (A) via plasma etching.
摘要翻译：在一个实施例中，本发明涉及一种用于在半导体器件中预处理和蚀刻电介质层的方法，包括以下步骤：（A）用等离子体中的等离子体预处理介电层的一个或多个暴露部分蚀刻工具，以在蚀刻时增加一个或多个暴露部分的去除速率; 和（B）通过等离子体蚀刻在步骤（A）的相同等离子体蚀刻工具中去除介电层的一个或多个暴露部分。

6. 发明授权

US06617215B1 Memory wordline hard mask 有权
标题翻译：内存字线硬掩模
公开(公告)号：US06617215B1
公开(公告)日：2003-09-09
申请号：US10109235
申请日：2002-03-27
申请人： Arvind Halliyal , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang , Emmanuil Lingunis , Angela T. Hui , Jusuke Ogura
发明人： Arvind Halliyal , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang , Emmanuil Lingunis , Angela T. Hui , Jusuke Ogura
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L21/0332 , H01L21/32139 , H01L27/115
摘要： A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric material. First and second bitlines are implanted and a wordline material is deposited. A hard mask material is deposited over the wordline material. The hard mask material is of a material having the characteristic of being deposited rather than grown. A photoresist material is deposited over the wordline material and is patterned to form a patterned hard mask. The patterned photoresist material is removed. The wordline material is processed using the patterned hard mask to form a wordline. The patterned hard mask material is removed.
摘要翻译：用于MirrorBit（R）闪存的制造方法包括提供半导体衬底和沉积电荷俘获电介质材料。植入第一和第二位线，并存放字线材料。硬掩模材料沉积在字线材料上。硬掩模材料是具有沉积而不是生长的特征的材料。光致抗蚀剂材料沉积在字线材料上并被图案化以形成图案化的硬掩模。去除图案化的光致抗蚀剂材料。使用图案化的硬掩模处理字线材料以形成字线。去除图案化的硬掩模材料。

7. 发明授权

US06884681B1 Method of manufacturing a semiconductor memory with deuterated materials 有权
标题翻译：用氘代材料制造半导体存储器的方法
公开(公告)号：US06884681B1
公开(公告)日：2005-04-26
申请号：US10672093
申请日：2003-09-26
申请人： Tazrien Kamal , Arvind Halliyal , Minh Van Ngo , Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino
发明人： Tazrien Kamal , Arvind Halliyal , Minh Van Ngo , Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino
IPC分类号： H01L21/336 , H01L21/8246
CPC分类号： H01L27/11568 , H01L29/66833
摘要： A method for manufacturing a MirrorBit® Flash memory includes providing a semiconductor substrate and successively depositing a first insulating layer, a charge-trapping layer, and a second insulating layer. First and second bitlines are implanted and wordlines are formed before completing the memory. Spacers are formed between the wordlines and an inter-layer dielectric layer is formed over the wordlines. One or more of the second insulating layer, wordlines, spacers, and inter-layer dielectric layers are deuterated, replacing hydrogen bonds with deuterium, thus improving data retention and substantially reducing charge loss.
摘要翻译：一种用于制造MirrorBit（闪存）闪存的方法包括：提供半导体衬底，并依次沉积第一绝缘层，电荷俘获层和第二绝缘层。植入第一和第二位线，并在完成内存之前形成字线。在字线之间形成间隔，并且在字线之间形成层间电介质层。第二绝缘层，字线，间隔层和层间电介质层中的一个或多个被氘化，用氘替代氢键，从而改善数据保留并显着降低电荷损失。

8. 发明授权

US06479348B1 Method of making memory wordline hard mask extension 有权
标题翻译：制作内存字线硬掩模扩展的方法
公开(公告)号：US06479348B1
公开(公告)日：2002-11-12
申请号：US10109516
申请日：2002-08-27
申请人： Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey Shields , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Angela T. Hui
发明人： Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey Shields , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Angela T. Hui
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115
摘要： A manufacturing method is provided for an integrated circuit memory with closely spaced wordlines formed by using hard mask extensions. A charge-trapping dielectric material is deposited over a semiconductor substrate and first and second bitlines are formed therein. A wordline material and a hard mask material are deposited over the wordline material. A photoresist material is deposited over the hard mask material and is processed to form a patterned photoresist material. The hard mask material is processed using the patterned photoresist material to form a patterned hard mask material. The patterned photoresist is then removed. A hard mask extension material is deposited over the wordline material and is processed to form a hard mask extension. The wordline material is processed using the patterned hard mask material and the hard mask extension to form a wordline, and the patterned hard mask material and the hard mask extension are then removed.
摘要翻译：提供了一种用于通过使用硬掩模延伸部形成的具有紧密间隔的字线的集成电路存储器的制造方法。在半导体衬底上沉积电荷俘获电介质材料，并在其中形成第一和第二位线。字线材料和硬掩模材料沉积在字线材料上。光致抗蚀剂材料沉积在硬掩模材料上并被处理以形成图案化的光致抗蚀剂材料。使用图案化的光致抗蚀剂材料处理硬掩模材料以形成图案化的硬掩模材料。然后去除图案化的光致抗蚀剂。硬掩模延伸材料沉积在字线材料上并被处理以形成硬掩模延伸部。使用图案化的硬掩模材料和硬掩模延伸部来处理字线材料以形成字线，然后去除图案化的硬掩模材料和硬掩模延伸部。

9. 发明授权

US06670241B1 Semiconductor memory with deuterated materials 有权
标题翻译：具有氘化材料的半导体存储器
公开(公告)号：US06670241B1
公开(公告)日：2003-12-30
申请号：US10128771
申请日：2002-04-22
申请人： Tazrien Kamal , Arvind Halliyal , Minh Van Ngo , Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino
发明人： Tazrien Kamal , Arvind Halliyal , Minh Van Ngo , Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L29/66833
摘要： A device and method for manufacturing thereof for a MirrorBit® Flash memory includes providing a semiconductor substrate and successively depositing a first insulating layer, a charge-trapping layer, and a second insulating layer. First and second bitlines are implanted and wordlines are formed before completing the memory. Spacers are formed between the wordlines and an inter-layer dielectric layer is formed over the wordlines. One or more of the second insulating layer, wordlines, spacers, and inter-layer dielectric layers are deuterated, replacing hydrogen bonds with deuterium, thus improving data retention and substantially reducing charge loss.
摘要翻译：用于制造MirrorBit（闪存）闪存的器件及其制造方法包括：提供半导体衬底，并依次沉积第一绝缘层，电荷俘获层和第二绝缘层。植入第一和第二位线，并在完成内存之前形成字线。在字线之间形成间隔，并且在字线之间形成层间电介质层。第二绝缘层，字线，间隔层和层间电介质层中的一个或多个被氘化，用氘替代氢键，从而改善数据保留并显着降低电荷损失。

10. 发明授权

US06653190B1 Flash memory with controlled wordline width 失效
标题翻译：具有受控字线宽度的闪存
公开(公告)号：US06653190B1
公开(公告)日：2003-11-25
申请号：US10023436
申请日：2001-12-15
申请人： Jean Y. Yang , Kouros Ghandehari , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Dawn M. Hopper , Angela T. Hui , Scott A. Bell
发明人： Jean Y. Yang , Kouros Ghandehari , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Dawn M. Hopper , Angela T. Hui , Scott A. Bell
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method of manufacturing for a MirrorBit® Flash memory includes depositing a charge-trapping material over a semiconductor substrate and implanting first and second bitlines in the semiconductor substrate. A wordline material is deposited over the charge-trapping dielectric material and a hard mask material deposited thereon. An anti-reflective coating (ARC) material is deposited on the hard mask material and a photoresist material is deposited on the ARC followed by processing the photoresist material and the ARC material to form a photomask of a patterned photoresist and a patterned ARC. The hard mask material is processed using the photomask to form a hard mask. The patterned photoresist is removed and then the patterned ARC without damaging the hard mask or the wordline material. The wordline material is processed using the hard mask to form a wordline and the hard mask is removed without damaging the wordline or the charge-trapping material.
摘要翻译：用于MirrorBit（闪存）闪存的制造方法包括在半导体衬底上沉积电荷捕获材料并在半导体衬底中注入第一和第二位线。字线材料沉积在电荷俘获电介质材料上并沉积在其上的硬掩模材料。将抗反射涂层（ARC）材料沉积在硬掩模材料上，并且将光致抗蚀剂材料沉积在ARC上，随后处理光致抗蚀剂材料和ARC材料以形成图案化光致抗蚀剂和图案化ARC的光掩模。使用光掩模处理硬掩模材料以形成硬掩模。去除图案化的光致抗蚀剂，然后去除图案化的ARC，而不损坏硬掩模或字线材料。使用硬掩模处理字线材料以形成字线，并且去除硬掩模而不损坏字线或电荷捕获材料。

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