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1. 发明授权

US06821847B2 Nonvolatile memory structures and fabrication methods 有权
公开(公告)号：US06821847B2
公开(公告)日：2004-11-23
申请号：US09969841
申请日：2001-10-02
申请人： Chung Wai Leung , Chia-Shun Hsiao , Vei-Han Chan
发明人： Chung Wai Leung , Chia-Shun Hsiao , Vei-Han Chan
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.

2. 发明授权

US06706596B2 Method for forming flash memory cell 有权
标题翻译：形成闪存单元的方法
公开(公告)号：US06706596B2
公开(公告)日：2004-03-16
申请号：US10209855
申请日：2002-08-02
申请人： Ping-Yi Chang , Wan-Yi Liu , Shu-Li Wu
发明人： Ping-Yi Chang , Wan-Yi Liu , Shu-Li Wu
IPC分类号： H01L218247
CPC分类号： H01L27/115 , H01L27/11521
摘要： The present invention provides a method for forming a flash memory cell and comprises following steps. First, a substrate is provided. Then, a gate dielectric layer, a first polysilicon layer and a hard mask layer are sequentially formed on the substrate. Next, a portion of the hard mask layer, the polysilicon layer, and the gate dielectric layer are removed to form a plurality of holes to expose the substrate. Following, a dielectric layer is formed in those holes by a HDPCVD process. Last, the hard mask layer on the first polysilicon layer is removed by the HDPCVD process. Further, a second polysilicon layer could be conformally formed on the first polysilicon layer and the isolation dielectric.
摘要翻译：本发明提供一种形成闪存单元的方法，包括以下步骤。首先，提供基板。然后，在衬底上依次形成栅介电层，第一多晶硅层和硬掩模层。接下来，去除硬掩模层，多晶硅层和栅极电介质层的一部分以形成多个孔以露出衬底。接下来，通过HDPCVD工艺在这些孔中形成介电层。最后，通过HDPCVD工艺去除第一多晶硅层上的硬掩模层。此外，第二多晶硅层可以共形地形成在第一多晶硅层和隔离电介质上。

3. 发明授权

US06656795B1 Method of manufacturing semiconductor memory element 失效
标题翻译：制造半导体存储元件的方法
公开(公告)号：US06656795B1
公开(公告)日：2003-12-02
申请号：US10325836
申请日：2002-12-23
申请人： Koki Muto
发明人： Koki Muto
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , G03F1/50 , H01L21/28273 , H01L27/115
摘要： A method of manufacturing a semiconductor memory element is disclosed. The method includes arranging a mask on the upper surface of a semiconductor substrate, using the mask to conduct exposure, forming first, second, and third element-isolation regions on the semiconductor substrate surface, and forming a gate electrode. A resist film is formed on the substrate. On the mask, auxiliary patterns are made at the each central portion of first, second, and third patterns. In the exposure with the mask, first, second, and third resist patterns is formed on the resist film. The resist patterns respectively correspond to the patterns on the mask. The gate electrode extending in the second direction is formed from the upper surface of the second element-isolation region to the upper surface of the third electrode element-isolation region through an area between the second and third element-isolation regions.
摘要翻译：公开了半导体存储元件的制造方法。该方法包括在半导体衬底的上表面上设置掩模，使用掩模进行曝光，在半导体衬底表面上形成第一，第二和第三元件隔离区域，以及形成栅电极。在基板上形成抗蚀剂膜。在掩模上，在第一，第二和第三图案的每个中心部分处形成辅助图案。在利用掩模的曝光中，在抗蚀剂膜上形成第一，第二和第三抗蚀剂图案。抗蚀剂图案分别对应于掩模上的图案。通过第二和第三元件隔离区域之间的区域，从第二元件隔离区域的上表面到第三电极元件隔离区域的上表面形成沿第二方向延伸的栅电极。

4. 发明授权

US06642109B2 Method of manufacturing a flash memory cell 失效
公开(公告)号：US06642109B2
公开(公告)日：2003-11-04
申请号：US10283073
申请日：2002-10-30
申请人： Seung Cheol Lee , Sang Wook Park
发明人： Seung Cheol Lee , Sang Wook Park
IPC分类号： H01L218247
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method of manufacturing a flash memory cell in which an ion implantation process is performed before a cleaning process for etching a protrusion of a trench insulating film to a nipple shape. As a result, the etch rate at a portion except for portions in which a moat will occur along the trench insulating film is increased. Therefore, generation of the moat in the trench insulating film can be prevented and spacing of the floating gate can be optimized.

5. 发明授权

US06627500B1 Method of fabricating nitride read only memory 有权
标题翻译：制造氮化物只读存储器的方法
公开(公告)号：US06627500B1
公开(公告)日：2003-09-30
申请号：US10064796
申请日：2002-08-19
申请人： Chien-Hung Liu , Shyi-Shuh Pan , Shou-Wei Huang
发明人： Chien-Hung Liu , Shyi-Shuh Pan , Shou-Wei Huang
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/978
摘要： A method of fabricating a nitride read only memory. A trapping dielectric sandwiched structure, including an insulation layer, a charge trap layer and an insulation layer, is formed on a substrate. An opening with indented sidewalls is formed in the insulation layer. A thermal oxide layer is formed to fill the opening, such that the indented sidewalls are completely sealed. The charge trap layer is thus sealed by the insulation layers and the thermal oxide layer to avoid the direct contact between the control gate and the charge trap layer, so as to prevent the data loss.
摘要翻译：一种制造氮化物只读存储器的方法。在衬底上形成包括绝缘层，电荷陷阱层和绝缘层的俘获电介质夹层结构。在绝缘层中形成具有凹入侧壁的开口。形成热氧化物层以填充开口，使得凹入的侧壁被完全密封。因此，电荷陷阱层被绝缘层和热氧化物层密封，以避免控制栅极和电荷陷阱层之间的直接接触，从而防止数据丢失。

6. 发明授权

US06624029B2 Method of fabricating a self-aligned non-volatile memory cell 有权
公开(公告)号：US06624029B2
公开(公告)日：2003-09-23
申请号：US10236670
申请日：2002-09-06
申请人： Bohumil Lojek , Alan L. Renninger
发明人： Bohumil Lojek , Alan L. Renninger
IPC分类号： H01L218247
CPC分类号： H01L29/7883 , H01L21/28273 , H01L21/76895 , H01L29/42324 , H01L29/42328 , H01L29/66825
摘要： Disclosed is a self-aligned non-volatile memory cell comprising a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer which is thinner between the small sidewall spacer and the substrate; and is thicker between the main floating gate region and the substrate. The small sidewall spacer can be made small; therefore, the thin oxide layer area can also be made small to create a small pathway for electrons to tunnel into the floating gate.

7. 发明授权

US06620689B2 Method of fabricating a flash memory cell using angled implant 有权
标题翻译：使用角度植入物制造闪存单元的方法
公开(公告)号：US06620689B2
公开(公告)日：2003-09-16
申请号：US10147236
申请日：2002-05-15
申请人： Shian-Jyh Lin
发明人： Shian-Jyh Lin
IPC分类号： H01L218247
CPC分类号： H01L29/42324 , H01L21/28273
摘要： A method of fabricating a flash memory cell. The method includes the steps of providing a semiconductor substrate; forming a first gate insulating layer; forming a first conductive layer; forming a barrier layer; removing a portion of the barrier layer to form a first opening; performing an angled implant on the exposed surface of the first conductive layer; forming a floating gate insulating layer; removing the barrier layer; forming a floating gate and a first gate insulating layer; forming a second insulating layer; forming a second conductive layer; removing portions of the second conductive layer and the second insulating layer to form a second opening and a third opening; forming a source region on the substrate; forming spacers on the sidewalls of the second opening and the third opening; and forming drain regions on the substrate within the third opening.
摘要翻译：一种制造闪存单元的方法。该方法包括提供半导体衬底的步骤; 形成第一栅极绝缘层; 形成第一导电层; 形成阻挡层; 去除阻挡层的一部分以形成第一开口; 在所述第一导电层的暴露表面上执行成角度的植入物; 形成浮栅绝缘层; 去除阻挡层; 形成浮栅和第一栅极绝缘层; 形成第二绝缘层; 形成第二导电层; 去除所述第二导电层和所述第二绝缘层的部分以形成第二开口和第三开口; 在所述基板上形成源极区域; 在所述第二开口和所述第三开口的侧壁上形成间隔物; 以及在所述第三开口内的所述基板上形成漏极区。

8. 发明授权

US06605509B1 Method for forming smooth floating gate structure for flash memory 失效
标题翻译：形成闪存平滑浮栅结构的方法
公开(公告)号：US06605509B1
公开(公告)日：2003-08-12
申请号：US10251962
申请日：2002-09-23
申请人： Wen-Kuei Hsieh
发明人： Wen-Kuei Hsieh
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for forming a smooth floating gate structure for a flash memory is disclosed. The method comprises the following steps. A substrate is firstly provided, and a first conductive layer and a second conductive layer are sequentially formed on the substrate. A first dielectric layer is then formed on the second conductive layer. A first hard mask layer and a second hard mask layer are formed sequentially on the first dielectric layer. A floating gate pattern is then transferred into the second hard mask layer to expose the first hard mask layer. The first hard mask layer is then etched to form a pattern and expose the first dielectric layer. A second dielectric layer is conformally formed over the second hard mask layer and the pattern; The second dielectric layer is etched back to form a spacer and expose the first dielectric layer. The first dielectric layer is then etched to expose the second conductive layer and the spacer, the second hard mask layer, the first hard mask layer and the first dielectric layer are finally removed.
摘要翻译：公开了一种用于形成用于闪速存储器的平滑浮动栅极结构的方法。该方法包括以下步骤。首先提供衬底，并且在衬底上依次形成第一导电层和第二导电层。然后在第二导电层上形成第一介电层。第一硬掩模层和第二硬掩模层依次形成在第一介电层上。然后将浮栅图案转移到第二硬掩模层中以暴露第一硬掩模层。然后蚀刻第一硬掩模层以形成图案并暴露第一介电层。在第二硬掩模层和图案上共形形成第二电介质层; 将第二电介质层回蚀以形成间隔物并露出第一介电层。然后蚀刻第一介电层以露出第二导电层，并且最终去除第二介电层，间隔物，第二硬掩模层，第一硬掩模层和第一介电层。

9. 发明授权

US06586303B2 Method for fabricating a mask ROM 有权
标题翻译：掩模ROM的制造方法
公开(公告)号：US06586303B2
公开(公告)日：2003-07-01
申请号：US09683246
申请日：2001-12-05
申请人： Yi-Ting Wu
发明人： Yi-Ting Wu
IPC分类号： H01L218247
CPC分类号： H01L27/11253 , H01L21/743 , H01L27/112
摘要： A patterned photoresist layer is coated onto a semiconductor substrate. Then a doped region is formed in the semiconductor substrate not covered by the patterned photoresist layer. In addition, a semiconductor process is performed to trim the patterned photoresist layer, and a lightly doped drain (LDD) region is formed in the region of the semiconductor substrate next to the doped region. The doped region and the LDD region constitute the buried bit lines of the mask ROM. Finally, the photoresist layer is stripped.
摘要翻译：将图案化的光致抗蚀剂层涂覆到半导体衬底上。然后，在未被图案化光致抗蚀剂层覆盖的半导体衬底中形成掺杂区域。此外，执行半导体工艺以修整图案化的光致抗蚀剂层，并且在半导体衬底的与掺杂区域相邻的区域中形成轻掺杂漏极（LDD）区域。掺杂区域和LDD区域构成掩模ROM的掩埋位线。最后，剥离光致抗蚀剂层。

10. 发明授权

US06573140B1 Process for making a dual bit memory device with isolated polysilicon floating gates 有权
标题翻译：制造具有隔离多晶硅浮动栅极的双位存储器件的工艺
公开(公告)号：US06573140B1
公开(公告)日：2003-06-03
申请号：US09810155
申请日：2001-03-16
申请人： Jusuke Ogura , Kiyoshi Izumi , Masaru Yano , Hideki Komori , Tuan Pham , Angela Hui
发明人： Jusuke Ogura , Kiyoshi Izumi , Masaru Yano , Hideki Komori , Tuan Pham , Angela Hui
IPC分类号： H01L218247
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11521 , H01L29/66825 , H01L29/7887
摘要： The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates. Processes for making the memory device according to the invention are also disclosed.
摘要翻译：本发明一般涉及半导体存储器件，更具体地说涉及在浮置栅极内采用电荷俘获来表示0或1位状态的多位闪存电可擦除可编程只读存储器（EEPROM）器件。根据本发明的一个方面，提供一种存储器件，其包括具有双重多晶硅浮动栅极的浮动栅极晶体管，在浮置栅极之间具有隔离开口。还公开了用于制造根据本发明的存储器件的工艺。

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