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1. 发明授权

US06828184B2 Method of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06828184B2
公开(公告)日：2004-12-07
申请号：US10618292
申请日：2003-07-11
申请人： Ihl Hyun Cho
发明人： Ihl Hyun Cho
IPC分类号： H01L218238
CPC分类号： H01L21/31133 , H01L21/02052 , H01L21/823462
摘要： Disclosed is a method of manufacturing semiconductor devices. In the process of simultaneously forming a high voltage device and a low voltage device, a photoresist film for patterning a gate oxide film in a high voltage device is removed in a wet mode using a solvent. The polysilicon film used as the gate electrode is then formed without applying a vacuum. It is thus possible to increase reliability of the gate oxide film, and prevent damage of the gate oxide film due to ozone plasma and penetration of a grain protrusion of the polysilicon film into the gate oxide film. Accordingly, the breakdown voltage characteristic of the gate oxide film is improved.
摘要翻译：公开了半导体器件的制造方法。在同时形成高电压器件和低电压器件的过程中，使用溶剂以湿模式除去用于在高电压器件中构图栅极氧化膜的光致抗蚀剂膜。然后在不施加真空的情况下形成用作栅电极的多晶硅膜。因此，可以提高栅极氧化膜的可靠性，并且防止由于臭氧等离子体导致的栅极氧化膜的损坏和多晶硅膜的晶粒突起的渗透进入栅极氧化膜。因此，提高了栅极氧化膜的击穿电压特性。

2. 发明授权

US06818505B2 Non-volatile semiconductor memory device and manufacturing method thereof 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US06818505B2
公开(公告)日：2004-11-16
申请号：US10135443
申请日：2002-05-01
申请人： Naoki Tsuji
发明人： Naoki Tsuji
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66825
摘要： In a non-volatile semiconductor memory device, three-layered structure of the first, second and third floating gate electrodes is implemented, and stepped portions are provided on the first interlayer insulating film surrounding the first floating gate electrode. The position of the bottom surface of the second floating gate electrode can be disposed higher than that of the upper surface of the first floating gate electrode. Consequently, compared with overlapping area of the floating gate electrode with a control gate electrode in a conventional non-volatile semiconductor device, it can be increased by the length of stepped portions on the first interlayer insulating film. Film thickness as floating gate electrode will not be as thick as conventional structures. Overlapping area of the floating gate electrode with the control gate electrode can be sufficiently secured without a portion with the maximum film thickness of floating gate electrode being larger.
摘要翻译：在非易失性半导体存储器件中，实现了第一，第二和第三浮栅电极的三层结构，并且在围绕第一浮栅电极的第一层间绝缘膜上设置有台阶部分。第二浮栅电极的底表面的位置可以比第一浮栅电极的上表面高。因此，与传统的非易失性半导体器件中的具有控制栅电极的浮栅电极的重叠面积相比，可以通过第一层间绝缘膜上的阶梯部分的长度来增加。作为浮栅电极的膜厚度将不如常规结构那样厚。可以充分确保浮栅电极与控制栅电极的重叠区域，而没有浮动栅电极的最大膜厚度的部分较大。

3. 发明授权

US06815286B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US06815286B2
公开(公告)日：2004-11-09
申请号：US10238880
申请日：2002-09-11
申请人： Juri H. Krieger , Nikolai Yudanov
发明人： Juri H. Krieger , Nikolai Yudanov
IPC分类号： H01L218238
CPC分类号： G11C13/0064 , B82Y10/00 , G11C11/34 , G11C11/5664 , G11C13/0009 , G11C13/0014 , G11C13/0016 , G11C13/0069 , G11C13/04 , G11C2213/11 , G11C2213/15 , G11C2213/34 , G11C2213/35 , G11C2213/52 , G11C2213/56 , G11C2213/71 , G11C2213/77 , H01L27/28 , H01L27/285 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/14 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L51/0034 , H01L51/0035 , H01L51/0036 , H01L51/0037 , H01L51/0041 , H01L51/0042 , H01L51/0051 , H01L51/0062 , H01L51/0077 , H01L51/0078 , H01L51/0094 , H01L51/0595
摘要： A method of forming and operating a memory storage and retrieval device containing (a) an electrically conductive first electrode; (b) an electrically conductive second electrode; (c) a layer stack intermediate the first and second electrodes containing (d) at least one active layer with variable electrical conductivity; and (e) at least one passive layer containing a source material for varying the electrical conductivity of the at least one active layer upon application of an electrical potential difference between the first and second electrodes.
摘要翻译：一种形成和操作包含（a）导电的第一电极的存储器存储和取回装置的方法; （b）导电的第二电极; （c）包含（d）至少一个具有可变导电性的活性层的第一和第二电极之间的层叠层; 和（e）至少一个含有源材料的钝化层，用于在施加第一和第二电极之间的电位差时改变至少一个有源层的导电性。

4. 发明授权

US06815285B2 Methods of forming dual gate semiconductor devices having a metal nitride layer 有权
标题翻译：形成具有金属氮化物层的双栅极半导体器件的方法
公开(公告)号：US06815285B2
公开(公告)日：2004-11-09
申请号：US10425276
申请日：2003-04-29
申请人： Gil-Heyun Choi , Jong-Ho Lee , Kyung-In Choi , Byung-Hee Kim
发明人： Gil-Heyun Choi , Jong-Ho Lee , Kyung-In Choi , Byung-Hee Kim
IPC分类号： H01L218238
CPC分类号： H01L21/28185 , H01L21/265 , H01L21/28088 , H01L21/28202 , H01L21/82345 , H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method for forming a dual gate includes providing a semiconductor substrate that has a first region of a first conductivity type and a second region of a second conductivity type. A gate insulating layer is formed on the semiconductor substrate. An initial metal nitride layer is formed on the gate insulating layer, opposite to the semiconductor substrate. Nitrogen ions are implanted into the initial metal nitride layer in the second transistor region to form a nitrogen-rich metal nitride layer. The initial metal nitride layer is patterned to form a first gate electrode in the first region. The nitrogen-rich metal nitride layer is patterned to form a second gate electrode in the second region. The work function of the nitrogen-rich metal nitride layer is higher than that of the initial metal nitride layer.
摘要翻译：形成双栅极的方法包括提供具有第一导电类型的第一区域和第二导电类型的第二区域的半导体衬底。在半导体衬底上形成栅极绝缘层。在栅极绝缘层上形成与半导体衬底相反的初始金属氮化物层。将氮离子注入到第二晶体管区域中的初始金属氮化物层中以形成富氮金属氮化物层。图案化初始金属氮化物层以在第一区域中形成第一栅电极。图案化富氮金属氮化物层以在第二区域中形成第二栅电极。富氮金属氮化物层的功函数高于初始金属氮化物层的功函数。

5. 发明授权

US06812085B2 Semiconductor device and method for fabricating same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06812085B2
公开(公告)日：2004-11-02
申请号：US10271745
申请日：2002-10-17
申请人： Sang Gi Lee
发明人： Sang Gi Lee
IPC分类号： H01L218238
CPC分类号： H01L27/105 , H01L27/11 , H01L27/1116
摘要： A semiconductor device and a method for fabricating the same which improve characteristic of stand-by current of an SRAM cell is disclosed in the present invention. The semiconductor device comprises a semiconductor substrate in which a peripheral area and a cell area are defined, a first and second gate insulating layers on the semiconductor substrate of the peripheral area and the cell area, first and second gate electrodes on the first and second gate insulating layers, respectively, first and second heavily doped source/drain regions in the semiconductor substrate at both sides of the first gate electrode and the second gate electrode, respectively, first and second lightly doped source/drain regions in the semiconductor substrate, adjacent to the first heavily doped source/drain regions and the second heavily doped source/drain regions, respectively, wherein the first and second lightly doped source/drain regions have a different length, and a silicide layer on the first and second gate electrodes and in the first and second heavily doped source/drain regions.
摘要翻译：在本发明中公开了一种提高SRAM单元的待机电流特性的半导体器件及其制造方法。半导体器件包括其中限定了外围区域和单元区域的半导体衬底，在周边区域的半导体衬底上的第一和第二栅极绝缘层和电池区域，第一和第二栅极上的第一和第二栅电极绝缘层分别在半导体衬底中在第一栅电极和第二栅极两侧的第一和第二重掺杂源/漏区分别在半导体衬底中的第一和第二轻掺杂源/漏区，邻近第一重掺杂源极/漏极区和第二重掺杂源极/漏极区，其中第一和第二轻掺杂源极/漏极区具有不同的长度，以及在第一和第二栅电极上的硅化物层第一和第二重掺杂源/漏区。

6. 发明授权

US06806128B2 Semiconductor integrated circuit device and a method of manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06806128B2
公开(公告)日：2004-10-19
申请号：US09898050
申请日：2001-07-05
申请人： Fumio Ootsuka , Katsuhiko Ichinose , Shoji Wakahara
发明人： Fumio Ootsuka , Katsuhiko Ichinose , Shoji Wakahara
IPC分类号： H01L218238
CPC分类号： H01L21/8238 , H01L21/26586 , H01L29/1083 , H01L29/665 , H01L29/66628
摘要： With a gate electrode and side wall spacers being used as masks, ions of an n-type impurity are implanted from the normal line direction of a substrate, whereby source/drain diffused regions are formed. Then, ions of an n-type impurity are introduced by oblique implantation having a predetermined angle relative to the normal line direction of the substrate to form an n-type semiconductor region having an impurity concentration higher than source/drain extended regions. By this method, the junction depth of the semiconductor region becomes smaller than that of the source/drain diffused regions and greater than that of the source/drain extended regions.
摘要翻译：使用栅电极和侧壁间隔物作为掩模，从衬底的法线方向注入n型杂质的离子，从而形成源极/漏极扩散区域。然后，通过相对于基板的法线方向具有预定角度的倾斜注入引入n型杂质的离子，以形成杂质浓度高于源极/漏极延伸区域的n型半导体区域。通过该方法，半导体区域的结深度变得比源极/漏极扩散区域的结深度大，并且大于源极/漏极延伸区域的结深度。

7. 发明授权

US06800908B2 Apparatus and circuit having reduced leakage current and method therefor 失效
公开(公告)号：US06800908B2
公开(公告)日：2004-10-05
申请号：US10255524
申请日：2002-09-25
申请人： Mark E. Schuelein
发明人： Mark E. Schuelein
IPC分类号： H01L218238
CPC分类号： H01L27/0928 , H01L27/0921
摘要： Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage generator that selectively increases the voltage potential on the channel region of a transistor relative to the source region of the transistor. The voltage potential may be provided to a diffusion region in the well regions with transistors.

8. 发明授权

US06787880B2 ESD parasitic bipolar transistors with high resistivity regions in the collector 有权
标题翻译：集电极中具有高电阻率区域的ESD寄生双极晶体管
公开(公告)号：US06787880B2
公开(公告)日：2004-09-07
申请号：US10437093
申请日：2003-05-13
申请人： David Hu , Jun Cai
发明人： David Hu , Jun Cai
IPC分类号： H01L218238
CPC分类号： H01L27/027
摘要： A method and a structure for a parasitic bipolar silicided ESD device that has high resistivity regions within the collector of the parasitic NPN. The device has the structure of a N-MOS transistor and a substrate contact. The device preferably has silicide regions over the doped regions. The invention has two types of high resistivity regions: 1) isolation regions (e.g., oxide shallow trench isolation (STI)) and 2) undoped or lightly doped regions (e.g., channel regions). The channel regions can have gates thereover and the gates can be charged. Also, optionally a n−well (n minus well) can be formed under the collector. The high resistivity regions increase the collector resistivity thereby improving the performance of the parasitic bipolar ESD device.
摘要翻译：一种在寄生NPN的集电极内具有高电阻率区域的寄生双极硅化ESD器件的方法和结构。该器件具有N-MOS晶体管和衬底接触的结构。器件优选在掺杂区域上方具有硅化物区域。本发明具有两种类型的高电阻率区域：1）隔离区域（例如，氧化物浅沟槽隔离（STI））和2）未掺杂或轻掺杂区域（例如沟道区）。通道区域可以有栅极，栅极可以充电。此外，可以在收集器下方形成任选的n - 阱（n-negative well）。高电阻率区域增加了集电极电阻率，从而提高了寄生双极型ESD器件的性能。

9. 发明授权

US06784062B2 Transistor formation for semiconductor devices 有权
标题翻译：半导体器件的晶体管形成
公开(公告)号：US06784062B2
公开(公告)日：2004-08-31
申请号：US10162289
申请日：2002-06-03
申请人： Chih-Chen Cho , Zhongze Wang
发明人： Chih-Chen Cho , Zhongze Wang
IPC分类号： H01L218238
CPC分类号： H01L27/11 , H01L21/82345 , H01L21/823842
摘要： A semiconductor fabrication method of forming a pair of transistor gates of opposite conductivity type by partially forming first and second gate stacks comprising an insulation layer, a conductive layer and polysilicon layer for the pair of transistor by removing a portion of the polysilicon layer. The polysilicon layer includes a dominant region of first-type conductive dopants and a dominant region of second-type conductive dopants. A first-type conductive transistor gate is formed by, completing the formation of the first gate stack and a second-type conductive transistor gate is formed by completing the formation of the second gate stack separately from the formation of the first-type transistor gate.
摘要翻译：通过部分地形成第一和第二栅极堆叠来形成具有相反导电类型的一对晶体管栅极的半导体制造方法，该第一和第二栅极堆叠通过去除多晶硅层的一部分而包括一对晶体管的绝缘层，导电层和多晶硅层。多晶硅层包括第一导电掺杂剂的主要区域和第二导电掺杂剂的主要区域。通过完成第一栅极堆叠的形成而形成第一导电晶体管栅极，并且通过与第一型晶体管栅极的形成分开完成第二栅极堆叠的形成而形成第二导电晶体管栅极。

10. 发明授权

US06784045B1 Microchannel formation for fuses, interconnects, capacitors, and inductors 有权
标题翻译：保险丝，互连线，电容器和电感器的微通道形成
公开(公告)号：US06784045B1
公开(公告)日：2004-08-31
申请号：US10646570
申请日：2003-08-22
申请人： David T. Price , Jayashree Kalpathy-Cramer
发明人： David T. Price , Jayashree Kalpathy-Cramer
IPC分类号： H01L218238
CPC分类号： H01L21/76895 , H01L21/76877 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/5256 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for forming interconnect lines and conductors and passive devices in the fabrication of an integrated circuit. A gap is created in the patterning of a first layer. The gap is filled by a dielectric material so that an encapsulated conduit is formed in the gap. The encapsulated conduit is filled with a conductor by chemical vapor deposition processes or other deposition processes, the filling facilitated by forming via holes to intersect the conduit, and then filling the via holes. The conductor filled conduit can be used as a resistor, fuse, inductor, or capacitor.
摘要翻译：本发明提供了在集成电路的制造中形成互连线和导体以及无源器件的方法。在第一层的图案化中产生间隙。间隙由电介质材料填充，使得在间隙中形成封装导管。封装的管道通过化学气相沉积工艺或其它沉积工艺填充导体，通过形成通孔以与导管相交，然后填充通孔来促进填充。导体填充导管可用作电阻，保险丝，电感或电容。

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