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1. 发明授权

US06905971B1 Treatment of dielectric material to enhance etch rate 有权
标题翻译：处理电介质材料以提高蚀刻速率
公开(公告)号：US06905971B1
公开(公告)日：2005-06-14
申请号：US10331938
申请日：2002-12-30
申请人： Cyrus Tabery , Chih-Yuh Yang , William G. En , Joong S. Jeon , Minh Van Ngo , Ming-Ren Lin
发明人： Cyrus Tabery , Chih-Yuh Yang , William G. En , Joong S. Jeon , Minh Van Ngo , Ming-Ren Lin
IPC分类号： H01L21/302 , H01L21/311 , H01L21/461
CPC分类号： H01L21/31116 , H01L21/31122
摘要： In one embodiment, the present invention relates to a method for pre-treating and etching a dielectric layer in a semiconductor device comprising the steps of: (A) pre-treating one or more exposed portions of a dielectric layer with a plasma in a plasma etching tool to increase removal rate of the one or more exposed portions upon etching; and (B) removing the one or more exposed portions of the dielectric layer in the same plasma etching tool of step (A) via plasma etching.
摘要翻译：在一个实施例中，本发明涉及一种用于在半导体器件中预处理和蚀刻电介质层的方法，包括以下步骤：（A）用等离子体中的等离子体预处理介电层的一个或多个暴露部分蚀刻工具，以在蚀刻时增加一个或多个暴露部分的去除速率; 和（B）通过等离子体蚀刻在步骤（A）的相同等离子体蚀刻工具中去除介电层的一个或多个暴露部分。

2. 发明授权

US06764898B1 Implantation into high-K dielectric material after gate etch to facilitate removal 有权
标题翻译：在栅极蚀刻后植入高K电介质材料以便于去除
公开(公告)号：US06764898B1
公开(公告)日：2004-07-20
申请号：US10147690
申请日：2002-05-16
申请人： William G. En , Joong S. Jeon , Minh Van Ngo , Ming-Ren Lin
发明人： William G. En , Joong S. Jeon , Minh Van Ngo , Ming-Ren Lin
IPC分类号： H01L218242
CPC分类号： H01L21/28273 , H01L21/2807 , H01L21/28123 , H01L21/28194 , H01L21/28202 , H01L21/28282 , H01L21/31111 , H01L21/31122 , H01L21/31691 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention relates to a process of fabricating a semiconductor device, including steps of providing a semiconductor wafer; depositing on the semiconductor wafer at least one layer comprising a high-K dielectric material layer; and subsequently removing a selected portion of the at least one layer comprising a high-K dielectric material by implanting ions into the selected portion, and removing the selected portion by etching. As a result of the implantation, the etch rate of the selected portion is increased relative to an etch rate without the implanting.
摘要翻译：本发明涉及制造半导体器件的方法，包括提供半导体晶片的步骤; 在半导体晶片上沉积包含高K电介质材料层的至少一层; 并且随后通过将离子注入所选择的部分中去除包含高K电介质材料的至少一层的选定部分，以及通过蚀刻去除所选择的部分。作为植入的结果，所选择的部分的蚀刻速率相对于没有植入的蚀刻速率而增加。

3. 发明授权

US06693004B1 Interfacial barrier layer in semiconductor devices with high-K gate dielectric material 有权
标题翻译：具有高K栅极电介质材料的半导体器件中的界面阻挡层
公开(公告)号：US06693004B1
公开(公告)日：2004-02-17
申请号：US10085318
申请日：2002-02-27
申请人： Arvind Halliyal , Joong S. Jeon , Minh Van Ngo , William G. En , Effiong Ibok
发明人： Arvind Halliyal , Joong S. Jeon , Minh Van Ngo , William G. En , Effiong Ibok
IPC分类号： H01L218242
CPC分类号： H01L21/28194 , H01L21/2807 , H01L21/28273 , H01L21/28282 , H01L21/28291 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A semiconductor device and a process for fabricating the device, including, in one embodiment, a silicon substrate; a first interfacial barrier layer on the silicon substrate, in which the first interfacial barrier layer may include aluminum oxide, silicon nitride, silicon oxynitride or a mixture thereof; and a layer of a high-K dielectric material. The device may further include a second interfacial barrier layer on the high-K dielectric material layer, and may further include a polysilicon or polysilicon-germanium gate electrode formed on the second interfacial barrier layer.
摘要翻译：一种半导体器件和用于制造器件的工艺，在一个实施例中包括硅衬底; 硅衬底上的第一界面阻挡层，其中第一界面阻挡层可以包括氧化铝，氮化硅，氮氧化硅或其混合物; 和一层高K电介质材料。该器件还可以包括在高K电介质材料层上的第二界面阻挡层，并且还可以包括形成在第二界面阻挡层上的多晶硅或多晶硅 - 锗栅电极。

4. 发明授权

US06849925B1 Preparation of composite high-K/standard-K dielectrics for semiconductor devices 失效
标题翻译：制备用于半导体器件的复合高K /标准K电介质
公开(公告)号：US06849925B1
公开(公告)日：2005-02-01
申请号：US10656470
申请日：2003-09-05
申请人： Arvind Halliyal , Joong S. Jeon , Minh Van Ngo , Robert B. Ogle
发明人： Arvind Halliyal , Joong S. Jeon , Minh Van Ngo , Robert B. Ogle
IPC分类号： H01L21/28 , H01L21/316 , H01L29/51 , H01L23/58
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/316 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a composite dielectric layer, including a semiconductor substrate, alternating sub-layers including a first dielectric material and a second dielectric material on the semiconductor substrate, the sub-layers forming a composite dielectric layer having at least two sub-layers of at least one of the first dielectric material and the second dielectric material, in which one of the first dielectric material and the second dielectric material is a high-K dielectric material and an other of the first dielectric material and the second dielectric material is a standard-K dielectric material comprising aluminum oxide; and the composite dielectric layer includes a reaction product of the high-K dielectric material and the standard-K dielectric material. In one embodiment, the composite dielectric layer includes a substantially uniform layer of the reaction product of the first dielectric material and the second dielectric material.
摘要翻译：一种具有复合电介质层的半导体器件，包括半导体衬底，在半导体衬底上包括第一电介质材料和第二电介质的交替子层，所述子层形成具有至少两个子层的复合电介质层第一介电材料和第二电介质材料中的至少一个，其中第一电介质材料和第二电介质材料之一是高K电介质材料，第一电介质材料和第二电介质材料中的另一个是标准 -K介电材料，包括氧化铝; 并且复合介电层包括高K介电材料和标准K电介质材料的反应产物。在一个实施例中，复合介电层包括第一电介质材料和第二电介质材料的反应产物的基本均匀的层。

5. 发明授权

US06645882B1 Preparation of composite high-K/standard-K dielectrics for semiconductor devices 有权
标题翻译：制备用于半导体器件的复合高K /标准K电介质
公开(公告)号：US06645882B1
公开(公告)日：2003-11-11
申请号：US10051790
申请日：2002-01-17
申请人： Arvind Halliyal , Joong S. Jeon , Minh Van Ngo , Robert B. Ogle
发明人： Arvind Halliyal , Joong S. Jeon , Minh Van Ngo , Robert B. Ogle
IPC分类号： H01L21469
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/316 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of fabricating the semiconductor device having a composite dielectric layer including steps of providing a semiconductor substrate; depositing on the semiconductor substrate alternating sub-layers of a first dielectric material and a second dielectric material to form a layered dielectric structure having at least two sub-layers of at least one of the first dielectric material and the second dielectric material, in which one of the first dielectric material and the second dielectric material is a high-K dielectric material and an other of the first dielectric material and the second dielectric material is a standard-K dielectric material comprising aluminum oxide; and annealing the layered dielectric structure at an elevated temperature to form a composite dielectric layer.
摘要翻译：一种半导体器件和制造具有复合介电层的半导体器件的方法，包括提供半导体衬底的步骤; 在所述半导体衬底上沉积交替的第一电介质材料和第二介电材料的子层，以形成具有至少两个第二电介质材料和所述第二电介质材料中的至少一个的子层的层状电介质结构，其中一个所述第一电介质材料和所述第二电介质材料是高K电介质材料，所述第一电介质材料和所述第二电介质材料中的另一个是包含氧化铝的标准K电介质材料; 以及在升高的温度下退火所述层状电介质结构以形成复合介电层。

6. 发明授权

US06762454B1 Stacked polysilicon layer for boron penetration inhibition 有权
标题翻译：堆叠多晶硅层用于硼渗透抑制
公开(公告)号：US06762454B1
公开(公告)日：2004-07-13
申请号：US10118363
申请日：2002-04-08
申请人： Effiong Ibok , Joong S. Jeon , Arvind Halliyal , Minh Van Ngo
发明人： Effiong Ibok , Joong S. Jeon , Arvind Halliyal , Minh Van Ngo
IPC分类号： H01L2976
CPC分类号： H01L21/28194 , H01L21/28044 , H01L21/28273 , H01L21/28282 , H01L21/28291 , H01L29/4925 , H01L29/513 , H01L29/517 , H01L29/78 , H01L29/792
摘要： A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a stacked polysilicon layer formed on a dielectric layer. The stacked polysilicon layer inhibits the diffusion of boron in the dielectric layer and the penetration of boron into the dielectric layer and the semiconductor substrate.
摘要翻译：公开了一种形成在具有有源区的半导体衬底上的半导体器件及其制造方法。半导体器件包括形成在电介质层上的堆叠多晶硅层。堆叠的多晶硅层抑制介电层中的硼的扩散以及硼渗透到介质层和半导体衬底中。

7. 发明授权

US08193030B2 Methods of fabricating non-volatile memory devices having carbon nanotube layer and passivation layer 有权
标题翻译：制造具有碳纳米管层和钝化层的非易失性存储器件的方法
公开(公告)号：US08193030B2
公开(公告)日：2012-06-05
申请号：US12929122
申请日：2011-01-03
申请人： Chang-wook Moon , Joong S. Jeon , El Mostafa Bourim , Hyun-deok Yang
发明人： Chang-wook Moon , Joong S. Jeon , El Mostafa Bourim , Hyun-deok Yang
IPC分类号： H01L29/861
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L45/1675 , Y10S438/957 , Y10S438/958 , Y10S977/735 , Y10S977/742 , Y10S977/943
摘要： Nonvolatile memory devices may be fabricated to include a switching device on a substrate and/or a storage node electrically connected to the switching device. A storage node may include a lower metal layer electrically connected to the switching device, a first insulating layer, a middle metal layer, a second insulating layer, an upper metal layer, a carbon nanotube layer, and/or a passivation layer stacked on the lower metal layer.
摘要翻译：可以制造非易失性存储器件，以在电连接到开关器件的衬底和/或存储节点上包括开关器件。存储节点可以包括电连接到开关装置的下金属层，堆叠在开关装置上的第一绝缘层，中间金属层，第二绝缘层，上金属层，碳纳米管层和/或钝化层下层金属层。

8. 发明申请

US20080164533A1 Method of manufacturing a germanosilicide and a semiconductor device having the germanosilicide 审中-公开
标题翻译：制造锗硅酸盐的方法和具有锗硅酸盐的半导体器件
公开(公告)号：US20080164533A1
公开(公告)日：2008-07-10
申请号：US12000494
申请日：2007-12-13
申请人： Hyun-Deok Yang , Chang-wook Moon , Joong S. Jeon
发明人： Hyun-Deok Yang , Chang-wook Moon , Joong S. Jeon
IPC分类号： H01L29/49 , H01L21/44
CPC分类号： H01L29/0847 , H01L21/28518 , H01L29/66628 , H01L29/78
摘要： Example embodiments relate to a method of manufacturing a germanosilicide and a semiconductor device having the germanosilicide. A method according to example embodiments may include providing a substrate having at least a portion formed of silicon germanium. A metal layer may be formed on the silicon germanium. A thermal process may be performed on the substrate at a relatively high pressure to form the germanosilicide.
摘要翻译：示例性实施方案涉及制造锗硅酸盐的方法和具有锗硅酸盐的半导体器件。根据示例性实施例的方法可以包括提供具有由硅锗形成的至少一部分的衬底。可以在硅锗上形成金属层。可以在相对较高的压力下在基材上进行热处理以形成硅酸锗。

9. 发明授权

US07071051B1 Method for forming a thin, high quality buffer layer in a field effect transistor and related structure 有权
标题翻译：在场效应晶体管和相关结构中形成薄的，高质量的缓冲层的方法
公开(公告)号：US07071051B1
公开(公告)日：2006-07-04
申请号：US10761009
申请日：2004-01-20
申请人： Joong S. Jeon , Robert B. Clark-Phelps , Qi Xiang , Huicai Zhong
发明人： Joong S. Jeon , Robert B. Clark-Phelps , Qi Xiang , Huicai Zhong
IPC分类号： H01L21/8238
CPC分类号： H01L21/28194 , H01L29/51 , H01L29/513 , H01L29/7833
摘要： According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate comprises a step of forming a buffer layer on the substrate, where the buffer layer comprises ALD silicon dioxide. The buffer layer can be formed by utilizing a silicon tetrachloride precursor in an atomic layer deposition process, for example. The buffer layer comprises substantially no pin-hole defects and may have a thickness, for example, that is less than approximately 5.0 Angstroms. The method further comprises forming a high-k dielectric layer over the buffer layer. The high-k dielectric layer may be, for example, hafnium oxide, zirconium oxide, or aluminum oxide. According to this exemplary embodiment, the method further comprises forming a gate electrode layer over the high-k dielectric layer. The gate electrode layer may be polycrystalline silicon, for example.
摘要翻译：根据一个示例性实施例，在衬底上形成场效应晶体管的方法包括在衬底上形成缓冲层的步骤，其中缓冲层包含ALD二氧化硅。例如，可以在原子层沉积工艺中利用四氯化硅前体形成缓冲层。缓冲层基本上不包括针孔缺陷，并且可以具有例如小于约5.0埃的厚度。该方法还包括在缓冲层上形成高k电介质层。高k电介质层可以是例如氧化铪，氧化锆或氧化铝。根据该示例性实施例，该方法还包括在高k电介质层上形成栅电极层。栅电极层例如可以是多晶硅。

10. 发明授权

US07026211B1 Semiconductor component and method of manufacture 有权
标题翻译：半导体元件及制造方法
公开(公告)号：US07026211B1
公开(公告)日：2006-04-11
申请号：US10795890
申请日：2004-03-08
申请人： Rinji Sugino , Joong S. Jeon , Robert B. Ogle, Jr.
发明人： Rinji Sugino , Joong S. Jeon , Robert B. Ogle, Jr.
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A semiconductor component having smooth, void-free conductive layers and a method for manufacturing the semiconductor component. Surface features such as gate structures are formed on a semiconductor substrate. A layer of insulating material is formed on the gate structures and a layer of polysilicon is formed on the layer of insulating material. The layer of polysilicon is annealed in a hydrogen ambient to redistribute the silicon atoms of the polysilicon layer. Redistribution of the atoms fills voids that may be present in the layer of polysilicon and smoothes the surface of the layer of polysilicon. Another layer of polysilicon is formed over the annealed layer of polysilicon. This polysilicon layer is annealed in a hydrogen ambient to redistribute the silicon atoms and smooth the surface of the polysilicon layer, thereby forming a subsequently annealed polysilicon layer. Control gate structures are formed from the subsequently annealed polysilicon layer.
摘要翻译：具有光滑无空隙的导电层的半导体部件和半导体部件的制造方法。诸如栅极结构的表面特征形成在半导体衬底上。在栅极结构上形成绝缘材料层，在绝缘材料层上形成多晶硅层。多晶硅层在氢环境中退火以重新分布多晶硅层的硅原子。原子的再分布填充可能存在于多晶硅层中的空隙，并且平滑多晶硅层的表面。在多晶硅的退火层上形成另一层多晶硅。该多晶硅层在氢环境中退火以重新分配硅原子并平滑多晶硅层的表面，从而形成随后退火的多晶硅层。控制栅结构由随后退火的多晶硅层形成。

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