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1. 发明授权

US08642441B1 Self-aligned STI with single poly for manufacturing a flash memory device 有权
标题翻译：自对准STI与单个poly制造闪存设备
公开(公告)号：US08642441B1
公开(公告)日：2014-02-04
申请号：US11639667
申请日：2006-12-15
申请人： Tim Thurgate , Shenqing Fang , Kuo-Tung Chang , YouSeok Suh , Meng Ding , Hidehiko Shiraiwa , Amol Joshi , Harpreet Sachar , David Matsumoto , Lovejeet Singh , Chih-Yuh Yang
发明人： Tim Thurgate , Shenqing Fang , Kuo-Tung Chang , YouSeok Suh , Meng Ding , Hidehiko Shiraiwa , Amol Joshi , Harpreet Sachar , David Matsumoto , Lovejeet Singh , Chih-Yuh Yang
IPC分类号： H01L21/76
CPC分类号： H01L27/11563 , H01L21/28282 , H01L21/76232 , H01L21/823481 , H01L27/11568 , H01L29/66833
摘要： A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.
摘要翻译：公开了一种用于制造具有自对准陷阱层和圆形有源区域拐角的存储器件的方法。在本发明中，在形成电荷捕获层和顶层之前进行STI工艺。 STI过程之后立即暴露有源区域的尖角。因为这些尖角在这个时候被曝光，所以它们可以通过任何数量的已知的四舍五入技术进行四舍五入。四舍五入改善了存储设备的性能特征。在舍入处理之后，电荷捕获结构和其它层可以通过自对准工艺形成。

2. 发明授权

US08143661B2 Memory cell system with charge trap 有权
标题翻译：带电荷陷阱的记忆体系统
公开(公告)号：US08143661B2
公开(公告)日：2012-03-27
申请号：US11539984
申请日：2006-10-10
申请人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
发明人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28273 , H01L27/115 , H01L27/11568
摘要： A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.
摘要翻译：提供一种存储单元系统，包括半导体衬底上的第一绝缘体层，第一绝缘体层上的电荷陷阱层和电荷陷阱层包括具有生长特性的第二绝缘体层的槽。

3. 发明授权

US07492001B2 High K stack for non-volatile memory 有权
标题翻译：高K堆栈用于非易失性存储器
公开(公告)号：US07492001B2
公开(公告)日：2009-02-17
申请号：US11086310
申请日：2005-03-23
申请人： Wei Zheng , Mark Randolph , Hidehiko Shiraiwa
发明人： Wei Zheng , Mark Randolph , Hidehiko Shiraiwa
IPC分类号： H01L29/788 , H01L29/72
CPC分类号： H01L29/792 , G11C16/0475 , H01L21/28273 , H01L21/28282
摘要： A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.
摘要翻译：存储器件可以包括形成在衬底中的源极区域和漏极区域以及形成在源极和漏极区域之间的衬底中的沟道区域。存储器件还可以包括形成在沟道区上的第一氧化物层，第一氧化物层具有第一介电常数，以及形成在第一氧化物层上的电荷存储层。存储器件还可以包括形成在电荷存储层上的第二氧化物层，形成在第二氧化物层上的介电材料层，介电材料具有大于第一介电常数的第二介电常数，以及栅电极形成在电介质材料层上。

4. 发明申请

US20080121981A1 MEMORY SYSTEM WITH PROTECTION LAYER TO COVER THE MEMORY GATE STACK AND METHODS FOR FORMING SAME 有权
标题翻译：具有保护层的存储器系统，以覆盖存储器栅极堆叠及其形成方法
公开(公告)号：US20080121981A1
公开(公告)日：2008-05-29
申请号：US11469164
申请日：2006-08-31
申请人： Hidehiko Shiraiwa , YouSeok Suh , Harpreet Sachar , Satoshi Torii
发明人： Hidehiko Shiraiwa , YouSeok Suh , Harpreet Sachar , Satoshi Torii
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L27/11568
摘要： A memory system is provided including forming a memory gate stack having a charge trap layer over a semiconductor substrate, forming a protection layer to cover the memory gate stack, and forming a protection enclosure for the charge trap layer with the protection layer and the memory gate stack.
摘要翻译：提供了一种存储器系统，包括形成在半导体衬底上具有电荷陷阱层的存储器栅极堆叠，形成覆盖存储器栅极堆叠的保护层，以及形成用于具有保护层和存储栅极的电荷陷阱层的保护外壳堆栈

5. 发明授权

US07232724B1 Radical oxidation for bitline oxide of SONOS 有权
标题翻译： SONOS的位线氧化物的自由基氧化
公开(公告)号：US07232724B1
公开(公告)日：2007-06-19
申请号：US11113507
申请日：2005-04-25
申请人： Hidehiko Shiraiwa , Joong Jeon , Weidong Qian
发明人： Hidehiko Shiraiwa , Joong Jeon , Weidong Qian
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： Methods are disclosed for fabricating multi-bit SONOS flash memory cells, comprising forming a first dielectric layer and a charge trapping layer over a substrate of a wafer and selectively etching the dielectric and charge trapping layers down to a substrate region to form a bitline opening, then implanting a dopant ion species into the substrate associated with the bitline opening in a bitline region. A radical oxidation process is then used to form a second dielectric layer of a triple layer dielectric-charge trapping-dielectric stack over the charge trapping layer and to fill the bitline opening in the bitline regions of the wafer. Finally, a wordline structure is then formed over the triple layer dielectric-charge trapping-dielectric stack and the bitline regions of the wafer. A multi-bit flash memory array is also disclosed, comprising a bitline region in a substrate, a first dielectric layer overlying the substrate substantially adjacent to and substantially exposing the bitline region, a charge trapping layer overlying the first dielectric layer substantially adjacent to and substantially exposing the bitline region, a bitline oxide isolation structure or layer extending continuously over the bitline region and charge trapping layer, the isolation structure comprising a single dielectric material layer formed by the radical oxidation process, and a conductive wordline overlying the bitline oxide isolation structure or layer.
摘要翻译：公开了用于制造多位SONOS闪速存储器单元的方法，包括在晶片的衬底上形成第一介电层和电荷俘获层，并选择性地蚀刻电介质并将陷阱层电荷捕获到衬底区域以形成位线开口，然后将掺杂剂离子物质注入与位线区域中的位线开口相关联的衬底中。然后使用自由基氧化工艺在电荷俘获层上形成三层介电电荷俘获 - 电介质堆叠的第二介电层，并填充晶片的位线区域中的位线开口。最后，在三层介电 - 电荷俘获 - 电介质堆叠和晶片的位线区域之后形成字线结构。还公开了一种多位闪存阵列，其包括衬底中的位线区域，覆盖衬底的基本上邻近并基本上暴露位线区域的第一电介质层，覆盖第一电介质层的电荷俘获层，其基本上邻近于并且基本上暴露位线区域，位线氧化物隔离结构或层，其在位线区域和电荷捕获层上连续延伸，所述隔离结构包括通过自由基氧化过程形成的单个电介质材料层，以及覆盖位线氧化物隔离结构的导电字线，层。

6. 发明申请

US20070058442A1 SONOS memory with inversion bit-lines 有权
标题翻译：具有反转位线的SONOS存储器
公开(公告)号：US20070058442A1
公开(公告)日：2007-03-15
申请号：US11595639
申请日：2006-11-10
申请人： Hidehiko Shiraiwa , Jaeyong Park , Satoshi Torii , Hideki Arakawa , Masaru Yano
发明人： Hidehiko Shiraiwa , Jaeyong Park , Satoshi Torii , Hideki Arakawa , Masaru Yano
IPC分类号： G11C16/04
CPC分类号： H01L29/792 , G11C16/0475 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A SONOS memory cell, formed within a semiconductor substrate, includes a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material. Furthermore, the SONOS memory cell includes a word-line gate structure disposed on the top dielectric and at least one bit-line gate for inducing at least one inversion bit-line within the semiconductor substrate.
摘要翻译：形成在半导体衬底内的SONOS存储单元包括设置在半导体衬底上的底部电介质，设置在底部电介质上的电荷捕获材料和设置在电荷俘获材料上的顶部电介质。此外，SONOS存储单元包括设置在顶部电介质上的字线栅极结构和用于在半导体衬底内引入至少一个反转位线的至少一个位线栅极。

7. 发明授权

US07151293B1 SONOS memory with inversion bit-lines 有权
公开(公告)号：US07151293B1
公开(公告)日：2006-12-19
申请号：US10928582
申请日：2004-08-27
申请人： Hidehiko Shiraiwa , Jaeyong Park , Satoshi Torii , Hideki Arakawa , Masaru Yano
发明人： Hidehiko Shiraiwa , Jaeyong Park , Satoshi Torii , Hideki Arakawa , Masaru Yano
IPC分类号： H01L29/72
CPC分类号： H01L29/792 , G11C16/0475 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A SONOS memory cell, formed within a semiconductor substrate, includes a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material. Furthermore, the SONOS memory cell includes a word-line gate structure disposed on the top dielectric and at least one bit-line gate for inducing at least one inversion bit-line within the semiconductor substrate.

8. 发明授权

US07067377B1 Recessed channel with separated ONO memory device 有权
标题翻译：嵌入式通道具有分离的ONO存储器件
公开(公告)号：US07067377B1
公开(公告)日：2006-06-27
申请号：US10812703
申请日：2004-03-30
申请人： Jaeyong Park , Hidehiko Shiraiwa , Satoshi Torii , Mark T. Ramsbey
发明人： Jaeyong Park , Hidehiko Shiraiwa , Satoshi Torii , Mark T. Ramsbey
IPC分类号： H01L21/336
CPC分类号： H01L29/42352 , H01L27/105 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： Systems and methods of fabricating a U-shaped memory device with a recessed channel and a segmented/separated ONO layer are provided. Multibit operation is facilitated by a separated ONO layer, which includes a charge trapping region on sidewalls of polysilicon gate structures adjacent to source/drain regions. Programming and erasing of the memory cells is facilitated by the relatively short distance between acting source regions and the gate. Additionally, short channel effects are mitigated by a relatively long U-shaped channel region that travels around the recessed polysilicon gate thereby adding a depth dimension to the channel length.
摘要翻译：提供了制造具有凹陷通道和分段/分离的ONO层的U形存储器件的系统和方法。通过分离的ONO层促进多位操作，该ONO层包括邻近源极/漏极区的多晶硅栅极结构的侧壁上的电荷俘获区域。存储器单元的编程和擦除由于作用源极区域和栅极之间的距离相对较短而便于实现。此外，通过在凹陷多晶硅栅极周围移动的相对较长的U形沟道区域减轻了短沟道效应，从而增加了沟道长度的深度尺寸。

9. 发明授权

US07052961B1 Method for forming wordlines having irregular spacing in a memory array 有权
标题翻译：用于形成在存储器阵列中具有不规则间隔的字线的方法
公开(公告)号：US07052961B1
公开(公告)日：2006-05-30
申请号：US11003574
申请日：2004-12-03
申请人： Hidehiko Shiraiwa , Jean Yee-Mei Yang , Jaeyong Park , Cyrus E. Tabery
发明人： Hidehiko Shiraiwa , Jean Yee-Mei Yang , Jaeyong Park , Cyrus E. Tabery
IPC分类号： H01L21/336 , H01L21/302
CPC分类号： H01L27/11568 , H01L21/0337 , H01L27/11521
摘要： According to one exemplary embodiment, a method of fabricating memory array includes forming a number of hard mask lines and at least one dummy hard mask line on a layer of polysilicon, where the at least one dummy hard mask line is situated in a bitline contact region of the memory array. The method further includes removing the at least one dummy hard mask line. According to this embodiment, the method further includes forming a number of wordlines, where each of the wordlines is situated under one of the hard mask lines, and where the bitline contact region causes an irregularity in spacing of the wordlines. Two of the wordlines are situated adjacent to the bitline contact region such that the spacing between the two wordlines is substantially equal to a width of the bit line contact region.
摘要翻译：根据一个示例性实施例，制造存储器阵列的方法包括在多晶硅层上形成多个硬掩模线和至少一个虚拟硬掩模线，其中至少一个虚拟硬掩模线位于位线接触区域的存储器阵列。该方法还包括移除至少一个虚拟硬掩模线。根据该实施例，该方法还包括形成多个字线，其中每个字线位于硬掩模线之一之下，并且其中位线接触区域引起字线间隔的不规则。两个字线位于与位线接触区域相邻的位置，使得两个字线之间的间隔基本上等于位线接触区域的宽度。

10. 发明授权

US06958511B1 Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen 有权
标题翻译：闪速存储器件及其制造方法，其包括具有不同氮浓度的两个区域的底部氧化物层
公开(公告)号：US06958511B1
公开(公告)日：2005-10-25
申请号：US10679774
申请日：2003-10-06
申请人： Arvind Halliyal , Amir H. Jafarpour , Hidehiko Shiraiwa , Tazrien Kamal , Mark Ramsbey , Jaeyong Park
发明人： Arvind Halliyal , Amir H. Jafarpour , Hidehiko Shiraiwa , Tazrien Kamal , Mark Ramsbey , Jaeyong Park
IPC分类号： H01L21/28 , H01L21/31 , H01L21/336 , H01L21/8238 , H01L29/51 , H01L29/76 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7923
摘要： Process of fabricating multi-bit charge trapping dielectric flash memory device, including forming on a semiconductor substrate a bottom oxide layer to define a substrate/oxide interface, in which the bottom oxide layer includes a first oxygen concentration and a first nitrogen concentration; and adding a quantity of nitrogen to the bottom oxide layer, whereby the bottom oxide layer includes a first region adjacent the charge storage layer and a second region adjacent the substrate/oxide interface, the second region having a second oxygen concentration and a second nitrogen concentration, in which the second nitrogen concentration exceeds the first nitrogen concentration, provided that the second nitrogen concentration does not exceed the second oxygen concentration. In one embodiment, the first nitrogen concentration is substantially zero.
摘要翻译：制造多位电荷俘获电介质闪存器件的方法，包括在半导体衬底上形成底部氧化物层以限定衬底/氧化物界面，其中底部氧化物层包括第一氧浓度和第一氮浓度; 并且向底部氧化物层添加一定量的氮，由此底部氧化物层包括与电荷存储层相邻的第一区域和与衬底/氧化物界面相邻的第二区域，第二区域具有第二氧浓度和第二氮浓度其中第二氮浓度超过第一氮浓度，条件是第二氮浓度不超过第二氧浓度。在一个实施方案中，第一氮浓度基本为零。

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