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1. 发明授权

US06653190B1 Flash memory with controlled wordline width 失效
标题翻译：具有受控字线宽度的闪存
公开(公告)号：US06653190B1
公开(公告)日：2003-11-25
申请号：US10023436
申请日：2001-12-15
申请人： Jean Y. Yang , Kouros Ghandehari , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Dawn M. Hopper , Angela T. Hui , Scott A. Bell
发明人： Jean Y. Yang , Kouros Ghandehari , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Dawn M. Hopper , Angela T. Hui , Scott A. Bell
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method of manufacturing for a MirrorBit® Flash memory includes depositing a charge-trapping material over a semiconductor substrate and implanting first and second bitlines in the semiconductor substrate. A wordline material is deposited over the charge-trapping dielectric material and a hard mask material deposited thereon. An anti-reflective coating (ARC) material is deposited on the hard mask material and a photoresist material is deposited on the ARC followed by processing the photoresist material and the ARC material to form a photomask of a patterned photoresist and a patterned ARC. The hard mask material is processed using the photomask to form a hard mask. The patterned photoresist is removed and then the patterned ARC without damaging the hard mask or the wordline material. The wordline material is processed using the hard mask to form a wordline and the hard mask is removed without damaging the wordline or the charge-trapping material.
摘要翻译：用于MirrorBit（闪存）闪存的制造方法包括在半导体衬底上沉积电荷捕获材料并在半导体衬底中注入第一和第二位线。字线材料沉积在电荷俘获电介质材料上并沉积在其上的硬掩模材料。将抗反射涂层（ARC）材料沉积在硬掩模材料上，并且将光致抗蚀剂材料沉积在ARC上，随后处理光致抗蚀剂材料和ARC材料以形成图案化光致抗蚀剂和图案化ARC的光掩模。使用光掩模处理硬掩模材料以形成硬掩模。去除图案化的光致抗蚀剂，然后去除图案化的ARC，而不损坏硬掩模或字线材料。使用硬掩模处理字线材料以形成字线，并且去除硬掩模而不损坏字线或电荷捕获材料。

2. 发明授权

US06479348B1 Method of making memory wordline hard mask extension 有权
标题翻译：制作内存字线硬掩模扩展的方法
公开(公告)号：US06479348B1
公开(公告)日：2002-11-12
申请号：US10109516
申请日：2002-08-27
申请人： Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey Shields , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Angela T. Hui
发明人： Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey Shields , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Angela T. Hui
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115
摘要： A manufacturing method is provided for an integrated circuit memory with closely spaced wordlines formed by using hard mask extensions. A charge-trapping dielectric material is deposited over a semiconductor substrate and first and second bitlines are formed therein. A wordline material and a hard mask material are deposited over the wordline material. A photoresist material is deposited over the hard mask material and is processed to form a patterned photoresist material. The hard mask material is processed using the patterned photoresist material to form a patterned hard mask material. The patterned photoresist is then removed. A hard mask extension material is deposited over the wordline material and is processed to form a hard mask extension. The wordline material is processed using the patterned hard mask material and the hard mask extension to form a wordline, and the patterned hard mask material and the hard mask extension are then removed.
摘要翻译：提供了一种用于通过使用硬掩模延伸部形成的具有紧密间隔的字线的集成电路存储器的制造方法。在半导体衬底上沉积电荷俘获电介质材料，并在其中形成第一和第二位线。字线材料和硬掩模材料沉积在字线材料上。光致抗蚀剂材料沉积在硬掩模材料上并被处理以形成图案化的光致抗蚀剂材料。使用图案化的光致抗蚀剂材料处理硬掩模材料以形成图案化的硬掩模材料。然后去除图案化的光致抗蚀剂。硬掩模延伸材料沉积在字线材料上并被处理以形成硬掩模延伸部。使用图案化的硬掩模材料和硬掩模延伸部来处理字线材料以形成字线，然后去除图案化的硬掩模材料和硬掩模延伸部。

3. 发明授权

US06617215B1 Memory wordline hard mask 有权
标题翻译：内存字线硬掩模
公开(公告)号：US06617215B1
公开(公告)日：2003-09-09
申请号：US10109235
申请日：2002-03-27
申请人： Arvind Halliyal , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang , Emmanuil Lingunis , Angela T. Hui , Jusuke Ogura
发明人： Arvind Halliyal , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang , Emmanuil Lingunis , Angela T. Hui , Jusuke Ogura
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L21/0332 , H01L21/32139 , H01L27/115
摘要： A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric material. First and second bitlines are implanted and a wordline material is deposited. A hard mask material is deposited over the wordline material. The hard mask material is of a material having the characteristic of being deposited rather than grown. A photoresist material is deposited over the wordline material and is patterned to form a patterned hard mask. The patterned photoresist material is removed. The wordline material is processed using the patterned hard mask to form a wordline. The patterned hard mask material is removed.
摘要翻译：用于MirrorBit（R）闪存的制造方法包括提供半导体衬底和沉积电荷俘获电介质材料。植入第一和第二位线，并存放字线材料。硬掩模材料沉积在字线材料上。硬掩模材料是具有沉积而不是生长的特征的材料。光致抗蚀剂材料沉积在字线材料上并被图案化以形成图案化的硬掩模。去除图案化的光致抗蚀剂材料。使用图案化的硬掩模处理字线材料以形成字线。去除图案化的硬掩模材料。

4. 发明授权

US06620717B1 Memory with disposable ARC for wordline formation 失效
标题翻译：具有一次性ARC用于字线形成的记忆
公开(公告)号：US06620717B1
公开(公告)日：2003-09-16
申请号：US10100487
申请日：2002-03-14
申请人： Tazrien Kamal , Scott A. Bell , Kouros Ghandehari , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang
发明人： Tazrien Kamal , Scott A. Bell , Kouros Ghandehari , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang
IPC分类号： H01L213205
CPC分类号： H01L27/11568 , H01L21/32139 , H01L27/115
摘要： A method of manufacturing for a Flash memory includes depositing a charge-trapping material over a semiconductor substrate and implanting first and second bitlines. A wordline material is deposited over the charge-trapping dielectric material and a hard mask material deposited. A disposable anti-reflective coating (ARC) material and a photoresist material are deposited followed by processing to form a patterned photoresist material and a patterned ARC material. The hard mask material is processed to form a patterned hard mask material. The patterned photoresist is removed and then the patterned ARC without damaging the patterned hard mask material or the wordline material. The wordline material is processed using the patterned hard mask material to form a wordline and the patterned hard mask material is removed without damaging the wordline or the charge-trapping dielectric material.
摘要翻译：一种用于闪速存储器的制造方法包括在半导体衬底上沉积电荷捕获材料并植入第一和第二位线。字线材料沉积在电荷捕获电介质材料上并沉积硬掩模材料。沉积一次性抗反射涂层（ARC）材料和光致抗蚀剂材料，然后进行处理以形成图案化的光致抗蚀剂材料和图案化的ARC材料。加工硬掩模材料以形成图案化的硬掩模材料。去除图案化的光致抗蚀剂，然后去除图案化的ARC，而不损坏图案化的硬掩模材料或字线材料。使用图案化的硬掩模材料处理字线材料以形成字线，并且去除图案化的硬掩模材料而不损坏字线或电荷捕获电介质材料。

5. 发明授权

US06720133B1 Memory manufacturing process using disposable ARC for wordline formation 失效
标题翻译：使用一次性ARC进行字线形成的存储器制造过程
公开(公告)号：US06720133B1
公开(公告)日：2004-04-13
申请号：US10126280
申请日：2002-04-19
申请人： Mark T. Ramsbey , Kouros Ghandehari , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa
发明人： Mark T. Ramsbey , Kouros Ghandehari , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa
IPC分类号： G03F700
CPC分类号： H01L27/11568 , H01L27/115 , Y10S430/151
摘要： A method of manufacturing an integrated circuit includes a semiconductor substrate having bitlines under a charge-trapping material over a core region and a gate insulator material over a periphery region. A wordline-gate material, a hard mask, and a first photoresist are deposited and patterned over the core region while covering the periphery region. After removing the first photoresist, wordlines are formed from the wordline-gate material in the core region. An anti-reflective coating and a second photoresist are deposited and patterned over the periphery region and covering the core region. The anti-reflective coating is removable without damaging the charge-trapping material. After removing the second photoresist and the anti-reflective coating, gates are formed from the wordline-gate material in the periphery region and the integrated circuit completed.
摘要翻译：集成电路的制造方法包括在芯区域上的电荷捕获材料下方具有位线的半导体衬底和在周边区域上的栅极绝缘体材料。在覆盖周边区域的同时，在芯区域上沉积并图案化字线栅极材料，硬掩模和第一光致抗蚀剂。在去除第一光致抗蚀剂之后，从芯区域中的字线栅极材料形成字线。在外围区域上沉积并图案化抗反射涂层和第二光致抗蚀剂并覆盖芯区域。防反射涂层是可去除的，而不会损坏电荷捕获材料。在去除第二光致抗蚀剂和抗反射涂层之后，栅极由周边区域中的字线栅极材料形成，并且集成电路完成。

6. 发明授权

US06884681B1 Method of manufacturing a semiconductor memory with deuterated materials 有权
标题翻译：用氘代材料制造半导体存储器的方法
公开(公告)号：US06884681B1
公开(公告)日：2005-04-26
申请号：US10672093
申请日：2003-09-26
申请人： Tazrien Kamal , Arvind Halliyal , Minh Van Ngo , Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino
发明人： Tazrien Kamal , Arvind Halliyal , Minh Van Ngo , Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino
IPC分类号： H01L21/336 , H01L21/8246
CPC分类号： H01L27/11568 , H01L29/66833
摘要： A method for manufacturing a MirrorBit® Flash memory includes providing a semiconductor substrate and successively depositing a first insulating layer, a charge-trapping layer, and a second insulating layer. First and second bitlines are implanted and wordlines are formed before completing the memory. Spacers are formed between the wordlines and an inter-layer dielectric layer is formed over the wordlines. One or more of the second insulating layer, wordlines, spacers, and inter-layer dielectric layers are deuterated, replacing hydrogen bonds with deuterium, thus improving data retention and substantially reducing charge loss.
摘要翻译：一种用于制造MirrorBit（闪存）闪存的方法包括：提供半导体衬底，并依次沉积第一绝缘层，电荷俘获层和第二绝缘层。植入第一和第二位线，并在完成内存之前形成字线。在字线之间形成间隔，并且在字线之间形成层间电介质层。第二绝缘层，字线，间隔层和层间电介质层中的一个或多个被氘化，用氘替代氢键，从而改善数据保留并显着降低电荷损失。

7. 发明授权

US06670241B1 Semiconductor memory with deuterated materials 有权
标题翻译：具有氘化材料的半导体存储器
公开(公告)号：US06670241B1
公开(公告)日：2003-12-30
申请号：US10128771
申请日：2002-04-22
申请人： Tazrien Kamal , Arvind Halliyal , Minh Van Ngo , Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino
发明人： Tazrien Kamal , Arvind Halliyal , Minh Van Ngo , Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L29/66833
摘要： A device and method for manufacturing thereof for a MirrorBit® Flash memory includes providing a semiconductor substrate and successively depositing a first insulating layer, a charge-trapping layer, and a second insulating layer. First and second bitlines are implanted and wordlines are formed before completing the memory. Spacers are formed between the wordlines and an inter-layer dielectric layer is formed over the wordlines. One or more of the second insulating layer, wordlines, spacers, and inter-layer dielectric layers are deuterated, replacing hydrogen bonds with deuterium, thus improving data retention and substantially reducing charge loss.
摘要翻译：用于制造MirrorBit（闪存）闪存的器件及其制造方法包括：提供半导体衬底，并依次沉积第一绝缘层，电荷俘获层和第二绝缘层。植入第一和第二位线，并在完成内存之前形成字线。在字线之间形成间隔，并且在字线之间形成层间电介质层。第二绝缘层，字线，间隔层和层间电介质层中的一个或多个被氘化，用氘替代氢键，从而改善数据保留并显着降低电荷损失。

8. 发明授权

US06927145B1 Bitline hard mask spacer flow for memory cell scaling 有权
标题翻译：位线硬掩模间隔流程用于存储单元缩放
公开(公告)号：US06927145B1
公开(公告)日：2005-08-09
申请号：US10770673
申请日：2004-02-02
申请人： Jean Y. Yang , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal , Emmanuil H. Lingunis
发明人： Jean Y. Yang , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal , Emmanuil H. Lingunis
IPC分类号： H01L21/027 , H01L21/761 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11568 , H01L27/115
摘要： The invention is a semiconductor device and a method of forming the semiconductor device. The semiconductor device comprises a substrate; buried bitlines formed in the substrate narrower than achievable at a resolution limit of lithography; a doped region formed adjacent at least one of the buried bitlines; a charge trapping layer disposed over the substrate; and a conductive layer disposed over the charge trapping layer, wherein the doped region adjacent the least one of the buried bitlines inhibits a leakage current between the buried bitlines.
摘要翻译：本发明是半导体器件和形成半导体器件的方法。半导体器件包括衬底; 在衬底中形成的掩埋位线比在光刻的分辨率极限下可实现的更窄; 与所述掩埋位线中的至少一个相邻地形成的掺杂区域; 设置在所述基板上的电荷捕获层; 以及设置在所述电荷俘获层上的导电层，其中与所述掩埋位线中的至少一个相邻的所述掺杂区域抑制所述掩埋位线之间的漏电流。

9. 发明授权

US08673716B2 Memory manufacturing process with bitline isolation 有权
标题翻译：内存制造过程采用位线隔离
公开(公告)号：US08673716B2
公开(公告)日：2014-03-18
申请号：US10118732
申请日：2002-04-08
申请人： Mark T. Ramsbey , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Yu Sun
发明人： Mark T. Ramsbey , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Yu Sun
IPC分类号： H01L21/8247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A wordline and gate are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate around the gate, and the gate is implanted with a gate doping implantation in the periphery region and not in the core region.
摘要翻译：集成电路的制造方法具有具有芯区域和周边区域的半导体基板。在芯区域中沉积电荷捕获电介质层，并且在周边区域中沉积栅极电介质层。位线在芯区域中的半导体衬底中而不是在周边区域中形成。在芯区域而不是周边区域中形成并注入掺杂剂的字线栅层。形成了一条字和门。源极/漏极结在栅极周围的半导体衬底中注入掺杂剂，栅极注入栅极掺杂注入在外围区域而不在核心区域。

10. 发明授权

US07018868B1 Disposable hard mask for memory bitline scaling 有权
标题翻译：用于存储器位线缩放的一次性硬掩模
公开(公告)号：US07018868B1
公开(公告)日：2006-03-28
申请号：US10770245
申请日：2004-02-02
申请人： Jean Y. Yang , Jeff P. Erhardt , Cyrus Tabery , Weidong Qian , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal
发明人： Jean Y. Yang , Jeff P. Erhardt , Cyrus Tabery , Weidong Qian , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal
IPC分类号： H01L21/44
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： The invention is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes buried bitlines in a semiconductor substrate. Additionally, doped regions are formed adjacent the buried bitlines. The doped regions adjacent the buried bitlines inhibit a leakage current between the buried bitlines.
摘要翻译：本发明是半导体器件和半导体器件的制造方法。半导体器件包括在半导体衬底中的掩埋位线。此外，掺杂区域形成在掩埋位线附近。与掩埋位线相邻的掺杂区域可以防止掩埋位线之间的漏电流。

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