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1. 发明授权

US09710664B2 Security layer and methods for protecting tenant data in a cloud-mediated computing network 有权
公开(公告)号：US09710664B2
公开(公告)日：2017-07-18
申请号：US13606979
申请日：2012-09-07
申请人： Shiju Sathyadevan , P. Venkat Rangan , Krishnashree Achuthan
发明人： Shiju Sathyadevan , P. Venkat Rangan , Krishnashree Achuthan
IPC分类号： G06F7/04 , G06F21/62 , G06F21/55 , G06F17/30
CPC分类号： G06F21/6218 , G06F21/554
摘要： A system for protecting data managed in a cloud-computing network from malicious data operations includes an Internet-connected server and software executing on the server from a non-transitory physical medium, the software providing a first function for generating one or more security tokens that validate one or more computing operations to be performed on the data, a second function for generating a hash for each token generated, the hash detailing, in a secure fashion, the operation type or types permitted by the one or more tokens, a third function for brokering two-party signature of the one or more tokens, and a fourth function for dynamically activating the one or more signed tokens for a specific time window required to perform the operations permitted by the token.

2. 发明申请

US20060223278A1 Non-critical complementary masking method for poly-1 definition in flash memory device fabrication 有权
标题翻译：闪存器件制造中poly-1定义的非关键互补掩模方法
公开(公告)号：US20060223278A1
公开(公告)日：2006-10-05
申请号：US11099339
申请日：2005-04-04
申请人： Unsoon Kim , Hiroyuki Kinoshita , Yu Sun , Krishnashree Achuthan , Christopher Raeder , Christopher Foster , Harpreet Sachar , Kashmir Sahota
发明人： Unsoon Kim , Hiroyuki Kinoshita , Yu Sun , Krishnashree Achuthan , Christopher Raeder , Christopher Foster , Harpreet Sachar , Kashmir Sahota
IPC分类号： H01L21/76
CPC分类号： H01L27/105 , H01L21/3212 , H01L21/32139 , H01L21/76229 , H01L27/1052 , H01L27/11526 , H01L27/11543 , H01L27/11568
摘要： A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.
摘要翻译：公开了一种用于在半导体晶片中定义多晶硅层的方法。使用非临界掩模在聚-1沉积之前将外围的场氧化物凹入等于最终聚-1厚度的量。使用互补的非关键掩模来允许芯的CMP将浅层隔离沟的核心氧化物台面的顶部暴露出来。

3. 发明申请

US20050118824A1 Multi-step chemical mechanical polishing of a gate area in a FinFET 有权
标题翻译： FinFET中栅极区域的多步化学机械抛光
公开(公告)号：US20050118824A1
公开(公告)日：2005-06-02
申请号：US11030191
申请日：2005-01-07
申请人： Krishnashree Achuthan , Shibly Ahmed , Haihong Wang , Bin Yu
发明人： Krishnashree Achuthan , Shibly Ahmed , Haihong Wang , Bin Yu
IPC分类号： C09G1/02 , H01L21/3105 , H01L21/321 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/786 , H01L21/00 , H01L21/302 , H01L21/3205 , H01L21/461 , H01L21/4763 , H01L21/84
CPC分类号： H01L29/785 , C09G1/02 , H01L21/31053 , H01L21/3212 , H01L29/42384 , H01L29/4908 , H01L29/66795 , H01L29/6681 , Y10S438/959
摘要： A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.
摘要翻译：制造MOSFET型半导体器件的方法包括平坦化沉积在沟道上的栅极材料层。平面化在包括初始“粗糙”平坦化然后是“精细”平坦化的多步骤过程中进行。用于更精细平坦化的浆料可以包括倾向于粘附到栅极材料的低区域的添加材料。

4. 发明授权

US06770523B1 Method for semiconductor wafer planarization by CMP stop layer formation 失效
标题翻译：通过CMP停止层形成的半导体晶片平面化方法
公开(公告)号：US06770523B1
公开(公告)日：2004-08-03
申请号：US10190397
申请日：2002-07-02
申请人： Kashmir S. Sahota , Jeffrey P. Erhardt , Arvind Halliyal , Minh Van Ngo , Krishnashree Achuthan
发明人： Kashmir S. Sahota , Jeffrey P. Erhardt , Arvind Halliyal , Minh Van Ngo , Krishnashree Achuthan
IPC分类号： H01L218238
CPC分类号： H01L21/76229 , H01L21/31053
摘要： A method of manufacturing an integrated circuit is provided having a semiconductor wafer. A chemical-mechanical polishing stop layer is deposited on the semiconductor wafer and a first photoresist layer is processed over the chemical-mechanical polishing stop layer. The chemical-mechanical polishing stop layer and the semiconductor wafer are patterned to form a shallow trench and a shallow trench isolation material is deposited on the chemical-mechanical polishing stop layer and in the shallow trench. A second photoresist layer is processed over the shallow trench isolation material leaving the shallow trench uncovered. The uncovered shallow trench is then treated to become a chemical-mechanical polishing stop area. The shallow trench isolation material is then chemical-mechanical polished to be co-planar with the chemical-mechanical stop layer and the chemical-mechanical polishing stop treated area.
摘要翻译：提供了具有半导体晶片的集成电路的制造方法。化学机械抛光停止层沉积在半导体晶片上，并且在化学机械抛光停止层上处理第一光致抗蚀剂层。化学机械抛光停止层和半导体晶片被图案化以形成浅沟槽，浅沟槽隔离材料沉积在化学机械抛光停止层和浅沟槽中。在浅沟槽隔离材料上处理第二光致抗蚀剂层，留下未覆盖的浅沟槽。然后将未覆盖的浅沟槽处理成为化学机械抛光停止区域。然后将浅沟槽隔离材料进行化学机械抛光以与化学 - 机械停止层和化学 - 机械抛光停止处理区共面。

5. 发明授权

US06472310B1 Tin palladium activation with maximized nuclei density and uniformity on barrier material in interconnect structure 有权
标题翻译：锡钯活化，在互连结构中的阻挡材料上具有最大的核密度和均匀性
公开(公告)号：US06472310B1
公开(公告)日：2002-10-29
申请号：US10118511
申请日：2002-04-08
申请人： Krishnashree Achuthan , Sergey Lopatin
发明人： Krishnashree Achuthan , Sergey Lopatin
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76873 , H01L2221/1089 , Y10S977/701 , Y10S977/712 , Y10S977/721
摘要： For fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, a layer of diffusion barrier material is formed on at least one wall of the interconnect opening. An activation layer comprised of palladium is formed on the layer of diffusion barrier material when the interconnect opening is immersed in an activation bath comprised of tin ions and palladium ions. The tin ions have a tin ion concentration in the activation bath that is greater than a palladium ion concentration in the activation bath. A layer of seed material is deposited on the activation layer in an electroless deposition process, and the interconnect opening is filled with a conductive fill material grown from the layer of seed material. A layer of silicon rich material may be formed on the layer of diffusion barrier material before deposition of the activation layer such that the activation layer is formed on the layer of silicon rich material. In that case, a ratio of the tin ion concentration to the palladium ion concentration in the activation bath is adjusted to decrease with an amount of silicon atoms of the layer of silicon rich material deposited on the layer of diffusion barrier material. The present invention may be practiced to particular advantage when the layer of seed material and the conductive fill material are comprised of copper.
摘要翻译：为了制造形成在由电介质材料包围的互连开口内的互连结构，在互连开口的至少一个壁上形成扩散阻挡材料层。当互连开口浸入由锡离子和钯离子组成的活化浴中时，在扩散阻挡材料层上形成由钯构成的活化层。锡离子在活化浴中的锡离子浓度大于活化浴中的钯离子浓度。一种种子材料在无电沉积工艺中沉积在活化层上，并且互连开口填充有从种子材料层生长的导电填充材料。可以在沉积激活层之前在扩散阻挡材料层上形成富硅材料层，使得活化层形成在富硅材料层上。在这种情况下，调节活化浴中锡离子浓度与钯离子浓度的比例，随着沉积在扩散阻挡材料层上的富硅材料层的硅原子量而减小。当种子材料层和导电填充材料由铜组成时，本发明可以特别有利。

6. 发明申请

US20140075568A1 Security Layer and Methods for Protecting Tenant Data in a Cloud-Mediated Computing Network 有权
标题翻译：用于保护云计算网络中的租户数据的安全层和方法
公开(公告)号：US20140075568A1
公开(公告)日：2014-03-13
申请号：US13606979
申请日：2012-09-07
申请人： Shiju Sathyadevan , P. Venkat Rangan , Krishnashree Achuthan
发明人： Shiju Sathyadevan , P. Venkat Rangan , Krishnashree Achuthan
IPC分类号： G06F21/24
CPC分类号： G06F21/6218 , G06F21/554
摘要： A system for protecting data managed in a cloud-computing network from malicious data operations includes an Internet-connected server and software executing on the server from a non-transitory physical medium, the software providing a first function for generating one or more security tokens that validate one or more computing operations to be performed on the data, a second function for generating a hash for each token generated, the hash detailing, in a secure fashion, the operation type or types permitted by the one or more tokens, a third function for brokering two-party signature of the one or more tokens, and a fourth function for dynamically activating the one or more signed tokens for a specific time window required to perform the operations permitted by the token.
摘要翻译：用于保护在云计算网络中管理的数据免受恶意数据操作的系统包括互联网连接的服务器和从非暂时物理介质在服务器上执行的软件，该软件提供用于生成一个或多个安全令牌的第一功能，验证要对数据执行的一个或多个计算操作，用于为所生成的每个令牌生成散列的第二功能，以安全的方式，所述一个或多个令牌允许的操作类型或类型的散列细节，第三功能用于代理一个或多个令牌的两方签名，以及用于在执行令牌所允许的操作所需的特定时间窗口中动态激活一个或多个签名令牌的第四功能。

7. 发明授权

US07358191B1 Method for decreasing sheet resistivity variations of an interconnect metal layer 有权
标题翻译：降低互连金属层的薄层电阻率变化的方法
公开(公告)号：US07358191B1
公开(公告)日：2008-04-15
申请号：US11388390
申请日：2006-03-24
申请人： Krishnashree Achuthan , Brad Davis , James Xie , Kashmir Sahota
发明人： Krishnashree Achuthan , Brad Davis , James Xie , Kashmir Sahota
IPC分类号： H01L21/311
CPC分类号： H01L21/3212 , H01L21/7684
摘要： According to one exemplary embodiment, a method includes a step of forming a number of trenches in a dielectric layer, where the dielectric layer is situated over a wafer. The method further includes forming a metal layer over the dielectric layer and in the trenches such that the metal layer has a dome-shaped profile over the wafer. The method further includes performing a planarizing process to form a number of interconnect lines, where each of the interconnect lines is situated in one of the trenches. The dome-shaped profile of the metal layer causes the interconnect lines to have a reduced thickness variation across the wafer after performing the planarizing process. The interconnect lines are situated in an interconnect metal layer, where the dome-shaped profile of the metal layer causes the interconnect metal layer to have increased sheet resistivity uniformity across the wafer after performing the planarizing process.
摘要翻译：根据一个示例性实施例，一种方法包括在电介质层中形成多个沟槽的步骤，其中电介质层位于晶片之上。该方法还包括在电介质层上和沟槽中形成金属层，使得金属层在晶片上具有圆顶形轮廓。该方法还包括执行平面化处理以形成多个互连线，其中每个互连线位于沟槽中的一个中。在执行平坦化处理之后，金属层的圆顶形轮廓使得互连线在晶片上具有减小的厚度变化。互连线位于互连金属层中，其中金属层的圆顶形轮廓使得互连金属层在执行平坦化处理之后在晶片上具有增加的片电阻率均匀性。

8. 发明授权

US06812076B1 Dual silicon layer for chemical mechanical polishing planarization 失效
标题翻译：双层硅化学机械抛光平面化
公开(公告)号：US06812076B1
公开(公告)日：2004-11-02
申请号：US10752691
申请日：2004-01-08
申请人： Krishnashree Achuthan , Shibly S. Ahmed , Haihong Wang , Bin Yu
发明人： Krishnashree Achuthan , Shibly S. Ahmed , Haihong Wang , Bin Yu
IPC分类号： H01L2972
CPC分类号： H01L29/785 , H01L21/3212 , H01L29/4908 , H01L29/66795 , H01L29/6681
摘要： A FinFet-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.
摘要翻译： FinFet型半导体器件包括翅片结构，其上形成相对薄的非晶硅层，然后形成未掺杂的多晶硅层。半导体器件可以使用化学机械抛光（CMP）进行平面化，其中非晶硅层用作阻挡层以防止损坏鳍结构。

9. 发明授权

US06610577B1 Self-aligned polysilicon polish 有权
标题翻译：自对准多晶硅抛光
公开(公告)号：US06610577B1
公开(公告)日：2003-08-26
申请号：US10150204
申请日：2002-05-15
申请人： Jack F. Thomas , Unsoon Kim , Krishnashree Achuthan
发明人： Jack F. Thomas , Unsoon Kim , Krishnashree Achuthan
IPC分类号： H01L218247
CPC分类号： H01L27/11526 , H01L21/28273 , H01L21/3212 , H01L27/11521 , H01L27/11531 , H01L29/66825
摘要： A method for removing polysilicon from isolation regions on a substrate during semiconductor fabrication is disclosed. The method includes depositing a layer of polysilicon over the substrate, and depositing at least one dielectric layer over the polysilicon. The method further includes polishing the polysilicon from the isolation regions, wherein the dielectric layers act as a polishing stop, resulting in regions of polysilicon that are self-aligned to the trench isolation regions.
摘要翻译：公开了一种用于在半导体制造期间从衬底上的隔离区域去除多晶硅的方法。该方法包括在衬底上沉积多晶硅层，以及在多晶硅上沉积至少一个电介质层。该方法还包括从隔离区域抛光多晶硅，其中介电层用作抛光停止，从而产生与沟槽隔离区自对准的多晶硅区域。

10. 发明授权

US06426297B1 Differential pressure chemical-mechanical polishing in integrated circuit interconnects 有权
标题翻译：集成电路互连中的差压化学机械抛光
公开(公告)号：US06426297B1
公开(公告)日：2002-07-30
申请号：US09905296
申请日：2001-07-13
申请人： Kashmir S. Sahota , Krishnashree Achuthan , Sergey D. Lopatin
发明人： Kashmir S. Sahota , Krishnashree Achuthan , Sergey D. Lopatin
IPC分类号： H01L21382
CPC分类号： H01L21/7684 , B24B37/042 , B24B49/16 , H01L21/3212
摘要： A method is provided for manufacturing an integrated circuit having a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor wafer and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening and a conductor core is deposited to fill the channel opening over the barrier layer. The semiconductor wafer is then subjected to chemical-mechanical polishing using a differential pressure between the center of the semiconductor wafer and its periphery.
摘要翻译：提供了一种用于制造具有半导体器件的半导体衬底的集成电路的方法。在半导体晶片上形成电介质层，并在电介质层中形成开口。沉积阻挡层以对开口进行排列，并且沉积导体芯以填充阻挡层上的通道开口。然后使用半导体晶片的中心与其周边之间的压差对半导体晶片进行化学机械抛光。

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