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1. 发明授权

US07135396B1 Method of making a semiconductor structure 有权
标题翻译：制造半导体结构的方法
公开(公告)号：US07135396B1
公开(公告)日：2006-11-14
申请号：US10939775
申请日：2004-09-13
申请人： Calvin T. Gabriel , Jeffrey Shields
发明人： Calvin T. Gabriel , Jeffrey Shields
IPC分类号： H01L21/44 , H01L21/4763 , H01L31/00 , H01L29/00 , H01L23/48
CPC分类号： H01L21/76838 , H01L21/32136
摘要： Methods of making a semiconductor structure are disclosed. A refractory metal layer containing W, TiW, Ta, or TaN and semiconductor layer are formed on a substrate that contains copper in, for example, a via therein. A portion of the refractory metal layer and semiconductor layer is removed by etching using a fluorine-containing compound. By using W, TiW, Ta, or TaN as the refractory metal layer material and employing fluorine-based etching, the copper portion in the substrate is not substantially etched, thus preventing corrosion of the copper portion.
摘要翻译：公开了制造半导体结构的方法。含有W，TiW，Ta或TaN的难熔金属层和半导体层形成在例如其中通孔中含有铜的基板上。通过使用含氟化合物的蚀刻除去难熔金属层和半导体层的一部分。通过使用W，TiW，Ta或TaN作为难熔金属层材料并且使用氟基蚀刻，基板中的铜部分基本上不被蚀刻，从而防止铜部分的腐蚀。

2. 发明申请

US20060102887A1 Protection of active layers of memory cells during processing of other elements 有权
标题翻译：在处理其他元件期间保护存储器单元的有源层
公开(公告)号：US20060102887A1
公开(公告)日：2006-05-18
申请号：US10987262
申请日：2004-11-12
申请人： Steven Avanzino , Igor Sokolik , Suzette Pangrle , Nicholas Tripsas , Jeffrey Shields
发明人： Steven Avanzino , Igor Sokolik , Suzette Pangrle , Nicholas Tripsas , Jeffrey Shields
IPC分类号： H01L29/02
CPC分类号： H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： A method of fabricating an electronic structure by providing a conductive layer, providing a dielectric layer over the conductive layer, providing first and second openings through the dielectric layer, providing first and second conductive bodies in the first and second openings respectively and in contact with the conductive layer, providing a memory structure over the first conductive body, providing a protective element over the memory structure, and undertaking processing on the second conductive body.
摘要翻译：一种通过提供导电层制造电子结构的方法，在导电层上提供电介质层，提供通过介电层的第一和第二开口，分别在第一和第二开口中提供第一和第二导电体，并与在第一导电体上提供存储结构，在存储器结构上提供保护元件，并对第二导电体进行处理。

3. 发明申请

US20130062587A1 Resistive Switching Devices Having Alloyed Electrodes And Methods of Formation Thereof 有权
标题翻译：具有合金电极的电阻式开关器件及其形成方法
公开(公告)号：US20130062587A1
公开(公告)日：2013-03-14
申请号：US13558296
申请日：2012-07-25
申请人： Wei Ti Lee , Chakravarthy Gopalan , Yi Ma , Jeffrey Shields , Philippe Blanchard , John Ross Jameson , Foroozan Sarah Koushan , Janet Wang , Mark Kellam
发明人： Wei Ti Lee , Chakravarthy Gopalan , Yi Ma , Jeffrey Shields , Philippe Blanchard , John Ross Jameson , Foroozan Sarah Koushan , Janet Wang , Mark Kellam
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1658
摘要： In accordance with an embodiment of the present invention, a resistive switching device comprises a bottom electrode, a switching layer disposed over the bottom electrode, and a top electrode disposed over the switching layer. The top electrode comprises an alloy of a memory metal and an alloying element. The top electrode provides a source of the memory metal. The memory metal is configured to change a state of the switching layer.
摘要翻译：根据本发明的实施例，电阻式开关装置包括底电极，设置在底电极上的开关层和设置在开关层上的顶电极。顶部电极包括记忆金属和合金元素的合金。顶部电极提供存储金属的源。存储器金属被配置为改变开关层的状态。

4. 发明授权

US07468296B1 Thin film germanium diode with low reverse breakdown 有权
标题翻译：薄膜锗二极管具有低反向击穿功能
公开(公告)号：US07468296B1
公开(公告)日：2008-12-23
申请号：US11290787
申请日：2005-11-30
申请人： Ercan Adem , Matthew Buynoski , Robert Chiu , Bryan Choo , Calvin Gabriel , Joong Jeon , David Matsumoto , Jeffrey Shields , Bhanwar Singh , Winny Stockwell , Wen Yu
发明人： Ercan Adem , Matthew Buynoski , Robert Chiu , Bryan Choo , Calvin Gabriel , Joong Jeon , David Matsumoto , Jeffrey Shields , Bhanwar Singh , Winny Stockwell , Wen Yu
IPC分类号： H01L21/8234 , H01L27/10
CPC分类号： H01L27/1021
摘要： In fabricating an electronic structure, a substrate is provided, and a first barrier layer is provided on the substrate. A germanium thin film diode is provided on the first barrier layer, and a second barrier layer is provided on the germanium thin film diode. A memory device is provided over and connected to the second barrier layer.
摘要翻译：在制造电子结构时，提供基板，并且在基板上设置第一阻挡层。锗薄膜二极管设置在第一阻挡层上，第二阻挡层设置在锗薄膜二极管上。存储器件设置在第二阻挡层上并连接到第二阻挡层。

5. 发明授权

US07199416B1 Systems and methods for a memory and/or selection element formed within a recess in a metal line 有权
标题翻译：用于存储和/或选择元件的系统和方法，其形成在金属线中的凹槽内
公开(公告)号：US07199416B1
公开(公告)日：2007-04-03
申请号：US10985172
申请日：2004-11-10
申请人： Nicholas H. Tripsas , Minh Tran , Jeffrey Shields
发明人： Nicholas H. Tripsas , Minh Tran , Jeffrey Shields
IPC分类号： H01L27/108 , H01L23/58
CPC分类号： H01L27/1021 , H01L2924/0002 , H01L2924/00
摘要： The subject invention provides systems and methodologies for fabrication of memory and/or selection (e.g., diodes) elements in a recession in a semiconductor layer. In particular, a trench of varying width is created in the semiconductor layer by employing various etching techniques. A metal film can be deposited in the trench according to a desired deposition thickness in order to seam close a narrow portion of the trench while form a dimple in a wide portion of the trench. The trench, after metal film deposition, exhibits a depression in wider trench portions relative to narrow trench portions. The depression can be utilized by placing one or more memory or selection layers in the depression, and a via can be formed over a portion of the trench to form an interconnect.
摘要翻译：本发明提供了用于制造半导体层中的凹陷中的存储器和/或选择（例如，二极管）元件的系统和方法。特别地，通过采用各种蚀刻技术在半导体层中产生不同宽度的沟槽。可以根据期望的沉积厚度在沟槽中沉积金属膜，以便在沟槽的宽部分形成凹坑的同时缝合沟槽的窄部分。在金属膜沉积之后，沟槽相对于窄沟槽部分在较宽的沟槽部分中呈凹陷。可以通过将一个或多个存储器或选择层放置在凹陷中来利用凹陷，并且可以在沟槽的一部分上形成通孔以形成互连。

6. 发明授权

US08866122B1 Resistive switching devices having a buffer layer and methods of formation thereof 有权
标题翻译：具有缓冲层的电阻式开关器件及其形成方法
公开(公告)号：US08866122B1
公开(公告)日：2014-10-21
申请号：US13517653
申请日：2012-06-14
申请人： Wei Ti Lee , Chakravarthy Gopalan , Yi Ma , Kuei-Chang Tsai , Jeffrey Shields , Janet Wang
发明人： Wei Ti Lee , Chakravarthy Gopalan , Yi Ma , Kuei-Chang Tsai , Jeffrey Shields , Janet Wang
IPC分类号： H01L47/00
CPC分类号： H01L45/143 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1675 , H01L45/1683
摘要： In one embodiment, a resistive switching device includes a bottom electrode, a switching layer, a buffer layer, and a top electrode. The switching layer is disposed over the bottom electrode. The buffer layer is disposed over the switching layer and provides a buffer of ions of a memory metal. The buffer layer includes an alloy of the memory metal with an alloying element, which includes antimony, tin, bismuth, aluminum, germanium, silicon, or arsenic. The top electrode is disposed over the buffer layer and provides a source of the memory metal.
摘要翻译：在一个实施例中，电阻式开关器件包括底部电极，开关层，缓冲层和顶部电极。开关层设置在底部电极上。缓冲层设置在开关层上并提供存储金属离子的缓冲液。缓冲层包括记忆金属与含有锑，锡，铋，铝，锗，硅或砷的合金元素的合金。顶部电极设置在缓冲层上方并提供存储金属的源。

7. 发明授权

US08847192B2 Resistive switching devices having alloyed electrodes and methods of formation thereof 有权
标题翻译：具有合金电极的电阻式开关器件及其形成方法
公开(公告)号：US08847192B2
公开(公告)日：2014-09-30
申请号：US13558296
申请日：2012-07-25
申请人： Wei Ti Lee , Chakravarthy Gopalan , Yi Ma , Jeffrey Shields , Philippe Blanchard , John Ross Jameson , Foroozan Sarah Koushan , Janet Wang , Mark Kellam
发明人： Wei Ti Lee , Chakravarthy Gopalan , Yi Ma , Jeffrey Shields , Philippe Blanchard , John Ross Jameson , Foroozan Sarah Koushan , Janet Wang , Mark Kellam
IPC分类号： H01L47/00 , H01L45/00
CPC分类号： H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1658
摘要： In accordance with an embodiment of the present invention, a resistive switching device comprises a bottom electrode, a switching layer disposed over the bottom electrode, and a top electrode disposed over the switching layer. The top electrode comprises an alloy of a memory metal and an alloying element. The top electrode provides a source of the memory metal. The memory metal is configured to change a state of the switching layer.
摘要翻译：根据本发明的实施例，电阻式开关装置包括底电极，设置在底电极上的开关层和设置在开关层上的顶电极。顶部电极包括记忆金属和合金元素的合金。顶部电极提供存储金属的源。存储器金属被配置为改变开关层的状态。

8. 发明授权

US07476604B1 Aggressive cleaning process for semiconductor device contact formation 有权
标题翻译：用于半导体器件接触形成的积极清洁工艺
公开(公告)号：US07476604B1
公开(公告)日：2009-01-13
申请号：US11128391
申请日：2005-05-13
申请人： Ning Cheng , Minh Van Ngo , Jinsong Yin , Paul Raymond Besser , Connie Pin-chin Wang , Russell Rosaire Austin Callahan , Jeffrey Shields , Shankar Sinha , Jeff P. Erhardt , Jeremy Chi-Hung Chou
发明人： Ning Cheng , Minh Van Ngo , Jinsong Yin , Paul Raymond Besser , Connie Pin-chin Wang , Russell Rosaire Austin Callahan , Jeffrey Shields , Shankar Sinha , Jeff P. Erhardt , Jeremy Chi-Hung Chou
IPC分类号： H01L21/44
CPC分类号： H01L21/76831 , H01L21/02063 , H01L21/28518 , H01L21/76814 , H01L21/76843 , H01L21/76855
摘要： A method of forming a contact through a material includes forming a via through a dielectric material and cleaning the via using a dilute hydrofluoric (DHF) acid solution. The method further includes depositing a barrier layer within the via and depositing metal adjacent the barrier layer.
摘要翻译：通过材料形成接触的方法包括通过电介质材料形成通孔，并使用稀氢氟酸（DHF）酸溶液清洗通孔。所述方法还包括在所述通孔内沉积阻挡层并在所述阻挡层附近沉积金属。

9. 发明申请

US20070140008A1 Independently programmable memory segments within an NMOS electrically erasable programmable read only memory array achieved by P-well separation and method therefor 审中-公开
标题翻译：通过P阱分离实现的NMOS电可擦除可编程只读存储器阵列中的独立可编程存储器段及其方法
公开(公告)号：US20070140008A1
公开(公告)日：2007-06-21
申请号：US11314504
申请日：2005-12-21
申请人： Jeffrey Shields , Kent Hewitt , Donald Gerber , Randy Yach
发明人： Jeffrey Shields , Kent Hewitt , Donald Gerber , Randy Yach
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： H01L27/115 , G11C16/0425 , H01L27/11521 , H01L27/11524
摘要： An array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.
摘要翻译： N沟道存储器单元的阵列可以通过在其上制造存储器段的多个电隔离的P阱分离成独立可编程的存储器段。多个电隔离的P阱可以例如通过p-n结隔离或电介质隔离来产生。

10. 发明授权

US06479348B1 Method of making memory wordline hard mask extension 有权
标题翻译：制作内存字线硬掩模扩展的方法
公开(公告)号：US06479348B1
公开(公告)日：2002-11-12
申请号：US10109516
申请日：2002-08-27
申请人： Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey Shields , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Angela T. Hui
发明人： Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey Shields , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Angela T. Hui
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115
摘要： A manufacturing method is provided for an integrated circuit memory with closely spaced wordlines formed by using hard mask extensions. A charge-trapping dielectric material is deposited over a semiconductor substrate and first and second bitlines are formed therein. A wordline material and a hard mask material are deposited over the wordline material. A photoresist material is deposited over the hard mask material and is processed to form a patterned photoresist material. The hard mask material is processed using the patterned photoresist material to form a patterned hard mask material. The patterned photoresist is then removed. A hard mask extension material is deposited over the wordline material and is processed to form a hard mask extension. The wordline material is processed using the patterned hard mask material and the hard mask extension to form a wordline, and the patterned hard mask material and the hard mask extension are then removed.
摘要翻译：提供了一种用于通过使用硬掩模延伸部形成的具有紧密间隔的字线的集成电路存储器的制造方法。在半导体衬底上沉积电荷俘获电介质材料，并在其中形成第一和第二位线。字线材料和硬掩模材料沉积在字线材料上。光致抗蚀剂材料沉积在硬掩模材料上并被处理以形成图案化的光致抗蚀剂材料。使用图案化的光致抗蚀剂材料处理硬掩模材料以形成图案化的硬掩模材料。然后去除图案化的光致抗蚀剂。硬掩模延伸材料沉积在字线材料上并被处理以形成硬掩模延伸部。使用图案化的硬掩模材料和硬掩模延伸部来处理字线材料以形成字线，然后去除图案化的硬掩模材料和硬掩模延伸部。

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